目录

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1 ASIC Ambit Ambit Ambit Silicon Ensemble Silicon Ensemble Silicon Ensemble 3.4 SE PKS(Physical knowledge synthesis) PKSSPnR

2 VHDL Cadence Ambit Cadence Silicon Ensemble Cadence PKS (Physical knowledge synthesis) Ambit 3 Silicon Ensemble 4 AmbitSilicon Ensemble PKS floorplanambit Silicon EnsemblePKS(Physical knowledge synthesis) 1

3 1.1 ASIC VLSI ULSI EDA 80 Very High Speed Integrated Circiut VHDL Cadence Verilog HDL HDL RTL HDL RTL ECO CLOCK TREE 2

4 1. 2. ASIC ASIC ASIC 5. 6 ASIC

5 1.1 ASIC 4

6 1.2 RTLHDL ASIC (synthesis) RTL HDL = + + ( Synthesis = Translation + Optimization + Mapping ) ( 1.2 ) 1.2 5

7 Synopsys 2000 Synopsys Synopsys Physical Synthesis IC Candence PKS(Physical knowledge Synthesis) Candence PKS Physical Synthesis 6

8 Ambit = + + ( Synthesis = Translation + Optimization + Mapping ) Ambit 2.1 Ambit Ambit 7

9 2.2 Ambit Ambit TCL Shell, ac_shell Ambit -navigates, navigates ac_shell gui navigates Ambit 2.3 navigates navigates HTML ac_shell ac_shell help <command name> Ambit Verilog VHDL RTL Verilog VHDL Ambit Data Base(ADB) SDF SDF (IOPATH/INTERCONNECT) write_assertions PDEF RC EDIF GCF

10 ambit report_timing report_area report_hierarchy report_design_rule_violations report_library report_net report_fanin report_fanout report_fsm Ambit 2.3 Ambit VHDL Verilog HDL Ambit Ambit ac_shell ac_shell gui navigates read_tlf csmc06core.tlf csmc06core.tlf 0.6um set_global target_technology csmco6core.tlf 9

11 2.3.4 RTL RTL HDL Verilog read_verilog filename VHDLread_vhdl filename RTL do_build_generic do_bu ( ) 2.4 do_build_generic 2.4 Control Data Flow Graphs CDFGs ATL ACL Ambit set_current_module mod_name 10

12 set_top_timing_module mod_name set_clock IDEAL_CLOCK period 20.0 wave {0 10} set_clock_arrival_time clock IDEAL_CLOCK \ rise 0 fall 10 clk set_data_arrival_time 0.0 clock \ideal_clock [find port noclock input *]

13 set_data_required_time value clock \ideal_clock[find port output *] set_drive_resistance value \ [find port input *] set_port_capacitance value portlist check_timing check_netlist do_optimize report_area report_timing write_verilog hier output_file hier write_adb output_file 12

14 read_tlf 2. set_global target_technology <lib_name> 3. HDL read_vhdl read_verilog 4. do_build_generic 5. source <constraint>.tcl 6. do_optimize 7. report_timing > file.rpt 8. HDL write_verilog 2.4 Ambit Lab Basic Flow of Ambit Synthesis ObjectiveSynthesize your design using Ambit Synthesis. Design FilesThree modules are used for this design: mux.v Selects the signal source ring_plus.v Contains the math operations bell_box.v Top level model Running the Design 1. Change directories by entering: cd lab1_2 2. Enter ambit GUI environment ac_shell gui & 3. Enter the key steps in Navigates command window to synthesize the design (1) Reading in the technology file read_tlf csmc06core.tlf read_tlf csmc06pad.tlf (2) Reading in the Verilog models read_verilog {bell_box.v mux.v ring_plus.v} (3)Building the technology independent netlist do_build_generic (Double click the bell_box in Module Brower to view the schematic) (4)Setting the constraints set top "bell_box set_top_timing_module $top 13

15 set_current_module $top set_clock IDEAL_CLOCK -period wave { } set_clock_arrival_time -clock IDEAL_CLOCK -rise \0.00 fall clock proc all_inputs {} {find -port -input -noclocks *} proc all_outputs {} { find -port -output * } set_data_arrival_time 3.5 -clock IDEAL_CLOCK \[all_inputs] set_drive_resistance 0 [all_inputs] set_data_required_time clock IDEAL_CLOCK \[all_outputs] (5) Optimizing the design do_optimize (6) Generating reports report_timing > timing.rpt report_area -hier -cells > area.rpt report_design_rule_violations > drc_violations.rpt report_fanin out > fanin.rpt report_fanout mode > fanout.rpt report_hierarchy > hierarchy.rpt (7) Writing out the gate-level models write_verilog -hier bell_box_h.vg Note: you can collect the commands you set ((1) to (7)) to a script file, e.g. (script.tcl). Then use source script.tcl in command window to progress the synthesis. 4. Make sure the module tab is selected in the NaviGates browser window (center-left of the main window). Each module is labeled with b, g, m, o, or x. These labels indicate the state of the modules listed. Module state Definition b Black box (no subcomponents) g Contains generic view m Contains mapped view o Contains an optimized view x Module is marked as don t modify 5. Right click bell box in the module tab. a. Select Open Schematic Main Window. b. Left click on the module u1. c. on smart icons above schematic window, click the icon down hierarchy, The schematic of u1 is displayed. d. Select Up hierarchy e. In the schematic window, right click. A popup appears. Select worst path from the popup. f. To clear the highlighted path, select the smart icon above the schematic window Click Highlighting 6. Reviewing the Reports Review the reports created. 14

16 Silicon Ensemble : ASIC ASIC PAD PAD PAD 4 5 ASIC CAD ASIC ASIC

17 Silicon Ensemble Silicon Ensemble floorplan Silicon Ensemble SE Silicon Ensemble (floorplan), ANSI( ) Silicon Ensemble (floorplanners) (placers) (routers) (system support tools) floorplanners: placer: Qplace router: (global) (final), (power) WarpRoute system support tools: Silicon Ensemble (Mutilayer metal routing) (Mixed library support)correct-by-construction layout, (APT), (ECO) Silicon Ensemble 16

18 Silicon Ensemble Silicon Ensemble 3.3 Silicon Ensemble SE SE setup 1. LEF (Library Exchange Format): ASCII TLF (Timing Library Format)CTLF (Compiled Timing Library Format)CTLF TLF GCF (General Constraints Format) CTLF Verilog clock tree, Verilog bus pins 17

19 2. DEF(Design Exchange Format) : ASCII DEF Verilog incremental DEF DEF Preview Verilog incremental DEF GCF(General Constraints Format) SDF 3. setup se.ini: SE se.env: se.fin: dlc.init: GCF the Central Delay Calculator(CDC), SE

20 se sedsm seultra [-b] [-j=journal] [-gd=drive] [-e=environmentalfile] [-m=memorysize] [ cmds ] [&] [-version] -b: -gd=ansi: SE> -gd-x: ANSI se sedsm =b -gd=ansi EXECUTE script.com; & 3. 1 LEF LEF LEF GDSII AutoAbgen File-Import-LEF INPUT LEF - 2 GCF CTLF GCF CTLF CTLF dlc.init File-Import-Timing Library INPUT CTLF 3 Verilog ( ) Clock tree, File-Import-VerilogINPUT VERILOG 4 i) Verilog File-Import-Verilog INPUT VERILOG. ii) DEF :File-Import-DEF INPUT DEF 5 DEF ( ) DEF File-Import-DEF INPUT DEF 6 ( ) GCF clodk tree GCF 7 GCFSDF DC 8 Verilog ( ) Verilog 4. floorplan core, I/O core GCell RGrid Floorplan-Initialize FloorplanINITIALIZE FLOORPLAN EDIT MOVE 5. I/O blocks blocks I/O I/O pads I/O pins I/Opads Place-I/OsPLACE IO. (Edit-Move MOVE) (Place-Blocks QPLACE BLOCKS blocks blocks Floorplan -Update Core RowsCUT ROW. 19

21 6. Route-Plan Power (-Delete Pwr Path -Restore Pwr Path). power rings(-add Rings CONSTRUCT RING)power stripes(-add Stripes ADD STRIPE) (RingWires-Add Change Delete). 7. (cell) cell, RSPF RSPF I/O pins, cell pin placement floorplan Floorplan-Compact Floorplan(Vsize)VSIZE 8. SE Central Delay Calculator Report-Timing Analysia REPORT TIMING Report-Timing PathREPORT TIMING PATH Report-RC REPORT RC Report-Delay DELAY SDF 9. Floorplan-Compact Floorplan(Vsize)VSIZE 10% floorplan 10. clock trees( ) CTGen Place-Clock Tree Generate CTGen skew budget clock tree skew File-Import-DEFINPUT DEF ECO clock tree clock tree Report-Clock SkewREPORT CLOCK SKEW clock skew Report-Timing Analyzsis REPORT TIMING ANALYSIS, (violations) 11. ( ) violations GCF PBOpt ( Place-Placement Optimization-PBOpt PBS) QPlace (Place- Placement Optimization-QPlace Optimization) Floorplan-Compact Floorplan(Vsize)VSIZE 20

22 12. Route-Connect Ring CONNECT RING power nets Route-Clock Route CLOCK ROUTE clock trees nets Route-Warp Route WROUTE, Route-Globals Route GROUTE Route-Final Route FROUTE Search Repair violations 13. Verify-Geometry VERIFY GEOMETRY violations Verify-ConnectivityVERIFY CONNECTIVITY violations Verify-AntennasVERIFY ANTENNA antennas searchrepair FROUTE wirenet violations Edit-Wire violations 14. Report-RC REPORT RC RSPF Report-Delay REPORT DELAYS SDF Verilog File-Export-Verilog OUTPUT VERILOG (datapath design) datapath design datapath File-Import-Verilog INPUT VERILOG.vip Verilog floorplan datapath datapath Floorplan-Datapath Toolbox-Initial Functions; Floorplan-Datapath Toolbox-Add Regions; Floorplan-Datapath Toolboxl-Place Regions ECO 1. File-Import-DEF ECO(INPUT DEF ECO)File-Import-Verilog(INPUT VERILOG ECO) nets GUI GUI DA Verilog-HDL PAD DEFIO constraint file (.ioc)generate clock tree **.ctgen.cmd. 21

23 3.4 SE block LEF block LEF block LEF Wrap Route verify Wrap Route Search and Repair verify, report report summary row pin report RC net report delay net DC Verilog core pad pad DEF 2. IO (.ioc) 3. clock tree (.constraint) (.ctgen.cmd) SE %cd work InitWorkDir.csh scripts/ ***************************************************************************** #!/bin/csh -f if(`basename $cwd` == "work") then # Remove all previous files. \rm -r dbs *.cfg *.dtp *.gds *.info *.ini *.jnl *.rpt *.summary *.wdb \rm -r * # Prepare the directory. mkdir dbs 22

24 cp ~chwtang/csmc/csmchdlib/se/se.ini./se.ini # Start se in the background. sedsm -m=500 & else echo "Not in work directory." endif ****************************************************************************** %../scripts/initworkdir.csh SE File-Import-LEF csmc06.lef File-Import-Timing Library csmc06.gcf File-Import-Verilog ddfs.vddfstop.v verilog csmc06.v File-Import-SDF ddfs_constraints.sdf File-Import-DEF pads DEF SE Initialize Floorplan Floorplan-Initialize Floorplan SE rows Iopads: Place-Ios IO pads ddfstop.ioc SE IO pads power planning Route-Plan Power-Add Rings Route-Plan Power-Add Stripes Place-Cells clock tree: Place-Clock Tree Generate(CTGEN) clock tree clock tree clock tree def File-Import-DEF ECO place filler core cells Place-Filler Cells-Add Cells Route-Connect Ring Route-Wroute File-Export-GDS II gdsii File-Verilog Report-Delay SDF 23

25 PKS(Physical knowledge synthesis) RTL GDSII Cadence SPnR(Synthesis Place and Route) RTL GDSII SPnR Cadence SPnR RTL RTL GDSII SPnR RTL Verilog VHDL verilog VHDL EDIF SPnr PKS(Physically Knowledgeable Synthesis) SE(Silicon Ensemble) 24

26 25

27 4.2 PKS SPnR SPnR 1 SPnR 1 RTL ( ) Verilog VHDL 2 DEF 5.1+, PDEF 2.0 3GCF GCF 1.3, ALF 3.0, OLA(DCL), TLF ( ) TCL 6 LEF 5.2 LEF ASCII 2. Run script: do_rtl RTL Run script: do_pks Run script: do_ctpks Run script: do_post_ctpks_optimize Run script: do_groute Encapsulation: do_wroute Encapsulation: do_hyperextract Run script: do_delay_calc Run script: do_post_route_optimize Encapsulation: d0_post_route_eco ECO 3. setup.tcl, library,tcl design.tcl 4. PKS set_global placement_initialize_autopass true set_min_wire_length 10 set_steiner_mode report_globals 26

28 auto_slew_prop_selection true path_style_constraints true clock_gating_to_be_checked true extra_space_for_opt RTL PKS DEF SPnR RTL RTL PKS Verilog DEF RTL <library>.tlf <library>.lef <library>.lut demo.v demo.def constraints.tcl floor.tcf TLF LEF LUT RTl TCL TCL demo_rtl.adb demo_rtl.v demo_rtl.def timing_rtl.txt RTL do_rtl Ambit / SPnR PKS DP SPnR SE LEF DEF TLF SE power planner DEF DEF 27

29 <library>.lef demo_rtl.def LEF RTL demo_se.def DEF PKS DEF <library>.tlf <library>.lef <library>.lut TLF LEF LUT RTL demo_rtl.adb demo_se.def / RTL RTL RTL RTL demo.v demo_se.def constraints.tcl RTL TCL demo_pks.adb Ambit demo_pks.v / demo_pks.def timing_pks.txt do_pks PKS do_place do_xform_optimize_slack CTPKS PKS4.0 CTGen PKS CTGen 28

30 CTGen ctgen2pks CTPKS TCL do-ctpks CTPKS TLFALF (LEF) LUT set_constrain_for_timing set_clock_root set_clock_insertion_delay set_cel_property don t_utilize true {$celllrefs} ( CTGen ) get_clock_tree_objects buffer -inverter set_attribute $cellrefs ct_don t_utilize true CTPKS set_attribute $cellrefs ct_don t_utilize fause CTPKS dont_modify ctpks.tcl TCL set_clock_tree_constraints pin $clock_pin min_delay 2.0 max_dealy 2.5 max_leaf_transition 1.0 do_build_clock_tree noplace pin $clock_pin save_structure $clock_structure report_clock_tree pin $clock_pin >clock_tree.rpt report_clock_tree_violations pin $$4clock_pin > clcok_tree_violation.rpt set_clock_tree_constrains report_clock_tree_violations CTPKS CTPKS do_place eco do_place eco do_build_clock_tree set_clock_propagation_mode 29

31 CTPKS CTPKS Ambit Verilog DEF 30

32 <library>.tlf <library>.lef <library>.lut constraints.tcl TLF LEF LUT TCL demo_pks.adb Ambit do_post_ctpks_optimize PKS WROUTE PKS RC NETS RC PKS RC RC RC Veilog DEF.adb Verilog DEF <library>.tlf <library>.lef <library>.lut TLF LEF LUT Ambit demo_post_ctpks.adb Ambit demo_post_ctpks.v / demo_post_ctpks.edf constraints.rcl demo_groute.adb demo_groute.v demo_groute.def demo_groute.wbd Ambit / WROUTE 31

33 Verilog DEF do_xform_fix_hold incremental dont_reclaim critical_ratio 0.0 write_verilog: verilog write_def: quit and restart: PKS read_verilog: read_def: PKS do_xform_fix_hold incremental dont_reclaim critical_ratio WROUTE WROUTE WROUTE wroute SPnR SE GUI ULTRA WROUTE 9 SPnR SE GUI <library>.tlf <library>.lef <library>.lut TLF LEF LUT wroute.wrconfig WROUTE do_wroute demo_groute.wdb WROUTE demo_groute.def demo_wroute.wdb WROUTE demo_wroute.log 32

34 do_wroute HyperExtract PKS HyperExtract <library>.lef demo_wroute.def hyperextract.rules LEF demo_hext.dspf demo_hext.rspf demo_hext.log do_hyperextract Parasitic format DSPF RSPF HyperExtract PKS3.0.X SPnR PKS4.0.X SPnR PKS BulidGates/PKS WROUTE HyperExtract DSPF RSPF do_delay_calc do_delay_calc SPF SDF DSPF RSPF SPF PKS Engineering Change Order ECO ECO ECO ECO ECO DEF ECO ECO ECO ECO 33

35 SPF <library>.tlf <library>.lef <library>.lut demo_groute.v TLF LEF LUT / demo_groute.def demo_hext.rspf HyperExtract. timing_ipo.rpt do_post_route_optimize <library>.tlf <library>,lef <library>.lut TLF LEF LUT wroute_eco.cmd demo_groute.v / demo_groute.def demo_ipo.adb Ambit demo_ipo.v demo_ipo.def do_post_route_eco / DRC SE SE HECK HECK 34

36 Physical Synthesis IC Cadence Ambit, Silicon Ensemble, PKS(Physical knowledge synthesis)ambit logic synthesissilicon Ensemble placement & routingpks PKS Physical Synthesis RTL EDA 35

37 -- ASIC [1] Ambit manual Cadence Design System, Inc. [2] Documents about Ambit NSC Chip Implementation Center [3] SE_tutorial Cadence Design System, Inc. [4] SPnR Flow Guide for PKS Cadence Design System, Inc. 36