Outline Introduction Design Rule Check Layout vs. Schematic Check Lab Tutorial

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1 VLSI Design Lab3 Dracula- Layout Verification Advisor Presenter: 2003/04/25 ACCESS IC LAB

2 Outline Introduction Design Rule Check Layout vs. Schematic Check Lab Tutorial

3 Introduction ACCESS IC LAB

4 Design Flows System Specification Testing Behavior Design package Structure design P&R Layout Verification Manufacture Post-sim

5 Why Do We need Layout Verification Physical design must meet process rules for manufacture reliability Converting layout database to foundry acceptable format may introduce error The performance of design after layout need to be verified

6 Layout Verification DRC(Design Rule Check) ERC(Electrical Rule Check) LVS(Layout Versus Schematic) LPE(Layout Parasitic Extraction) PRE(Parasitic Resistance Extraction)

7 What is Dracula It is a IC verification tool for DRC,ERC,LVS,LPE,PRE,etc. Widely used, reliable The operation is guided by command file

8 How to Use Dracula Create/Obtain command file Fill in design database information Compile the command files Submit the run file Consult the checked reports and correct the violation

9 About Command File The contents of command file specify Source data information Data integrity check and processing Process rules for verification Device parameters Command files must be consistent with process

10 DRC ACCESS IC LAB

11 Design Rule Check Make sure our design is follow all the manufacture rules The rules define the width, space between layers and the relationship with each other layer The rules are based on process variation, equipment limitation

13 LVS ACCESS IC LAB

14 LVS Layout vs. Schematic check lvs drc/erc Tape-out lvs error free Lvs text label lvs

17 LVS Initial Node Pairs LVS comparison using text extracted form the schematic and layout as a starting point LVS result heavily rely on the matching of input labels

19 Lab Tutorial ACCESS IC LAB

20 DRC-Getting Started(I) icfb unix% mkdir DRC Unix% cd DRC

21 Getting Started(II) cds.lib icfb Unix% icfb & icfb CIW Tools New Library library New Library form design Libarary Name hw3 OK

22 Getting Started(III) Technology File for New Library Attach to an existing techfile ok Load Technology File ASCII Technology File 035.tf

23 Generate GDSII file gds CIW File Export Stream Run directory. Library Name hw3 Top Cell Name nand3(nor3) View Name layout Output File nand3.gds ok

24 Edit the Command File drc.com DRC INDISK = nand3.gds PRIMARY = nand3 PRINTFILE = edu( )

25 Run DRC Operation(I) PDRACULA drc.com :/get drc.com n fetches the command file :/fin finishes compilation and produce UNIX run file unix unix% jxrun.com > drc_logs&

26 Run DRC Operation(II) edu.sum *.sum PDRACULA drc.log

27 DRC Summary(I) OUTPUT CELL SUMMARY EJ49 50/ OUTDISK PRIMARY CELL : OUT4_1mux WINDOW : ENDED AT TIME =22:14:03 DATE =28-OCT-98 ****** PROBLEM GEOMETRY ERROR LISTING ****** ***** END OF PROBLEM GEOMETRY LISTING ***** OUTPUT CELL SUMMARY D DRC E ERC EJ49 No path to Vdd or Gnd

28 Debug the DRC Error debug layout edit window Tools->DRC Interactive DRC->Setup PDRACULA

29 DRC Summary(II) ****** PROBLEM GEOMETRY ERROR LISTING ****** ***** END OF PROBLEM GEOMETRY LISTING ***** NUMBER OF ACUTE ANGLE INPUT POLYGONS = 0 DRC check ERC layout verification

30 LVS-Getting Started(I) unix% mkdir LVS cds.lib icfb CIW File Export CDL Top Cell Name nand3(nor3); View Name schmatic; Library Name hw3; Output File nand3.cdl Run directory. ok

31 LVS-Getting Started(II) CDL si.log Run Directory Output File

32 Converting Netlist File(I) LVSLOG.DAT unix unix% LOGLVS :htv generate information for debugging :genpad :cir nand3.cdl compile CDL/SPCE/HSPICE netlist file :conv add8bit produce LVSLOGIC.DAT file for LVS :exit

33 Converting Netlist File(II) PRINT.OUT LOGLVS cdl

34 RUN Dracula LVS Operation(I) lvs.com LVS lvs.com INDISK=nand3.gds PRIMARY=nand3 PRINTFILE=edu( ) SCHMATIC=LVSLOGIC

35 RUN Dracula LVS Operation(II) lvs.com unix unix% PDRACULA :/g lvs.com n :/fin unix Unix% jxrun.com > lvs_log& edu.lvs

36 LVS Summary(I) *************************************************** ********** LVS DEVICE MATCH SUMMARY ********** *************************************************** NUMBER OF UN-MATCHED SCHEMATICS DEVICES = 0 NUMBER OF UN-MATCHED LAYOUT DEVICES = 0 NUMBER OF MATCHED SCHEMATICS DEVICES = 2512 NUMBER OF MATCHED LAYOUT DEVICES = 2512 unmatch 0 ok 0 debug

37 LVS Summary(II) **************** DISCREPANCY POINTS LISTING ********** ******************************************************** NO DISCREPANCIES device CIC data book LVS

38 LVS Summary(III) ******** DEVICE MATCHING SUMMARY BY TYPE ******** TYPE SUB-TYPE TOTAL DEVICE UN-MATCHED DEVICE SCH. LAY. SCH. LAY. MOS P MOS N bit work cascad work

40 Layout (I) Vdd Gnd spice simulation Average Current electromigration metal1 metal2 0.8mA/1um metal3 1.6mA/1um metal1 2.5um 2mA block

41 Layout (II) Vdd or Gnd block N block vdd gnd subtract contact 10um n-well Vdd pwell( n-well ) Gnd well performance

42 Layout (III) metal Schmatic check&save cdl

43 Thanks For Your Attention!

gate level ADMS Power Noise Timing RC RCC Signal Integrity RC RCC Calibre xrc Eldo Hspice spectre DSPF SPEF Calibre xrc reduce thresholds tolerances C

gate level ADMS Power Noise Timing RC RCC Signal Integrity RC RCC Calibre xrc Eldo Hspice spectre DSPF SPEF Calibre xrc reduce thresholds tolerances C Calibre xrc 1 Calibre xrc intrinsic coupled substrate 1 1 intrinsic plate 4 5 intrinsic fringe 1 2 3 6 2 nearbody 3 crossover fringe 6 crossover plate 1 RC 2 Calibre xrc Calibre xrc transistor level gate