Microsoft Word - SOC_Encounter_Flow_new4.docx

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1 SOC Encounter Flow First version: Chlin Second version: Paulman, lkince, Arong Data Prepare Description Working Directory Bonding Pad Capacitance Table File IO Filler Layout Mapping File Gate Level Netlist IO Constraint File Timing Constraint File Antenna Rules IO library Core Library Timing Library(Core) Timing Library(IO) Technology File for Veriuoso Virtuoso File Physical Layout(Core) Physical Layout(IO) Calibre DRC Rule File IOPAD SPICE File IOPAD Verilog File Core Cell SPICE File Core Cell Verilog File Calibre LVS Rule File RAM FILE or Directroy ~/SOCE/run/ ~/SOCE/run/addbonding_tpz.pl ~/SOCE/run/io_tpz.list ~/SOCE/run/tsmc013.capTbl ~/SOCE/run/addIoFiller_tpz.cmd ~/SOCE/run/streamOut.map ~/SOCE/design_data/CHIP.vg ~/SOCE/design_data/CHIP.ioc ~/SOCE/design_data/CHIP.sdc ~/SOCE/lef/antenna_8.lef ~/SOCE/lef/tpz013g3_8lm_cic.lef ~/SOCE/lef/tsmc13fsg_8lm_cic.lef ~/SOCE/lib/fast.lib, slow.lib, typical.lib ~/SOCE/lib/tpz013g3lt.lib, tpz013g3wc.lib, tpz013g3tc.lib ~/SOCE/replace/Virtuoso4.4_0.13um_Ver2.la.1.tf ~/SOCE/replace/.cdsinit ~/SOCE/replace/display.drf ~/SOCE/replace/GDSII/tsmc13gfsg_fram.gds ~/SOCE/replace/GDSII/tpz013g3.gds ~/SOCE/verify/drc/Calibre drc cur ~/SOCE/verify/lvs/tpz013_lvs.spi ~/SOCE/verify/lvs/tpz013_lvs.v ~/SOCE/verify/lvs/tsmc13gfsg_fram_lvs.spi ~/SOCE/verify/lvs/tsmc13gfsg_fram_lvs.v ~/SOCE/verify/lvs/Calibre lvs cur ~/SOCE/RAM_relate/RF1SHD_64x8_ant.clf ~/SOCE/RAM_relate/RF1SHD_64x8.vclef ~/SOCE/RAM_relate/RF1SHD_64x8*.lib

2 Place & Route with SOC Encounter 注意事項 : 以下的設定由於檔案設定不同, 所以與原先 Lab 不同, 是需要注意的地方, 此專題練習仍需要按照原先 Lab 流程進行 DAY 1 執行目錄為 run 在 Design Import 部分 Verilog Files../design_data/CHIP.vg Top Cell CHIP Max Timing Library../lib/slow.lib../lib/tpz013g3wc.lib../RAM_relate/RF1SHD_64x8_slow_syn.lib Min Timing Library../lib/typical.lib../lib/tpz013g3tc.lib../RAM_relate/RF1SHD_64x8_typical_syn.lib Common Timing Library../lib/typical.lib../lib/tpz013g3tc.lib../RAM_relate/RF1SHD_64x8_typical_syn.lib LEF Files../lef/tsmc13fsg_8lm_cic.lef../lef/tpz013g3_8lm_cic.lef../lef/antenna_8.lef../RAM_relate/RF1SHD_64x8.vclef../RAM_relate/RF1SHD_64x8_ant.lef Timing Constraint File../design_data/CHIP.sdc IO Assignment File../design_data/CHIP.ioc

3 注意,LEF File 的第一個 import 進去的一定要是 tsmc13fsg_8lm_cic.lef, 輸入完千萬不要急著按 OK 切換到 Advance 的 slide 切換到 IPO/CTS Buffer Name/Footprint buf Delay Name/Footprint dly2 Inverter Name/Footprint inv CTS: Cell Footprint clkinv clkbuf clkand2 clkxor2 clkmux2 切換到 Power Power Nets VDD Ground Nets VSS 切換到 RC Extraction Typical Capacitance tsmc013.captbl Table File Best Capacitance Table tsmc013.captbl File Worse Capacitance Table tsmc013.captbl File 按 Save 把這個表格存起來以後可以重新 Load, 存好後按 OK 在 Specify Floorplan 的設定

4 Ratio(H/W) 1 Core Utilization 0.2 Core to Left 80 Core to Top 80 Core to Right 80 Core to Bottom 80 其他用 default 即可, 按 OK 不需要 Specify scan chain 不需要打 Block ring, 與 Stripe 步驟 8.5 在步驟 8.3 之前做, 可先將 Memory 加上 Halo 再讓 Tool 去幫我們做 Placement

5 DAY 2 (Day 2, Lab1 Clock Tree Synthesis, step 6) Generate Clock Tree Spec Buffer Footprint clkbuf Inverter Footprint clkinv Save Spec To CHIP.ctstch (Day 2, Lab3 SI Analysis, Route, Stream out, step 4) NanoRoute > Route Timing Driven Enable SI Driven Enable 按 Attribute Net Type(s) Enable Clock Nets Enable Weight 10 Spacing 1 Avoid Detour True 按 OK, 離開 Attribute 畫面在 NanoRoute 的畫面按 OK (Day 2, Lab3 SI Analysis, Route, Stream out, step 9) 回到 unix terminal 執行 %./addbonding_tpz.pl CHIP.def 產生 bondpads.md, bondpads.eco 在 encounter terminal 輸入 source bondpads.cmd, 檢查是否有 Bounding Pad 接上, 且 Power Pad 都接短的 Bonding pad (Day 2, Lab3 SI Analysis, Route, Stream out, step 10) 這一步都不用做, 我們改到 lvs 及 drc 時再做 (Day 2, Lab3 SI Analysis, Route, Stream out, step 11) Design > Save > GDS Output Stream File CHIP.gds Map File streamout.map Unit 1000 其他不動按 OK 跟 Lab 中不一樣的是這邊 Memory 的 gds 我們改由 Virtuoso Stream out 出來, 因為在本專題中如果由 SOC Encounter stream out 的話 gds 檔出錯

DAY 3 Stream Out with Virtuoso 輸入下面的指令 cd../replace cp../run/chip.gds. icfb& File > Import > Stream Input File CHIP.gds Top Cell Name CHIP Library Name CHIP ASCII Technology Virtuoso4.4_0.13um_Ver2.

6 DAY 3 Stream Out with Virtuoso 輸入下面的指令 cd../replace cp../run/chip.gds. icfb& File > Import > Stream Input File CHIP.gds Top Cell Name CHIP Library Name CHIP ASCII Technology Virtuoso4.4_0.13um_Ver2.1a.1.tf File Name 按 OK, 等到跳出一個小視窗說 OK 才進行下一步 File > Import > Stream Input File./GDSII/tsmc13gfsg_fram.gds Top Cell Name ( 記得清成空白 ) 按 OK, 等到跳出一個小視窗說 OK 才進行下一步 File > Import > Stream Input File./GDSII/tpz013g3.gds Top Cell Name ( 記得清成空白 ) 按 OK, 等到跳出一個小視窗說 OK 才進行下一步 File > Import > LEF LEF File Name RF1SHD_64x8.vclef Target Library Name CHIP 按 OK 在 CIW 底下的 command line 輸入 load( t13abs2lay.ile ) 按 LVS Tools for TSMC13 > Copy Abs to Lay Library CHIP Cell Name RF1SHD_64x8 按 OK

File > Open Library fcell Name View Name 按 OK CHIP CHIP layout 在 LSW 的視窗上選 METAL2 pin 的選項在 layout 上按小寫 L, Label DVDD Height 10 按 Hide 此時會有個 DVDD 的 label 跟著滑鼠走移動到 PVDD2POC 的 bond pad 上按滑鼠左鍵一下放的位置如下,

7 File > Open Library fcell Name View Name 按 OK CHIP CHIP layout 在 LSW 的視窗上選 METAL2 pin 的選項在 layout 上按小寫 L, Label DVDD Height 10 按 Hide 此時會有個 DVDD 的 label 跟著滑鼠走移動到 PVDD2POC 的 bond pad 上按滑鼠左鍵一下放的位置如下, 可用 Shift+f 切喚看到 cell 內部的線,Ctrl+f 切換回來同樣的方法, 打一個 DVSS 的 label 在 PVSS2DGZ 的 bond pad 上 Design > Save 回去 icfb 視窗, 按照之前 lab 的流程做 stream out 的動作 DRC, LVS with Calibre 所需檔案放在 verify/drc/ 以及 verify/lvs/ 中 DRC 注意事項 :( 指令 :calibre -drc Calibre-drc-cur) 1. 自行修改 Calibre drc cur 中的 LAYOUT PATH 和 LAYOUT PRIMARY 2. 在 DRC report 的最下面若看到 TOTAL DRC Results Generated: 21 (21) 表示成功了

8 LVS 注意事項 :( 指令 :calibre -lvs -spice CHIP.spi -hier -auto Calibre-lvs-cur) 1. 自行準備 RAM 的 black box LVS 所需要的檔案 RF1SHD_64x8.v 內容如下 : module RF1SHD_64x8 ( Q, CLK, CEN, WEN, A, D); output [7:0] Q; input CLK; input CEN; input WEN; input [5:0] A; input [7:0] D; endmodule RF1SHD_64x8.spi 內容如下 :.SUBCKT RF1SHD_64x8 + VDD VSS Q[0] Q[1] Q[2] Q[3] Q[4] Q[5] Q[6] Q[7] CLK CEN WEN + A[0] A[1] A[2] A[3] A[4] A[5] + D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7].ENDS 2. 將用來進行 APR 的 netlist 轉換成 spice 格式, 用來和 layout 比對 v2lvs v ( 用來 APR 的 netlist 名稱 ) l RF1SHD_64x8.v l tsmc13gfsg_fram_lvs.v l tpz013g3_lvs.v o CHIP.spi s RF1SHD_64x8.spi s tsmc13gfsg_fram_lvs.spi s tpz013g3_lvs.spi s1 VDD s0 VSS 3. 自行修改 Calibre lvs cur 中的 LAYOUT PRIMARY,LAYOUT PATH,SOURCE PRIMARY,SOURCE PATH, 並在檔案最後一行加上 LVS BOX RF1SHD_64x8 4. 在 LVS report 裡看到笑臉便成功了

gate level ADMS Power Noise Timing RC RCC Signal Integrity RC RCC Calibre xrc Eldo Hspice spectre DSPF SPEF Calibre xrc reduce thresholds tolerances C

gate level ADMS Power Noise Timing RC RCC Signal Integrity RC RCC Calibre xrc Eldo Hspice spectre DSPF SPEF Calibre xrc reduce thresholds tolerances C Calibre xrc 1 Calibre xrc intrinsic coupled substrate 1 1 intrinsic plate 4 5 intrinsic fringe 1 2 3 6 2 nearbody 3 crossover fringe 6 crossover plate 1 RC 2 Calibre xrc Calibre xrc transistor level gate