國立交通大學 電信工程學系碩士論文 低功率變壓器回授變壓器回授與低電壓與低電壓多頻多頻之壓控震盪器和超寬頻系統之超寬頻系統之低雜訊放大器設計與研究 Design of Low Power Transformer Feedback and Low voltage Multi-Band VCO and Low Noise Amplifier for UWB System 研究生 : 廖昱舜 指導教授 : 周復芳 博士 中華民國九十七年六月
低功率變壓器回授與低電壓多頻之壓控震盪器和 超寬頻系統之低雜訊放大器設計與研究 Design of Low Power Transformer Feedback and Low voltage Multi-Band VCO and Low Noise Amplifier for UWB System 研究生 : 廖昱舜 指導教授 : 周復芳博士 Student: Yu Shun Liao Advisor: Dr. Christina F. Jou 國立交通大學電信工程學系碩士班碩士論文 A thesis Submitted to Department of Communication Engineering College of Electrical and Computer Engineering National Chiao Tung University In Partial Fulfillment of the Requirements for the Degree of Master of Science in Communication Engineering June 008 Hsinchu, Taiwan, Republic of China 中華民國九十七年六月
低功率變壓器回授與低電壓多頻之壓控震盪器和 超寬頻系統之低雜訊放大器設計與研究 研究生 : 廖昱舜 指導教授 : 周復芳博士 國立交通大學電信工程學系碩士班 摘 要 本論文討論的第ㄧ主題是壓控震盪器的分析和設計 在第一主題中 : 探討三種不同類型的壓控震盪器 : 基底回授與超低功率之變壓器型式壓控震盪器和低電壓多頻之帶壓控震盪器與其除頻器 為了達到高頻的操作, 變壓器架構基底回授的方式, 量測結果顯示 : 在供應電壓.5V 功率消耗 6. 毫瓦的條件下, 可調範圍 8.4~8.6 GHz, 相位雜訊為 -3dBc/Hz@MHz 採用汲極與源極端的回授, 則可達到超低功率的應用, 量測結果顯示出 : 可調範圍 5.3-5.4 GHz, 相位雜訊為 -4dBc/Hz@MHz, 而在 0.5V 供應電壓下, 功率消耗僅 0.57mW 另外, 提出壓控震盪器適用於多頻帶正交分頻多工超寬頻的系統, 其中壓控震盪器產生 Band 6~9 的載波頻率, 而除頻器產生 Band,, 並且由二對一多工器輸出選擇信號來自壓控震盪器或是除頻器, 量測結果顯示出 : 可調範圍 5.85-7.93 GHz, 相位雜訊為 -6dBc/Hz@MHz, 總功率消耗共 36.mW 第二主題為 : 介紹一個寬頻的低雜訊放大器, 其輸入匹配利用電晶體雜散電容來達成, 此方法可以使輸入匹配網路簡化, 並且減少雜訊的貢獻 其模擬結果顯示 3.GHz~0.6GHz, 其輸入返回損耗和輸出返回損耗皆在 -0dB 以下, 增益為 5dB, 最小雜訊指數為 4.dB, 電路功率消耗為 9.8 毫瓦 I
Design of Low Power Transformer Feedback and Low voltage Multi-Band VCO and Low Noise Amplifier for UWB System Student: Yu Shun Liao Advisor: Dr. Christina F. Jou Department of Communication Engineering National Chiao Tung University ABSTRACT This thesis about part one discusses the design and analysis of voltage-controlled oscillator. In part one, we discuss three kinds of VCO:Back-gate feedback and ultra low power transformer based VCO and low voltage multi-band VCO with its divider. In order to achieve higher frequency operation, transformer is feedback to the back gate. The measured results reveal that the power consumption is 6.mW for.5v supply voltage, the tuning rage is between 8.4~8.6 GHz, the phase noise is -3dBc/Hz@MHz. Adopting transformer feedback from drain to source enables ultra-low power application. The measured results reveal that the tuning rage is between 5.3~5.4 GHz, the phase noise is -4dBc/Hz @MHz, the power consumption is only 0.57mW under 0.5V supply voltage. Besides, for MB-OFDM UWB system, the VCO generates the carrier frequency for Band 6~9, the divider generate Band,, and multiplexer select the signal from the VCO or Divider. The measured results reveal that the tuning rage is between 5.85~7.93 GHz, the phase noise is -3dBc/Hz @MHz, the total power consumption is 36.mW. The second part introduces an ultra-wide band low noise amplifier. It uses the intrinsic capacitance of transistors to achieve the input matching and the complicated input matching network is replaced. The simulation result of UWB LNA demonstrates S < II
-0dB and S < -0dB from 3. to 0.6 GHz. The power gain (S) is 5dB. The minimum noise figure is 4.dB. III
致謝 能夠順利取得碩士學位, 首先要感謝我的指導教授周復芳老師給予悉心的指導與教誨, 除了在射頻積體電路的領域上能自由的從事研究, 並對於人生處事的觀念有不一樣的見解 同時要感謝口試委員郭建男博士及陳巍仁博士在論文上的建議與啟發, 使這篇論文更為完善 此外, 要特別感謝國家晶片中心研究人員在量測上所給予的協助與指導, 使我能順利的量測到晶片的各項參數 感謝實驗室吳匯儀學長的教導, 指引了我研究方向, 讓我在這兩年中獲益匪淺 還要感謝已畢業的學長子豪 宇清 瑞嫻與直升的宜星 智鵬學長, 在課業 電路設計及生活上的幫忙 也要感謝實驗室的同學志豪 沛遠 智元和廉昇, 有了大家的陪伴, 使得平淡的碩士生活多了不少樂趣 另外感謝俊緯學長 子哲 玠煌等學弟, 因為有你們的搞笑與幫忙, 讓我度過愉快的碩二 也要感謝一起從中正來到交大 清大的好友們與在 CIC 認識的每個人, 讓我有閒話家常的快樂時光, 使我更有勇氣完成碩士論文 最後要感謝是我最愛的父母親, 在求學的路上給予我最大的支持和呵護, 與生活上遊山玩水的回憶 ; 陪伴我成長的妹妹與 Mina, 總是能在我煩心的時候給予溫暖的力量, 讓我能順利地完成碩士學業 在此僅以小小的研究成果貢獻給我家人, 並與你們分享我的喜悅 昱舜 Sirius 於 008 年風城夏 IV
CONTENTS Chinese Abstract English Abstract Acknowledgement Contents List of Tables List of Figures I II IV V VII VIII Chapter Introduction...- -. Background and motivation... - -. Thesis organization... - 3 - Chapter CMOS voltage-controlled oscillator with transformer feedback.- 4 -. Introduction... - 4 -. Circuit Design Consideration... - 5 -.. X-band Low phase noise QVCO with back-gate transformer feedback - 5 -.. 5.5GHz Low power VCO with drain-source Transformer feedback - 9 -.3 Chip layout and simulation results... - 6 -.3. X-band Low phase noise QVCO with back-gate transformer feedback - 6-.3. 5.5GHz Low power VCO with drain-source Transformer feedback - 9 -.4 Measurement results and Discussions... -.4. Measurement consideration... - - Chapter 3 Low Voltage Multi-Band VCO and its Frequency Divider. - 30-3. Introduction... - 30-3. Circuit Design and Consideration... - 3-3.. Volatage Controlled Oscillator... - 3-3.. Divider... - 36-3..3 -to- Multiplexer... - 38-3.3 Chip layout and simulatoin results... - 39-3.4 Measurement results and Discussions... - 47 - Chapter 4 Conclusion and Future Work...- 54-4. Conclusion... - 54-4. Future Work... - 55 - Appendix CMOS Low Noise Amplifier for UWB system...- 56 - V
A. Introduction... - 56 - A. Design Consideration... - 6 - A.. Wideband matching technique... - 6 - A.. Ultra Wide-band Low-Noise Amplifier... - 64 - A.3 Chip implementation and Measured results... - 66 - A.4 Discussion and Conclusions... - 76 - Reference...- 78 - VI
LIST OF TABLE Table - Wireless communication system characteristc... Table -~ QVCO performance in different corner conditions...8 Table -3~4 VCO performance in different corner conditions... Table -5 Performance summary of the TF-QVCO...5 Table -6 Comparison of TF-QVCO...6 Table -7 Performance summary of the TF-VCO...9 Table -8 Comparison of TF-VCO...9 Table 3- Power consumption of each block...40 Table 3- Summary performance of the carrier frequencies...46 Table 3-3~6 VCO corner simulation...46 Table 3-7 K VCO comparison between the simulation and measurement...48 Table 3-8 Measurement of output power and phase noise performance...50 Table 3-9 Performance summary of the multi-band VCO...53 Table 3-0 Comparison with the multi-band VCOs...53 Table 3-7 K VCO comparison between the simulation and measurement...48 Table 3-8 Measurement of output power and phase noise performance...50 Table 3-9 Performance summary of the multi-band VCO...53 Table 3-0 Comparison with the multi-band VCOs...53 Table A- Performance summary of Ultra-wideband LNA...75 Table A- The comparisons of this work and recent LNA papers....76 VII
LIST OF FIGURE Figure - DS-UWB spectrum allocation... Figure - Multi-band spectrum allocation...3 Figure - Differential VCOs with transformer feedback...4 Figure - Proposed architecture of TFQVCO...5 Figure -3 Two interleaved VCO configuration...6 Figure -4 The primary and secondary self-inductances...7 Figure -5 The lumped model of the MOS varactor...8 Figure -6 The Proposed TF-VCO...9 Figure -7 Half circuits (a) Colpitts (b) TF-VCO... Figure -8 I-V characteristics of the MOSFET with and without FBB...4 Figure -9 Simulated Vth and drain current of the MOSFET with FBB...4 Figure -0 The primary and secondary self-inductances...5 Figure - The drain and source voltage waveform...6 Figure - The Chip layout...7 Figure -3 The frequency tuning range...7 Figure -4 The phase noise...8 Figure -5 The chip layout...9 Figure -6~7 The phase noise and the tuning range...0 Figure -8 The measurement equipment... Figure -9 Chip Photograph...3 Figure -0~ The measured tuning range and phase noise and spectrum...4 Figure -3 The Chip photograph...6 Figure -4~6 The measured tuning range and phase noise and spectrum...8 Figure -7 Transformer topology...30 Figure 3- Forecast of the CMOS supply voltage by ITRS...3 Figure 3- Frequency allocation of MB-OFDM proposal...3 Figure 3-3 Architecture of this circuit...3 Figure 3-4 Schematic of the proposed VCO with switched capacitor array...33 Figure 3-5 Simplified half-circuit model of the proposed VCO...33 Figure 3-6 The drain and source voltage waveform...35 Figure 3-7~8 Block diagram and shcematic of the CML frequency dividers...37 Figure 3-9 Schematic and gain of multiplexer...39 Figure 3-0 The chip layout...34 Figure 3-~ Tuning range curves of different banks and switching time...4 Figure 3-3~4 Output waveform and phase noise of 7.9GHz...4 Figure 3-5~6 Output waveform and phase noise of 7.39GHz...43 VIII
Figure 3-7~8 Output waveform and phase noise of 6.864GHz...44 Figure 3-9~0 Output waveform and phase noise of 6.336GHz...45 Figure 3- Chip photograph...47 Figure 3- Measured tuning range curves with different banks...48 Figure 3-3 Measurement of output power and phase noise...50 Figure 3-4 Output power of the carrier frequency...5 Figure 3-6 Maximal frequency in the locking range of the divider...5 Figure 4- Revised architecture of back gate TF-QVCO...55 Figure A- Basic input matching topology...57 Figure A- Basic four single-end distributed amplifier...58 Figure A-3 Narrowband LNA topology....59 Figure A-4 Fourth-order bandpass ladder filter used for impedance matching...59 Figure A-5 Configuration of a common-gate input stage...60 Figure A-6 The small signal equivalent circuit of common-source with inductive source degeneration...6 Figure A-7 The small signal equivalent circuit of source degeneration...6 Figure A-8 The equivalent small signal circuit of resistive loading...6 Figure A-9 The equivalent small signal circuit of capacitive loading...63 Figure A-0 The equivalent circuit of input impedance...64 Figure A- The schematic of the proposed UWB LNA...65 Figure A- The equivalent circuit of first stage UWB LNA...65 Figure A-3 (a) the chip layout (b) the chip photograph...67 Figure A-4 Measurement setups...69 Figure A-5 (a) Power gain vs. Frequency(b) Isolation vs. Frequency(c) Input return loss coefficient vs. Frequency(d) Output return loss coefficient vs. Frequency...7 Figure A-6 Noise Figure vs. Frequency...7 Figure A-7 (a)~(c) Pdb at 3,6,9 GHz...73 Figure A-8 (a)~(c) IIP3 at 3,6,9 GHz...75 Figure A-9 (a)the modified S simulation(b) The modified NF simulation...77 IX
Chapter Introduction. Background and motivation The continuous growth of personal wireless communications demands low-cost low-power in the design of wireless systems. Wireless transceivers for many standards, including GSM, Bluetooth, WLAN, and Wireless Personal Area Network (WPAN) require low-power design techniques to enhance their battery lifetime and to improve their portability. Having being aggressively scaled down, CMOS becomes an attractive process choice to implement low-cost integrated transceiver systems. Due to the flexibility, the demand for high-speed data transmission is increasing, such as real-time video and wireless USB. But according to Table -, most wireless communication systems support the data rate up to a few tens megabits per second only. For the personal short-range use, Bluetooth is very popular and able to integrate several wireless devices. However, there is a disadvantage of Bluetooth: poor data rate (Mbps). In other words, longer time is inevitable when a lot of data are accessed or different wireless devices work simultaneously. In order to raise the data rate, Ultra Wide-Band (UWB) can be a solution. In 00, the Federal Communications Commission (FCC) has allocated 7500-MHz of spectrum for ultra-wideband (UWB) applications in the 3. 0.6 GHz frequency range []. There are two mainly modulation technologies for UWB communications:direct sequence code division multiple access (DS-CDMA) and multi-band orthogonal frequency division multiple access (MB-OFDM). - -
Table - Wireless communication system characteristc System Cellular phone WLAN WPAN WCDMA 80. b/g 80. a Bluetooth UWB Frequency (GHz).9~.98.~.7.4~.4835 5.5~5.35.4~.48 3.~0.6 Modulation QPSK QPSK/OFDM OFDM GFSK DSSS/QPSK Channel Bandwith Date Rate (bit/sec) 5 MHz 0 MHz 0 MHz MHz 58 MHz 384 k/ M /54 M 54 M M 0/ 480 M DS-CDMA uses a sequence of Gaussian monocycle pulses which their spectrum is spread as in Fig. -. The lower band occupies the spectrum from 3.-4.85GHz and the upper band occupies the spectrum from 6.-9.7GHz []. The 5-6GHz band is dedicated to WLAN 80.a systems. WLAN 80.a Lower Band Upper Band 3. 4.85 6. 9.7 Frequency (GHz) Figure - DS-UWB spectrum allocation In Multi-Band-OFDM (MB-OFDM) UWB, frequency span is grouped into 5 major Band Groups which are in turn sub-divided into 4 bands in total, as shown in Fig. -. Each band is 58MHz bandwidth [3]. - -
Figure - Multi-band spectrum allocation. Thesis organization In this thesis, three voltage-control oscillators for X-band, WLAN 80.a, Multi-band operation and an Ultra-wideband Low noise amplifier are realized in TSMC RF P6M 0.8μm CMOS technology. Chapter will include two kinds of transformer feedback techniques in two voltage-controlled oscillators separately. One of this is to achieve higher oscillating frequency and the other is for ultra-low power operation. Chapter 3 will introduce a multi-band voltage-controlled oscillator and its frequency divider. The characteristic of wide tuning range under low voltage operation covers some group of MB-OFDM UWB system. Both the simulation and the measurement results are further discussed. Chapter 4 will give some discussions of these circuits to compare the simulation and measurement results. Besides, the future work will be mentioned to propose the possible improvement. Finally, appendix will present the design and implementation of 3.~0.6 GHz UWB LNA. In this chapter we study the input matching technique. - 3 -
Chapter CMOS Voltage-Controlled Oscillator with transformer feedback. Introduction Fig. - Differential VCOs with (a) transformer feedback to the source and (b) transformer feedback to the front gate As shown in Fig. -(a), the drain terminal is magnetically feedback to source terminal with an impedance transformation of n /g m, where n is the transformer turns-ratio and g m is the transconductance of the transistor [4][5]. Since the impedance seen at the source terminal is /g m, a relatively high turns-ratio is required for the transformer to make an impedance transformation, thereby entailing complexity in transformer design, making it possible to lower the oscillation frequency. If we feedback the drain voltage to the front-gate like Fig. -(b). Since the impedance seen at the gate of the switching transistor is relatively high, the turns-ratio - 4 -
of the transformer can be optimized with a smaller number of turns. However, the parasitic capacitances of the transformer directly couple to the tank, and lower the oscillation frequency significantly.. Circuit Design Consideration.. X-band Low phase noise QVCO with back-gate transformer feedback A. Transformer Feedback to the Back-gate To obtain both higher frequency and simplify the transformer design (small number of turns ratio), the front-gate feedback path can be modified to have a feedback to the back-gate as shown in Fig. -. Fig. - Proposed architecture of TFQVCO - 5 -
B. Harmonic Filtering Resistor Because the current source is the main contributor to the phase noise, the current source is replaced by resistor providing bias condition and wide-band operation, it can suppress not only second harmonic but also all the other harmonics [6]. The thermal noise of the resistor will be up converted into /f phase noise by the switching transistors. So there is a tradeoff between the harmonic filtering and its thermal noise contribution. As we increase the resistance, the /f phase noise performance will reach its optimum value and begin to degrade in the same way. This is because the thermal noise contribution overwhelms the phase noise reduction by the harmonic filtering. In this design, R=70Ω is selected. C. Quadrature Generation Fig. -3 Two interleaved VCO configuration There are several ways to obtain quadrature signals: RC poly-phase filters, divider-by- circuit, and two interleaved voltage-controlled oscillators. RC poly-phase filters attenuate the signal and increase the effective capacitance of the tank. A lot of chip area is needed for a good matching of the filters. The divider-by- circuit needs and oscillator operating at times higher than the desired frequency and a high-speed frequency. Both circuits dissipate a lot of power. For the low power consumption and quadrature phase accuracy, two interleaved VCO configuration is adopted as shown in Fig. -3. With parallel coupling transistor to generate the I-Q phase. From the Barkhausen - 6 -
inductance criterion, oscillation only occurs when the loop gain is [A(jω)] 4 =, which means A(j ω)= 90 o [7]. Therefore, this configuration provides quadrature-phase signals from the four outputs of these two proposed VCOs. The all-pmos topology is preferred since PMOS has lower corner frequency of flicker noise, which means less low frequency noise [8]. D. Transformer Design A -µm-thick top AlCu metal is used for the windings to increase the quality factor. The transformer is designed with -µm line spacing, 50-µm outer dimension. Besides, the quality factor of transformer can be optimized by increasing the metal width progressively from the inner to the outer turn [5][9]. As such, the series loss in the outer turn is reduced while its substrate loss associated with the wider metal width does not degrade the performance due to the virtual ground at the inductor's center tap. Fig. -4(a) shows the transformer is simulated by ADS Momentum with primary inductance (L d ) 0.46nH, and the secondary inductance (L s ) 0.3nH, with quality factors 6.8 and 4.4 respectively. The transformer coupling coefficient k m is modeled as shown in Fig. -4(b), which is calculated by Eq. (-) as 0.4 [0]. 0.7 0.6 0.5 primary 0.4 0.3 0. 0. secondary 0 0.0E+0.0E+9 4.0E+9 6.0E+9 8.0E+9.0E+0.E+0 freq Fig. -4 (a) The primary and secondary self-inductances (b) Transformer lump model - 7 -
K im = Im( Z Im( Z ) )Im( Z ) = L s L / M L d / (-) MOS varactors are used to provide the frequency tuning capability. AM noise originating from the upconversion of low frequency noise cannot be neglected due to AM-PM conversion through the varactors. So the frequency tuning capability will be controlled as varactor's selectivity and traded for lower phase noise []. The accumulation-mode MOS varactor is adopted in one group with 0 fingers. The equivalent capacitance Ceq is about 4~ ff and its equivalent lumped model is shown as in Fig. -5. Fig. -5 The lumped model of the MOS varactor - 8 -
.. 5.5 GHz Low power VCO with drain-source Transformer feedback The continuous growth of personal wireless communication demands low-cost low-power solutions in the design of wireless system. Low-voltage operation may save the power consumption of the analog as long as the total bias current does not need to be increased to maintain the same performance. Low voltage, however, limits the signal amplitude, which in turn limits the signal-to-noise ratio and degrades system performance. (a) (b) Fig. -6 The Proposed (b) TF-VCO and its (b) half circuit To improve the VCO performance in terms of low supply voltage, low power, and low phase noise, a TF-VCO is proposed to provide extra voltage swings, improved loaded quality factor, minimum noise-to-phase-noise transfer [5] as shown in Fig. -6. A. Enhanced voltage swings The main limitation of the signal amplitude is overcome by the concept of dual signal swing, which enables the output signals to swing above the supply voltage and - 9 -
below the ground potential with transformer feedback to increase the carrier power. Besides, the drain and source signal oscillate in phase to enhanced the swing amplitude. For an ideal coupling factor k=, the source signal amplitude V s,p is related to the drain signal amplitude V d,p by V s,p =V d,p /K L for K L =L d /L s and the maximum peak-to-peak oscillation amplitude at the drain would be increased to.v DD (+/K L ) B. Improved loaded quality factor The TF-VCO could also be analyzed by the half circuit VCO s transfer function. In Fig. -6(b), the tanks at the source and the drain are modeled by two RLC networks with a magnetic coupling coefficient k between Ld and Ls. For simplicity, the coupling coefficient k is assumed to be unity for now. Defining K L =L d /L s, K C =C d /C s, R d =Q d.ω.l d and R s =Q s.ω.(l d /K L ) with Q d and Q s being the parallel quality factors of L d and L s, respectively, and ω being the angular frequency. ( + ) V sgm Ld Ls Ld Ls out = Vin Ls + srscs + srdcd Ld Ls Ls s - Ls + Ld + sgmls + + L d Rs R d Ls L d Ld = s LdCd (+ K K L c K L + K L sg mld ( ) K L K L K L + K L Qd + Q ) + s gmld ( ) + K L ( K L ) ω QdQs s + (-) The oscillation frequency of the half-circuit VCO is determined by definition as the transfer function V out /V in having a magnitude of unity and a phase shift of 80 o, which corresponds to a unity loop gain with a zero phase shift for the closed loop. By solving (-), the oscillation frequency of TF-VCO is - 0 -
- - d d C L d d o C L K K C L + = ω (-3) where the approximation is a valid assumption because the resonant frequency of the tank at the source is much larger than that of the tank at the drain. An important parameter is the loaded quality factor Q loaded of the tank circuit, which is defined as the Q factor of the second-order transfer function V out /V in. From (-), the quality factor is given by ) ( + + = s L L L L d m d loaded Q K K K K R g Q Q (-4) which indicates the loaded quality factor increases as g m increase. The term ( L L K K + ) / ( ) L L K K could be optimized with a maximum value of /4. Because the resonant frequency of the secondary tank ω resonance of the TF-VCO is far above the oscillation frequency ω o, the unloaded parallel quality factor Q parallel of the secondary inductor atω o is = o resonance Q parallel Q series ω ω (-5) and thus Q s >>Q d and (-4) could be approximated as d m d loaded R g Q Q 4 4 (-6)
C. Minimum noise-to phase-noise transfer Fig. -7 Half circuits (a) Colpitts (b) TF-VCO Fig.-7 shows a comparison between a common-gate Colpitts VCO and the half-circuit TF-VCO, where the transformer is represented by an equivalent model. For the Colpitts oscillator, the capacitors C and C form the feedback network of the total tank capacitance and thus limit the maximum achievable L/C ratio. This contradicts the requirements for high tank quality factor and high tank impedance, and thus the Colpitts VCO is not favorable for low-power VCO design. The TF-VCO, on the other hand, uses a single transformer for the feedback and does not impose extra capacitance to the tank circuit, which could be similar to the Hartley design. Since the proposed VCO is operated under an ultra-low dc voltage, the cross-coupled transistors are potentially biased in the weak-inversion region. Therefore, the drain noise of the transistors is no longer dominated by the thermal noise as in, d [], = 4kTγg d 0, where g d0 is the channel conductance with V GS =0, and γ is the f thermal noise coefficient. Instead, the drain noise is expressed as [3] i n, d f 4kTγgd 0 = VGS Vt + exp( mv T qi D + VGS Vt ) + exp( ) mv T (-7) where I D is the drain current, V T is the thermal voltage, and m is the weak inversion slope factor. From (-7), i n d, / f includes not only the contribution from the thermal noise, but also that of the shot noise since the drain current consists of both drift and - -
diffusion components as the gate overdrive V GS -Vt approaches V T. Due to the fact that qi D is generally greater than 4kTγ gd 0 for low-power operation, the cross-coupled transistors may contribute more noise to the LC tank as the supply voltage decreases. Therefore, it imposes a fundamental limitation on the phase noise of the VCO for ultra-low-power and ultra-low-voltage applications. D. Forward Body Bias For deep-submicrometer MOSFETs, the threshold voltage V t is no longer constant, but influenced by circuit parameters such as gate length, channel width, and drain-to source voltage due to the short-channel and narrow-channel effects. Typically, transistors with a large channel width and a minimum gate length exhibit a reduced V t, which is preferable for low-voltage operations. In this VCO topology, the fundamental limitation on the supply voltage is imposed by the threshold voltage of the cross-coupled transistors. To further reduce the supply voltage, the FBB technique is adopted [4] as shown in Fig. -8. For a MOSFET device, the threshold voltage is governed by the body effect as ( qn Aε s / Cox) ( φ F + VSB φ F ) Vt= V (-8) t0+ Where V t0 is the threshold voltage for V SB =0V, ψ F is a physical parameter with a typical value of 0.3V, N A is the substrate doping, and ε s is the permittivity of silicon. By applying a forward bias voltage to the body through a current-limiting resistor R B, the effective threshold voltage is thus reduced while maintaining a minimum forward junction current between the body and the source terminals. The simulated effective threshold voltage and the drain current of a MOSFET with W=60μm and L=0.8μm are demonstrated in Fig. -8, indicating a threshold voltage reduction more than 80mV due to the FBB technique. - 3 -
ID (ma) 0 9 8 7 With FBB Without FBB 6 5 4 3 0 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VGS (V) Fig. -8 I-V characteristics of the MOSFET with and without FBB Besides, Fig. -9 shows the threshold voltage and its corresponding drain current under different forward body bias conditions. 0.8.4 Threshold Voltage (V) 0.6 0.4.6 0.8 Drain Current (ma) 0. 0. 0.3 0.4 0.5 0.6 Forward Body Bias (V) 0 Fig. -9 Simulated threshold voltage and drain current of the MOSFET with FBB E. Transformer Design The design takes advantage of the higher mobility of the NMOS devices compared to PMOS and the higher quality factor of differential inductors over simple single-ended inductors for differential circuits with a deep n-well as the source-bulk isolation to the substrate. For differential inductors, the quality factor is improved by a factor of two, without special processing steps because the magnetic coupling between - 4 -
the two coils ideally doubles the inductance value while the series loss is unchanged. Fig. -0 shows the transformer is simulated by ADS Momentum with primary inductance (L d ) 0.786nH, and the secondary inductance (L s ) 0.nH, with quality factors 7 and 5 respectively. The transformer coupling is calculated by Eq. (-) as 0.5 [0]. Primary Secondary 0.8 inductance(nh) 0.6 0.4 0. 0 0 4 6 8 0 Frequency(GHz) Fig. -0 The primary and secondary self-inductances Fig. - shows the drain voltage swing under different coupling coefficient, which implies the actual carrier power is reduced for lower coupling coefficient, and the source voltage swing is no longer sinusoidal to help enhance the voltage swing. This will unavoidably degrade the phase noise. Vd Vs Vd Vs.5.5 Amplitude (V) 0.5 Amplitude (V) 0.5 0 0-0.5-0.5-0 0.05 0. 0.5 0. Time (ns) (a) - 0 0.05 0. 0.5 0. Time (ns) (b) - 5 -
.5 Vd Vs Amplitude (V) 0.5 0-0.5-0 0.05 0. 0.5 0. Time (ns) (c) Fig. - The drain and source voltage waveform for (a) k= (b) k=0.75 (c) k=0.5.3 Chip Layout and Simulation Results.3. X-band Low phase noise QVCO with back-gate transformer feedback Fig. - shows the layout designed and processed using TSMC 0.8µm mixed-signal/rf CMOS P6M technology. The chip size is 0.88 0.49mm including the pads. The simulation result shows the phase noise is about -4dBc/Hz at MHz offset in Fig. -3 and Fig. -4 shows the output frequency tuning range of the QVCO is around 800 MHz ranging from 8.9 to 9.7 GHz. The QVCO core circuit draws only 4.mA from a.5-v supply. The figure-of-merit (FOM) is expressed as [5]. ω0 FOM = 0log[( ) ω ] L{ ω} V DD I DD (-9) where ω 0 is the center frequency, ωis the frequency offset, L { ω} is the phase noise at ω, VDD is the supply voltage, and I DD is the supply current. To further compare the performance of the proposed VCO, the power-frequency-normalized figure-of-merit (FOM) is used in (-9) as -85.5@MHz. - 6 -
Fig. - The Chip layout Fig. -3 The frequency tuning range - 7 -
Fig. -4 The phase noise Table - QVCO performance in different corner conditions Corner TT FF SS Tuning Range 8.9~9.7GHz 9.05~9.8 GHz 8.8~9.65 GHz Phase Noise@MHz -4dBc/Hz -3dBc/Hz -5dBc/Hz Total Power (with buffer) 6.+6.mW.4mW 7.75+3.mW 39.95mW 5.+5.9mW mw Table - QVCO performance under different supply voltage Supply Voltage.5V.65V.35V Tuning Range 8.9~9.7 GHz 8.85~9.6 GHz 8.95~9.75 GHz Phase Noise@MHz -4dBc/Hz -4dBc/Hz -3dBc/Hz Total Power (with buffer) 6.+6.mW.4mW 8.+30.5mW 38.6mW 4.6+5.6mW 0.mW - 8 -
.3. 5.5 GHz Low power VCO with drain-source Transformer feedback Fig. -5 The chip layout Fig. -5 shows the layout designed and processed using TSMC 0.8µm mixed-signal/rf CMOS P6M technology. The chip size is 0.66 0.58mm including the pads. The simulation result shows the phase noise is about -3dBc/Hz at MHz offset in Fig. -6 and Fig. -7 shows the output frequency tuning range of the TF-VCO is around 30 MHz ranging from 5.05 to 5.36 GHz. The power dissipation of the TF-VCO core circuit draws only 0.57mW from a 0.5-V supply. The figure-of-merit (FOM) is about -9@MHz. - 9 -
Fig. -6 The phase noise Fig. -7 The tuning noise - 0 -
Table -3 VCO performance in different corner conditions Corner TT FF SS Tuning Range 5.05~5.36GHz 5.08~5.38GHz 5.03~5.34GHz Phase Noise@MHz -3-5 - Core Power 0.6mW.mW 0.4mW Buffer Power 6.3mW mw mw Table -4 VCO performance under different supply voltage Supply Voltage 0.5V 0.55V 0.45V Tuning Range 5.05~5.36GHz 5.03~5.35GHz 5.05~5.36GHz Phase Noise@MHz -3-4 - Core Power 0.6mW.mW 0.46mW Buffer Power 6.3mW 6.3mW 6.3mW.4 Measurement Results and Discussions.4. Measurement Consideration The two voltage controlled oscillator are designed for on-wafer testing. Therefore the arrangement of each pad must satisfy rules of CIC s (Chip Implementation Center s) probe station testing rules. The measurement equipments contain Agilent E505A signal source analyzer, E4407B spectrum analyzer, and E365A DC power supply in Fig. -8. - -
(a) (b) (c) Fig. -8 (a) Agilent E505A signal source analyzer (b) E4407B spectrum analyzer (c) E365A DC power supply - -
A. X-band Low phase noise Quadrature CMOS VCO with back-gate transformer feedback The chip photograph is shown in Fig. -9. Fig. -9 Chip Photograph According to Fig. -0, the measured output frequency tuning range of the fabricated TF-QVCO is 470kHz ranging from 8.4 GHz to 8.6 GHz. Fig. - shows the phase noise of -3dBc/Hz at MHz offset when the frequency is 8.45GHz and the output spectrum is -6.5dBm as show in Fig. -. The VCO core draws 4.mA from.5v supply. - 3 -
8.65 8.6 8.55 Frequency (GHz) 8.5 8.45 8.4 8.35 8.3 8.5 8. 8.5 8. 0 0. 0.4 0.6 0.8..4.6.8 Control Voltage (V) Fig. -0 The measured tuning range Fig. - The measure phase noise - 4 -
Fig. - The measure spectrum Table -5 Performance summary of the TF-QVCO Performance Post-Simulation Measurement Supply Voltage.5V Tuning Range 8.9~9.7 GHz (9 %) 8.4~8.6 GHz Phasenoise@MHz -4dBc/Hz -3dBc/Hz Power Consumption.4mW.mW (VCO core 6.mW) (VCO core 6.mW) Output Power -3. dbm -6.5 dbm FOM 85.5 83.6-5 -
Table -6 Comparison of TF-QVCO This work MWCL,005 [4] MWCL,003 [6] Technology 0.8um CMOS 0.8um CMOS 0.8um CMOS Voltage.5V.8V 3V Oscillation Frequency 8.4 GHz. GHz 8 GHz Tuning Range 8.4~8.6 GHz 300MHz vtune 8.08~7.83GHz 5.6% from.6-v 3 % Phase noise (dbc/hz) -3dBc/Hz -09.4 @ MHz -7 @ MHz Power 6.84 mw 4 mw 6. mw Dissipation (vco core) (vco core) FOM 83.6-8.8-8.7 B. A Low-Power CMOS VCO with drain-source transformer feedback The chip photograph is shown in Fig. -3. Fig. -3 Chip Photograph - 6 -
According to Fig. -4, the measured output frequency tuning range of the fabricated TFDSVCO is 90kHz ranging from 5.3 GHz to 5.4 GHz. Fig. -5 shows the phase noise of -4dBc/Hz at MHz offset when the frequency is 5.33GHz and the output spectrum is.6dbm as show in Fig. -6. The VCO core draws.ma from 0.5V supply. 5.45 5.4 5.35 Frequency (GHz) 5.3 5.5 5. 5.5 5. 0 0. 0.4 0.6 0.8..4.6.8 Control Voltage (V) Fig. -4 The measured tuning range - 7 -
Fig. -5 The measure phase noise Fig. -6 The measure spectrum - 8 -
Table -7 Performance summary of the TF-VCO Performance Post-Simulation Measurement Voltage 0.5V 0.5 Tuning Range 5.05~5.36GHz 5.3~5.4 Phase noise (dbc/hz) - 3@ MHz -4@ MHz Total Power Dissipation 0.6(vco core) +6.3mW(buffer) 0.6(vco core) +7mW(buffer) FOM 9 93 Table -8 Comparison of TF-VCO This work (Measurement) JSSCC, 005 [5] MTT, 007 [4] Technology 0.8um CMOS 0.8um CMOS 0.8um CMOS Voltage 0.5V 0.5V 0.6V Oscillation Frequency 5.5 GHz 3.8 GHz 5.6 GHz Tuning 5.3~5.4 GHz 3.7~3.84 GHz 5.35 ~ 5.85 GHz Range 5.5 % 8.4 % 8. % Phase noise (dbc/hz) -4 @ MHz -9 @ MHz -8 @ MHz Total Power Dissipation 0.6 mw 0.57 mw 3 mw FOM -93-93 -89-9 -
Chapter 3 Low Voltage Multi-Band VCO and its Frequency Divider 3. Introduction Unfortunately, the inherently low transconductance of the MOSFETs at higher frequencies have impeded the evolution of low-power designs to RF front-ends. In addition to the power considerations, a reduced supply voltage is also an inevitable trend for CMOS designs as well. With the continuous shrinking in the transistor feature size, a proportional down-scaling of the supply is required to ensure the gate-oxide reliability [7]. The forecast of the supply voltage for CMOS circuits within the next decade [8] is shown in Fig. 3-. Fig. 3- Forecast of the CMOS supply voltage by ITRS [4] - 30 -
3. Circuit Design Consideration Fig. 3- Frequency allocation of MB-OFDM proposal. In this work, Band, and 6~9 are covered as shown in Fig. 3-. Band Group from 475~5808 MHz causes interference with 80. a and Band Group 4,5 is reserved for future use. In order to meet such a specification, a VCO accompanied with a frequency divider is used to loosen the stringency, where the VCO provides carriers for Band 6~9 while the frequency divider is in charge of Band,. The multiplexer is also included to select where the output is from vco or divider. The architecture is shown in Fig. 3-3. Fig. 3-3 Architecture of this circuit - 3 -
3.. Voltage-Controlled Oscillator The schematic of the proposed VCO is shown Fig. 3-4. In order to reduce the required supply voltage and to eliminate additional noise contribution, the tail current transistor in a conventional cross-coupled VCO is replaced by on-chip inductors. For an enhanced voltage swing under a low supply voltage, the capacitive-feedback technique is employed [4]. Due to the use of the on-chip inductor and the feedback loop established by C and C, the drain and source voltages can swing above the supply voltage and below the ground potential. Consequently, the output swing of the VCO is enhanced, leading to a superior close-in phase noise. Fig. 3-4 Schematic of the proposed VCO with switched capacitor array A. Startup Conditions - 3 -
- 33 - Fig. 3-5 Simplified half-circuit model of the proposed VCO In order to derive the startup conditions and the oscillation frequency,the equivalent half-circuit of the VCO core is shown in Fig. 3-5, where R and R represent the losses of the on-chip inductors L and L, respectively. In the equivalent circuit, the shunt resistance R and R can be estimated by / / s s R L R R L R ω ω = = (3-) where R s and R s are the equivalent series resistances of L and L, respectively. From the small-signal analysis, the transfer function between V o and V i is given by ( ) 0 3 3 4 4 a s a s a s a s a s L R R R s L L s R R C L L g V V m i o + + + + + + = (3-) where ( ) ( ) ( ) ( ) [ ] v v m v v v m m C C C C C R R L L a R g C R R C R R C R C L L a C L C L L C L C R R C L C L L C L C R R R g L L a R R L g R L L R a R R a + + = + + + + = + + + + + + + + = + + = = 4 3 0 The circuit oscillates if the loop gain is unity, which corresponds to a voltage gain V o /V i =- at the oscillation frequency ω0 ( ) 0 0 0 3 0 3 4 0 4 0 0 0 = + + + + a ja a ja a L R R R jl L R R C L L jg m ω ω ω ω ω ω ω (3-3)
with proper arrangement, (3-3) yields and L L L L g v (3-4) 4 m [ C C + C ( C + C )] ω L( C + C ) + L ( C + C ) ω + 0 0 v 0 = R 3 [ LL ( RC + RC + RC + RC v) gmll RR ( C Cv )] ω0 [ g R R ( L L ) + R L + R L] ω = 0 m 0 (3-5) Provided g m L R ( C + ) L << in typical design cases, (3-4) can be simplified as C 4 [ C C + C ( C + C )] ω [ L( C + C ) + L ( C + C )] ω + 0 L 0 v 0 = v (3-6) From (3-6), the oscillation frequency can be approximated by L ( C+ Cv) + L( C+ C) [ C C + C ( C + C )] ω 0 (3-7) L L v Based on (3-5) and (3-7), the required transconductance g m to sustain the oscillation is given by g m LL ( RC + RC + RC + RC v ) ω0 LR LR = L L R R ( C C ) ω + R R ( L L ) v 0 (3-8) Equations (3-7) and (3-8) show the general form of oscillating frequency and transconductance, which could be simplified by selecting the ratio appropriately. B. Output Voltage Swing In the proposed VCO circuit, a capacitive feedback is formed by capacitors C and C. Due to the in-phase relationship provided by the capacitive feedback and the use of on-chip inductors, the drain and source voltage can swing above the supply voltage and below the ground potential, as illustrated in Fig. 3-6(a). To evaluate the performance enhancement of this technique, the output voltage swing of the VCO is derived from the time-domain waveform of the drain current I (t), as shown in Fig. 3-6(b). - 34 -
Fig. 3-6 (a) The drain and source voltage waveform due to capacitive feedback (b) Acutal and modeld drain current waveform [4] For simplicity, the periodic drain current is modeled by a square wave with a period of T 0 =π/ω0 and an amplitude of I 0. Note that, at the quiescent point, the transistors are biased at V D =V D =V DD and V S =V S =0. The maximum drain current occurs when the gate voltage V G reaches its peak value. Assuming that the amplitude of output oscillating signal is A, the gate voltages V G and V G are (V DD +A) and (V DD -A), respectively, while the source voltages V S and V S can be obtained by the voltage divider of C and C. Thus, I 0 is approximated by the maximum drain current with the transistor operating in the nonsaturated region I W µ ncox ( VDD + A+ na Vt )( VDD A+ na) ( VDD A+ na L (3-9) 0 ) where n = C /( C+ C) and Vt is the threshold voltage of the MOSFET. From the Fourier series of I (t), the fundamental current component is given by I( t) fundamental I0 sin( ω0t) (3-0) π and the fundamental voltage amplitude is I Rp (3-) π A 0 where Rp is the load resistance. From (3-9) and (3-), a simplified expression of the VCO output swing is given by A + C / C ). V ( DD - 35 -
C. Switched-Capacitor-Array In order to achieve a wide frequency range while keeping a relatively low tuning sensitivity, the frequency tuning range is divided into 0 sub-bands by using a 4-bit binary weighted. For single ended switched capacitors, when a branch is turned ON it will contain two r ds0 in series going from one side of the differential circuit via ground to the other. This limits the achievable quality factor and degrades the phase noise. Therefore, the differential switched-tuning is used [9][0], the MOS switches are not directly connected to the ground, and instead they are connected both capacitors. This topology can avoid the substrate noise coupling into the tank and halve the number of the MOS switches. Therefore the on-resistance can be reduced and phase noise is improved. Furthermore, to achieve a high quality a wide transistor could be as wide and as short as possible, however the drain capacitance is proportional to the width of the transistor, that would reduce the tuning range and maximum oscillation frequency, leading to a compromise. The inverter does not consume any static power, and a negligible amount of silicon area. Together with the resistors it makes sure that the transistor is OFF at all times in the OFF state and gets the maximum gate to source(and drain) voltage in the ON state. 3.. Divider Frequency dividers operating at high frequency are one of the key blocks in the RF circuits because dividers must function properly over the required bandwidth and provide enough output swing for the next stage. Three kinds of dividers are often used: digital CMOS logic, current-mode logic (CML), and injection-locked frequency dividers (ILFD) []. Digital CMOS logic is seldom used since full-scale swing is needed and the operating frequency is relatively low. Compared with CML, ILFD has - 36 -
lower power consumption with larger area and narrower locking range. Due to very wide bandwidth of VCO, the CML is chosen in this work. Fig. 3-7 Block diagram of the CML frequency dividers Fig. 3-8 Schematic of the CML frequency dividers The block diagram of CML frequency dividers is shown is Fig.3-7. The master and slave D-FFs are clocked by complementary clocked signals and the differential outputs of LC-VCO in the previous section provide this kind of input signals. Consequently, the inverter in Fig.3-7 is implemented without adding any circuit. The frequency of both Vm and Vo is half the frequency of Vi. Meanwhile the phase difference between Vm and Vo is just 90 degree and quadreture outputs are obtained. In other words, CML is also a kind of quadrature signal generators owing to the characteristic of the output nodes. The D-FFs implemented in CML are composed of a clocked differential sensing amplifier pair and inversely clocked latching pair as shown in Fig. 3-8. The two D flip-flops are operate periodically and alternately between two modes. When the input - 37 -
VCO signal is low, one of the D-FF is in the sensing mode, while the other D-FF is in the latching mode. In contrast with common CML circuits, the bias current source is eliminated increase the maximum operating frequency about 0% []. Only NMOS transistors are used in this circuit because the drain parasitic capacitance and power dissipation should be minimized. The trans-conductance of clock transistors has to be large and then the small input signals can drive them from the linear region to the saturation region. Therefore the sensitivity to the DC level of input signals is increased. Due to omitting the current source, the DC bias point of the circuit is determined by the size and Vgs-Vt of the clock transistors, the DC level of the input, and the value of the load resistance. The load resistance is another key parameter since the dominant pole is decided by the load resistance and parasitic capacitance from transistors, interconnection, and next stage. To make this pole high enough, the R must be small, which inevitable leads to increased power consumption to set the DC output. 3..3 -to- Multiplexer (a) - 38 -
(b) Fig. 3-9 (a) Schematic of multiplexer (b) Gain of the multiplexer vs. the input frequency The -to multiplexer is to decide that the output is generated from VCO or the Divider. Fig. 3-9 shows the schematic of the multiplexer. Again the current source is removed to relax the voltage headroom problem [3]. When V sel is high, M S is off and the output is only from the VCO. On the other hand, when V sel is low, M S is off and the output is only from the divider. Because the output frequency covers a wide range of spectrum, the gain must insensitive to the operating frequency. The load inductors and capacitors should be designed as large as possible to alleviate the impedance variation with the frequency. Therefore, the bias-tee is chosen as the load impedance. The inductor and capacitor in the bias-tee can be treated as infinitely large at the multi-ghz frequency. For this reason, the load impedance is approximately on R L (50Ohm). 3.3 Chip Layout and Simulation Results - 39 -
A signal generator is designed and simulated by Eldo RF simulator. The chip size is 0.95 0.65mm including the pads and fabricated using TSMC 0.8µm mixed-signal/rf CMOS P6M technology. Fig. 3-0 shows the layout of this circuit, which is kept symmetry to equalize the amplitude of the differential outputs. The power consumption of each block is listed in Table 3-. Fig. 3-0 The chip layout Table 3- Power consumption of each block power current VCO 7. mw 7.9 ma Divider 8.6 mw 4.5 ma MUX 0.53 mw.4 ma total 35.8 mw.06 ma The simulation result shows that the tuning range is 6.05~8.4 GHz for the total 0 curves. Overlapping between curves is necessary to avoid the process variation and cover the entire band as shown in Fig. 3- - 40 -
Fig. 3- Tuning range curves of different banks In Fig. 3-, the band switching is completed in about 0.6 nsec. In consequence, both of the periods are much shorter than the required time 9.5 nsec. Fig. 3- Output waveform switching from bank (0,0,0,0) to (,,,) - 4 -
When the digital input is (0,0,0,0) with the control voltage of V, the oscillation frequency is 7.90 GHz. The output swing is 0.95 V pp (3.6dBm) and the phase noise is -0 dbc/hz. Through the frequency divider, output frequency at 3.960 GHz is generated. These results are shown in Fig. 3-3 and Fig. 3-4 Fig. 3-3 Output waveform of VCO and frequency divider Fig. 3-4 Phase noise with oscillation at 7.90 GHz - 4 -
When the digital input is (0,0,,0) with the control voltage of 0.95V, the oscillation frequency is 7.39GHz. The output swing is 0.9 V pp (3dBm) and the phase noise is - dbc/hz. Through the frequency divider, output frequency at 3.69 GHz is generated. These results are shown in Fig. 3-5 and Fig. 3-6 Fig. 3-5 Output waveform of VCO and frequency divider Fig. 3-6 Phase noise with oscillation at 7.39 GHz - 43 -
When the digital input is (,0,0,0) with the control voltage of 0.73V, the oscillation frequency is 6.864GHz. The output swing is 0.8 V pp (.8dBm) and the phase noise is -3 dbc/hz. Through the frequency divider, output frequency at 3.69 GHz is generated. These results are shown in Fig. 3-7 and Fig. 3-8 Fig. 3-7 Output waveform of VCO and frequency divider Fig. 3-8 Phase noise with oscillation at 6.864 GHz - 44 -
When the digital input is (,0,,) with the control voltage of 0.4V, the oscillation frequency is 6.336GHz. The output swing is 0.75 V pp (0.dBm) and the phase noise is -4 dbc/hz. Through the frequency divider, output frequency at 3.69 GHz is generated. These results are shown in Fig. 3-9 and Fig. 3-0 Fig. 3-9 Output waveform of VCO and frequency divider Fig. 3-0 Phase noise with oscillation at 6.336 GHz - 45 -
Table 3- Summary performance of the carrier frequencies Output Frequency Voltage Swing Phase noise @ MHz FOM 6.336 GHz 0.73V PP -4 dbz/hz 83 6.864 GHz 0.8 V PP -3 dbz/hz 8.8 7.39 GHz 0.9 V PP - dbz/hz 8. 7.90 GHz 0.95 V PP -0 dbz/hz 8 Table 3-3 VCO tuning range and power dissipation for different corner Corner TT FF SS Tuning Range (GHz) 6.05~8.4 6.36~8.3 5.75~7.99 Power Dissipation 35.8 mw 45.6mW 9.6mW Table 3-4 VCO tuning range and power dissipation for different power supply V DD 0.9V 0.8V 0.99V Tuning Range(GHz) 6.05~8.4 6.05~8.7 6.04~8. Power Dissipation 35.8mW 33.4mW 39.45mW Table 3-5 VCO phase noise of the carrier frequency for different corner Corner TT FF SS 7.90GHz -0-09 - 7.39GHz - -0-6.684GHz -3-0 - 6.336GHz -4-3 -09 Table 3-6 VCO phase noise of the carrier frequency for different power supply Corner 0.9V 0.8V 0.99V 7.90GHz -0-0 - 7.39GHz - - - 6.684GHz -3 - -3 6.336GHz -4-3 -4-46 -
3.4 Measurement results and Discussion The multi-band controlled oscillator is designed for on-wafer testing. Therefore the arrangement of each pad must satisfy rules of CIC s (Chip Implementation Center s) probe station testing rules. The measurement equipments contain Agilent E505A signal source analyzer, E4407B spectrum analyzer, and E365A DC power supply. Also the whole chip photograph is shown in Fig. 3- Fig. 3- Chip photograph According to Fig. 3-, the 0 tuning range curves cover each other and signal at GHz can be generated. Comparing with 6.05~8.4 GHz bandwidth in the simulation results, the total tuning range is a little shrunk. Because the gain of the VCO is little change in Table 3-7, the compressed tuning range is mainly from the overestimated capacitors in SCA. - 47 -
Frequency (GHz) 8 7.8 7.6 7.4 7. 7 6.8 6.6 6.4 6. 6 5.8 (0000) (000) (000) (00) (00) (00) (00) (0) (0) () 0 0. 0.4 0.6 0.8..4.6.8 Control Voltage (V) Fig. 3- Measured tuning range curves with different banks Table 3-7 K VCO comparison between the simulation and measurement Simulation Measurement (0,0,0,0) 7. MHz/V 6.7 MHz/V (0,0,0,) 44.4 MHz/V 00 MHz/V (0,0,,0) 7.7 MHz/V 00 MHz/V (0,0,,). MHz/V 6 MHz/V (,0,0,0) 83.3 MHz/V 44.4MHz/V (,0,0,) 77.7 MHz/V 38.8MHz/V (,,0,0) 6. MHz/V 33.3MHz/V (,,0,) 50 MHz/V 30.MHz/V (,,,0) 38.8 MHz/V 7.7MHz/V (,,,) 7.7 MHz/V 6.6MHz/V - 48 -
Following the tuning range, the output power and phase noise performance is measured in Fig. 3-3 and Table 3-8. The measure value of the phase noise is approximately equal to the simulated one. (a) 6.336GHz (b) 6.864 GHz - 49 -
(c) 7.39GHz (d) 7.90GHz Fig. 3-3 Measurement of output power and phase noise Table 3-8 Measurement of output power and phase noise performance Output Frequency Output Power Phase noise @ MHz FOM 6.336 GHz 3.64-6 dbz/hz 85 6.864 GHz.5-4 dbz/hz 84 7.39 GHz.7 - dbz/hz 83 7.90 GHz 3.84 - dbz/hz 83-50 -
Besides the VCO, the performance of the divider-by- circuit is measured in Fig. 3-4. The multiplexer suppresses the VCO signal about 0dB when the frequency divider is selected. But at 7.3GHz the divider doesn t work properly in Fig. 3-5. The reason is likely that the parasitic effect at the output nodes of the divider is not completely extracted and the behavior can t be accurately predicted in the post-simulation. (a) (b) Fig. 3-4 Output power of the carrier frequency at (a).94 and (b) 3.74 GHz (c) (c) 3.440 GHz - 5 -
As a result, the control voltage of VCO is tuned and the locking range of the frequency divider is up to 7.7GHz. The measurement is shown in Fig. 3-6. Finally, the power dissipation of each block in the measurement is very close to the result in the simulation. Fig. 3-6 Maximal frequency in the locking range of the divider The performance in the measurement is close to the results in the simulation except that 3.96 GHz signal is not generated successfully. To improve this, the layout parasitic extraction by EM software has to be more detailed although this will take a longer time. Besides, the bias point of divider design should be checked and fine-tuned. The summary of this work is listed in Table 3-9. In addition, the comparison with other wideband VCOs is shown in Table 3-0. Through the calculation of the figure-of-merit (FOM), this work really achieves better performance. - 5 -
Table 3-9 Performance summary of the multi-band VCO Performance Post-Simulation Measurement Supply Voltage 0.9V Tuning Range 6.05~8.4 GHz 5.85~7.93GHz Phasenoise@MHz -0~-4dBc/Hz -~-6dBc/Hz Power Consumption 35.8 mw 36. Output Power.~4.5 dbm.5~3.84 dbm FOM 8~83 83~85 Table 3-0 Comparison with the multi-band VCOs This work ISCAS 005 [5] MWCL 005 [4] Technology 0.8μm CMOS 0.8μm CMOS 0.8μm CMOS Supply Voltage 0.9 V.5V.8V Tuning range 5.85~7.93 GHz 3.5~5.3 GHz 5.5~6.7 GHz Phase noise (dbc/hz) -6 @ MHz -5 @ MHz -4 @ MHz Power 36. mw (7 mw Dissipation in VCO core) 6 mw 5.8 mw FOM 85 8 80-53 -
Chapter 4 Conclusion and Future Work 4. Conclusion In chapter two, we discuss two kinds of VCO based on transformer:feedback to the Back-gate and the source. In order to achieve higher frequency operation, transformer is feedback to the back gate. The measured results reveal that the power consumption is 6.mW for.5v supply voltage, the tuning rage is between 8.4~8.6 GHz, the phase noise is -3dBc/Hz@MHz. Adopting transformer feedback from drain to source enables ultra-low power application. The measured results reveal that the tuning rage is between 5.3~5.4 GHz, the phase noise is -4dBc/Hz @MHz, the power consumption is only 0.57mW under 0.5V supply voltage. In chapter three, for MB-OFDM UWB system, the VCO generates the carrier frequency for Band 6~9, the divider generate Band,, and multiplexer select the signal from the VCO or Divider. The measured results reveal that the tuning rage is between 5.85~7.93 GHz, the phase noise is best -6dBc/Hz @MHz, the total power consumption is 36.mW. Finally, we introduce an ultra-wide band low noise amplifier in the appendix. It uses the intrinsic capacitance of transistors to achieve the input matching and the complicated input matching network is replaced. The simulation result of UWB LNA demonstrates S < -0dB and S < -0dB from 3. to 0.6 GHz. The power gain (S) is 5dB. The minimum noise figure is 4.dB. - 54 -
4. Future Work From chapter, the X-band back gate TF-QVCO could be modified as shown in Fig. 4-. We insert a resistor between the bias transistor as current source and the core circuit [6]. Low frequency bias noise is the dominant factor for the /f 3 phase noise. The filtering resistance can isolate the bias transistor from the cross-coupled pair and less bias noise can be upconverted into the /f 3 phase noise. As we increase the resistance, the /f phase noise performance will reach its optimum value and begin to degrade in the same way. This is because the thermal noise contribution overwhelms the phase noise reduction by the harmonic filtering. So there is a tradeoff between /f and /f 3 phase noise performance as a function of the filtering resistance. Fig. 4- Revised architecture of back gate TF-QVCO - 55 -
Appendix CMOS Low-Noise Amplifier for UWB System A. Introduction A low-noise amplifier is the first stage in the receiver block of a communication system. For UWB applications, the criteria to judge its performances are slightly different from narrow system. Because transmitted power spreads over a wide range and is restricted to be less than -4.3 dbm per MHz, the requirement on linearity in UWB system is not such important as in narrow system. The important requirements for UWB applications are wide-band input impedance matching, low power consumption, low noise performance, and enough gain to suppress noise of the next stages. Fig. A- shows the four basic 50 Ohm input matching techniques. However, these topologies have some drawbacks. The four input matching is only suit for narrow band amplifier [6][7][8][9][30]. (a) (b) - 56 -
(c) (d) Fig. A- Basic input matching topology. (a) Inductive source degeneration.(b) Direct resistor termination.(c) Shunt-series feedback.(d) Chebyshev band-pass filter Fig. A- (a) is traditional source degeneration topology, because it only resonances at one frequency, it can t achieve wide-band 50 Ohm matching. It realizes only narrow band matching. Fig. A- (b) is the resistive termination matching, because of the loading effect, it will loss a lot of voltage if resistive termination matching is used. Fig. A- (c) is feedback method. It can achieve wideband input matching. But because of feedback mechanism, it can t achieve high gain to suppress noise of the next stages. Fig. A- (d) is LC 3 rd Chebyshev band-pass filter. It can perform good input matching, but it consumes large chip area because of using four inductors for input matching. The noise performance of an LNA is directly dependent on its input matching. The wide-band input matching is intrinsically noisier than narrow-band counterparts as the noise performance can not be optimized for a specific frequency. Thus the designer has to be trade off between the input matching and noise. Distributed amplifiers [3] The Fig. A- shows a basic four-stage single-ended distributed amplifier. - 57 -
Fig. A- Basic four single-end distributed amplifier The distributed amplifiers normally provide wide bandwidth characteristics but they consume large dc current due to the distribution of multiple amplifying stages, which make them unsuitable for low-power application. And the distributed amplifiers are not optimized for noise. This bring the challenge of finding a low-power topology that satisfies all the other design requirements, the most stringent one being the input match. Ultra-wideband low noise amplifier using LC-ladder filter input matching network [3][33] Recently another topology of wideband LNA has been present. It expands the conventional narrow-band LNA using source degeneration by embedding the input network of the amplifying device in a multisection reactive network so that the overall input reactance is resonated over a wider bandwidth. Fig. A-3 shows a typical narrowband cascode LNA topology and its small-signal equivalent circuit. - 58 -
Fig. A-3 Narrowband LNA topology. (a) overall schematic. (b) Small-signal equivalent circuit at the input The inductor L s is added for simultaneous noise and input matching and L g for the impedance matching between the source resistance R s and the input of the narrowband LNA [4]. Fig. A-3(b) shows the equivalent small-signal circuit. Assume the gate-drain C gd can be ignored, the impedance of the gate terminal is a series RLC circuit. The reactive part of the input impedance is resonated at the carrier frequency in narrowband design. The basic concept of the LC-ladder input matching is expanded from the input impedance of the narrowband which is a series RLC circuit. Consider a fourth-order bandpass ladder filter, shown as in Fig. A-4. Fig. A-4 Fourth-order bandpass ladder filter used for impedance matching. The right part of the bandpass filter looks similar to the equivalent circuit of the inductively degenerated transistor in Fig. A-3(b). Therefore, the bandpass filter can embed the inductively degenerated transistor and obtain the desire input impedance. - 59 -
The LC-ladder filter input matching of wideband LNA has two significant drawbacks. Because the LC-ladder filter at the input mandates a number of reactive elements, which could lead to a larger chip area and noise figure degradation in the case of on-chip implementation. Ultra-wideband low noise amplifier using the common-gate as the first stage.[34] In traditional narrow-band receiver the common-gate is not used widely due to its relatively lower gain and higher noise figure than a common-source amplifier. The actual configuration of common-gate stage is shown in Fig. A-5(a). Fig. A-5 (a) Configuration of a common-gate input stage. (b) The small-signal equivalent circuit. From the Fig. A-5(b), we can derive the input impedance Z in = g m + Z s ( ω ) g mz o ( ω ) + R + Z ( ω ) o o g m j X ( s ω ) + R o jg m X o ( ω ) + jx ( ω ) o In below equation we assume that the Z s (ω) and Z o (ω) are both composed of high-q inductors and capacitors and can be regarded as purely reactive within the frequency band of interest. Z s ( ω) = jωls // = jx s ( ω), Zo ( ω) = // Z L // Z in = jωc jωc gs gd jx o ( ω) After some mathematical calculation - 60 -
Z in = ( g g m. X o ( ω) Ro + g mro m ) j( + X ( ω o R ( ω) X s ( ω) o + X o Ro + X o ( ω) Since g m X o (ω)<<r o +X o (ω),the real part in the denominator will remain relatively constant within the 3.-0.6GHz UWB band. The imperfect matching of the common-gate stage throughout the band arise from the frequency dependent Xs(ω) that dominates the imaginary part in the denominator. To get a good matching over the wide band, the LC tank of Xs(ω) formed by Ls and C gs should be selected such that they resonate at the center of the 3.-0.6GHz, leaving only a 50Ω real input impedance. The noise figure of the common-gate input stage UWB LNA can be improved by increasing g m but it will degrade the input matching. Wideband matching using the transistor intrinsic gate-drain capacitor [35] Recently a novel wideband input match has been present. It considers the gate-drain capacitor has significant effect on the circuit performance. The Fig. A-6 show a simple common source amplifier with source degeneration inductor and the drain loaded an equivalent capacitor and resistor from the next stage. )) Fig. A-6 The small signal equivalent circuit of common-source with inductive source degeneration The C gd and r o are neglected in conventional analysis of low noise amplifier. It is inaccurate numerically. If both C gd and r o are considered we will find that the input match at high frequency is depend on the resistive load and at low frequency is depend on the capacitive load. We can achieve wideband match without external input - 6 -
match network. It also can achieve low noise match. Therefore, we will adopt this wideband matching method as a part of the proposed LNA. A. Design Consideration A.. Wideband matching technique[35] Consider a small signal equivalent circuit of a source degeneration low noise amplifier which is shown in Fig. A-7. C L and R L present the parasitic capacitance and resistance which is contributed from the next stage. Fig. A-7 The small signal equivalent circuit of source degeneration To derive the input impedance we consider that the load of the circuit is divided into two parts, one of which is only a resistor R L which dominates at the high frequency and another is the capacitor C L dominates at the low frequency. The circuit of resistive loading is shown in Fig. A-8 Fig. A-8 The equivalent small signal circuit of resistive loading - 6 -
Z in While we assume that ( jωc gs Lsγg + C gs m C )[+ C L ω s << ωls R ωc << gd gs (+ γg m R gs L )], with L γ we can find the input impedance r r + R + = o. As frequency as o L jωl s high the input impedance will approach the 50Ω when the inductor Ls is designed properly. To derive the input impedance of the capacitive loading, which is shown in Fig. A-9, we divided this circuit into two branches and replace the current source by voltage source. Fig. A-9 The equivalent small signal circuit of capacitive loading One of the two branches is looking into the capacitor C gs and another is looking into the capacitor C gd. Y α is the impedance looking into the C gd and Z β is the impedance looking into the C gs. Assuming that the current flowing the capacitor C gd and C gs is smaller than the induced current g m V gs, the Y α can be derived. Thus Y gd and α = jωc + ( Rα + + jωlα ) jωcα Z β = jω + ( + jωc + ) β Cgs Rβ jωlβ CL LSCL with Rα =, Cα = gmro Cgd, Lα = ( + gmro ) g C g r C m gd m o gd g L Cgs L g r C Rβ =, Cβ =, Lβ = C g r C m s s m o L gs m o gs The input impedance of the capacitive loading circuit can be found out as follow - 63 -
Z in = ( Y α + Z β ). According to above the equations the input impedance can be rearranged as a simpler RLC circuit as shown in Fig.4-0 Fig. A-0 The equivalent circuit of input impedance The C gd branch is the critical branch that is a series component of RLC and its resonate frequency is f0 = π L C α α = π S L C (+ g L m. At the high frequency the r ) resistive loading is matched and the capacitive loading is matched at the comparatively low frequency. Thus the composite R L C L load circuit is matched over a wide bandwidth. o A.. Ultra Wide-band Low-Noise Amplifier Fig. A- shows a UWB LNA using transistor s intrinsic gate-drain capacitor to achieve input matching. In this design we add an inductor to the original R L C L loading circuit, as shown in figure Fig. A-. - 64 -
Fig. A- The schematic of the proposed UWB LNA Fig. A- The equivalent circuit of first stage UWB LNA In this circuit the external C ex is added to increase the equivalent gat-drain capacitance, thus allowing a smaller transistor to get better input match but it effect the noise figure at lower frequency. The inductor L i can improve the input matching. To improve the input match at lower frequency the gate inductor is added and it will influence the noise figure. Shunt-series-peaking is a bandwidth extension technique [36] which is used in this circuit to extend bandwidth by the inductor L d, L i and resistor R d. To achieve a flat gain over whole frequency range we cascade three stages. - 65 -
The concept of this design is that we design the first stage with a capacitive, resistive and inductive load to achieve the input return loss first. The transformer is added to improve the input return loss and flatter gain but it may make the circuit become a little unstable and it has to be design carefully. The value of capacitive load is approximated to the next input impedance of next stage. Due to the input impedance of the common source topology is the series resistance, capacitor and inductor it is suited to be the consequence stage. We use the common source topology to be the second and third stage. Then we replace the resistance by the common source stage with a capacitive, inductive and resistive load and fine tune all elements to get required specification. The three stages are response for different band of gain to maintain the flatter gain over whole wide band. A.3 Chip implementation and Measured Results The chip layout and photo of the UWB LNA is shown in Fig. A-3. The power supply (Vdd) is V. The 0.8µm (minimum) gate length was chosen to get the highest speed. The MIM (Metal-Insulator-Metal) capacitors without shield and hexagonal spiral inductors (the Q-value is below 8) are used in this work. Guard-rings are added with all elements to prevent substrate noise and interference. A shielded signal GSG pad structure is used in RF input and RF output to reduce the coupling noise from the noisy substrate. All interconnections between elements are taken as a 45 corner. The chip size is.48x.03 mm. All connection wire are simulated by ADS momentum to extract parasitical effect. - 66 -
(a) (b) Fig. A-3(a) the chip layout (b) the chip photograph The UWB LNA is designed for on-wafer measurement so the layout must satisfy the rules of CIC s (Chip Implementation Center s) probe station testing rules. The measurement equipments include a network analyzer ( HP850C ), a noise analyzer ( Agilent N8975A ), a spectrum analyzer ( Agilent E4407B ), two signal generators, and several dc power supplies. Besides, this circuit needs two 6-pin DC PGPPGP probe and - 67 -
two RF GSG probes for on-wafer measurement. Fig. A-4 show the measurement setup for S-parameters, noise figure, db compression point and third-order intercept point. Angilent-850C network analyzer N 8975A Noise Analyzer (a) (b) (c) - 68 -
(d) Fig. A-4 Measurement setups for (a) S-parameter (b) noise figure (c) PdB (d) IIP3 The S-parameter are shown in Fig. A-5(a)~(d), where the measured S < -8dB and S < -3 db from 3. GHz to 0.6 GHz. The power gain (S) is around 5dB from 3. to 8 GHz, except the point which produces peak value, the 3dB bandwidth is.9-9 GHz. The measured noise figure of 4.-5.4 db from 3. to 0.6 GHz has been presented as shown in Fig. A-6. The measured P db are -7dBm at 3 GHz, and -3.5dBm at 9 GHz in Fig. A-7(a)~(c). The measured IIP3 are -7.5dBm at 3 GHz, and -5dBm at 9 GHz in Fig.A-7,A-8. Table A- summarizes the measured data of proposed wideband LNA. Table A- summarizes the comparison of proposed wideband LNA. - 69 -