1 02 * Floating-gate Non-volatile Semiconductor Memory Dawon Kahng [1] Bell Laboratories ** Magnetic Core Memory [2] Meta

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1 1 02 * Floating-gate Non-volatile Semiconductor Memory Dawon Kahng [1] Bell Laboratories ** Magnetic Core Memory [2] Metal-oxide-semiconductor, MOS MOSFET [3] * Proceedings of the International Symposium on Nonvolatile Memory the Technology Driver of the Electronics Industry, National Chiao Tung University, Hsinchu, Taiwan, March ** 3 1

2 * NANO COMMUNICATION 19 No.1 03 George Carey Andy Loya Marty Lepselter Zr ZrO [1] Bell System Technical Journal 7 1 BSTJ, Vol. 46, p (1967) *** [4, 5] BIOS iphone ipad DVD 1997 MP ipod mini GPS DVD Ultrabook [5] bits ,000 [6,7] [1] *** Field Effect Semiconductor Apparatus with Memory Involving Entrapment of Charge Carriers ,500,142

3 Floating Gate 1 M(1) I(1) I(2) M(1) 2 2a M(2) FN Fowler- Nordheim Tunneling I(1) I(1) I(2) 2b M(2) FN 2c 5 SiO 2 I(1) 100 Zr M(1) 100 ZrO 2 I(2) M(2) 50 V 0.5 µs EEPROM [1] (a) (b) V G 50 V t 1 = 0.5 µs 4 A B Threshold Voltage 0.25 ma Channel 2 (a) (b) (c) 3 50%

* NANO COMMUNICATION 19 No.1 05 6 (a) FAMOS [9] (b) SAMOS [10] 5 1 3.

4 * NANO COMMUNICATION 19 No (a) FAMOS [9] (b) SAMOS [10] Frohman-Bentchkowsky a EEPROM V T 4 V T Q /C FC Q C FC [8] 5 V T 6V s FAMOSAvalanche-injection MOS EPROM [9] 3.1 ev FAMOS

1 06 8 (a) NOR 1 [12] (b) NAND 16 2 [13] 32 64 I i z u k a 1 9 7 6 6 b SAMOS MOS [10] EEPROM 1 Fowler-Nordheim EEPROM EEPROM MOSFET 1984 Masuoka 7 [11] A-A B-B

5 (a) NOR 1 [12] (b) NAND 16 2 [13] I i z u k a b SAMOS MOS [10] EEPROM 1 Fowler-Nordheim EEPROM EEPROM MOSFET 1984 Masuoka 7 [11] A-A B-B EEPROM Masuoka NOR-Flash NAND-Flash 8 [12,13] NOR Flash NAND Flash 16 NOR Flash NAND Flash NOR Flash EEPROM NOR Flash NAND Flash EEPROM Bit [14]

Multi-level Cell Bauer 1995 Multilevel Cell, MLC [15] MLC Singlelevel Cell, SLC MLC MLC SLC 10 SLC MLC SLC MLC 2 MLC 3 MLC 4 MLC 2 3 =

6 * NANO COMMUNICATION 19 No.1 07 Alterability NOR Flash NAND Flash 9 [14] MP3 Ultrabook NAND Flash 2005 NAND Flash % 4. Multi-level Cell Bauer 1995 Multilevel Cell, MLC [15] MLC Singlelevel Cell, SLC MLC MLC SLC 10 SLC MLC SLC MLC 2 MLC 3 MLC 4 MLC 2 3 = = Through Silicon Via, TSV [16] 1Tb Solid-state Drive, SSD 32 NAND Flash 32 Gb Footprint 2.52 cm 2 1 Tb SSD 37 cm Dual Control-gate with Surrounding Floating-gate DC-SF NAND [18] 12a 12b MLC 63 DC-SF 1 Tb NAND Flash 10 (a) 1 (b) 2 11

7 NAND Flash [18] (a) (b) BIOS HDD HDD HDD GB NAND Flash NAND Flash 1987 $600,000/GB 256 kb SLC [14] 2010 $1.0/GB 64 Gb MLC $1/ GB Ultrabook HDD HDD NAND Flash GB 2015 NAND Flash [14,19] GB HDD [4] %

15 [5] 35 16 1990 300 5 15 GPS ABS EBS ETC IC MRI 15 2010

8 * NANO COMMUNICATION 19 No GB SSD **** 14 [4] 2011 ***** 97% 3 100% 15 [5] GPS ABS EBS ETC IC MRI [4,5] EKG 16 [4,5] [20] **** 2% Floating Trap 7 ***** 3% 2014 MP3

9 Half Pitch [21] [21,22] Retention Endurance Trap SLC Flash MLC Flash Cross Talk V T Memory Window Dielectric Leakage Substrate Doping Gate Granularity Substrate TrapCapture and Emission Random Telegraph Noise, RTN V T = q l/c FS + l/c FC q C FS 18 (a) [25] (b) [26]

10 * NANO COMMUNICATION 19 No.1 11 C Fc C FS C Fc ECC Parallel/Shadow Programming Wearlevel Incremental Step Pulse Programming, ISPP V T 7. (1) MOS (2) [23] 7.1 Floating Trap 18a 1 Wegener MNOS [24] 18a SONOS [25] SONOS 18b Tiwari [26] Single-Electron Memory Cell, SEMC Yano [27] 1994 SEMC Guo 7 7 [28] SEMC SEMC 2 Coulomb Blockade q/2c q C 7.2 U n i f i e d Memory 19 5 DRAM 10 ns SRAM.5 ns [19] FeRAM Perovskite Remanent Polarization PCRAM RAM Chalcogenide RRAM RAM 19

11 1 12 PZT Ta 2 O 5 STT-MRAM RAM MRAM CMOS FAMOS SAMOS Norman Erdos R. M. Ryder G. E. Smith [1] D. Kahng and S. M. Sze, "A Floating Gate and its Application to Memory Devices," Bell Syst. Tech. J., 46, 1288, [2] A. Wang and W. D. Woo, "Static Magnetic Storage and Delay Line," J. Appl. Phys., 21, 49, [3] For a discussion of MOSFET and non-volatile memory devices, see for example: (1) S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3rdEd., Wiley Interscience, Hoboken, N.J (2) T. Y. Tseng and S. M. Sze, Eds, Nonvolatile Memories: Materials, Devices, and Applications, American Scientific Publishers, Stevenson Ranch, CA, [4] R. N. Castellano, NVSM's Penetration in Electronics Industry, The Information Network, [5] A Niebel, Nonvolatile Semiconductor Memory Applications and Market, Web-feet Research Inc., Monterey, CA, [6] T. Coughlin, "2009 Conference on an Entertainment Storage Alliance Event," Proc. Storage Visions, p.22, Las Vegas, Nevada, Jan. 6, [7] C. Y. Lu. and H. Kuan, "Nonvolatile Semiconductor Memory Revolutionizing Information Storage," IEEE Nanotechnology Mag., p.4, Dec [8] P. Pavan, R. Bez, P. Olive, and E. Zanoni, "Flash Memory Cells-An Overview," Proc. IEEE 85, 1248, [9] D. Frohman-Bentchkowsky, "Memory Behavior in a Floating-gate Avalanche-Injection MOS (FAMOS) Structure,"Appl. Phys. Lett., 18, 332, [10] H. Iizuka, F. Masuoka, T. Sato, and M. Ishikawa, "Electrically Alterable Avalanche Injection Type MOS Read-Only Memory with Stacked Gate Structure," IEEE Trans. Elec. Dev., ED-23, 379, [11] F. Masuoka, M Asano, M. Iwahashi, T. Komuro, and

12 * NANO COMMUNICATION 19 No.1 13 S. Tanaka, "A New Flash EEPROM Cell Using Triple Polysilicon Technology," IEEE IEDM Tech. Dig., p.464, [12] F. Masuoka, M.Asano, H. Iwahashi, T. Komuro, and S. Tanaka, "A 250K Flash EEPROM Using Triple Polysilicon Technology," IEEE ISSCC Tech. Dig., p.168, [13] F. Masuoka, M. Momodomi, Y. Iwata, and R. Shirora, "New Ultra High Density EPROM and Flash EEPROM with NAND Structured Cell," IEEE IEDM Tech. Dig., p.552, [14] Global Semiconductor Devices:Applications, Market, and Trend Analysis. Topology Research Institute, Taipei, Taiwan, Dec [15] M. Bauer, R. Alexis, G. Atwood, B. Baltar, A. Fazio, K. Frary, M. Hensel, et al.,"a Multilevel-cell 32Mb Flash Memory," IEEE ISSCC Tech.Dig., p.132, [16] R. Micheloni, L. Crippa, A. Grossi, and P. Tessariol, "High-capacity NAND Flash Memories: XLC Storage and Single-die 3D," a chapter in Memory Mass Storage, Ed,G. Campardo et al., Springer-Verlag, Berlin, [17] J. S. Lee, "Prospects and Challenges of Next-generation Flash Memory Devices," a chapter in Future Trends in Microelectronics-From Nanophotonics to Sensorsand Energy, Eds, S. Luryi, J. Xu and A. Zaslavsky, Wiley, Hoboken, N.J [18] S. J. Whang, K. H. Lee, et al, "Novel 3-dimensional Dual Control-gate with Surrounding Floating-gate (DC-SF) NAND Flash Cell for 1Tb File Storage Applications," IEEE IEDM Tech. Dig., p.668, [19] G. W. Burr, B. N.Kurdi, J.C. Scott et al., "Overview of Candidate Device Technologies for Storage-class Memory," IBM J. Res. & Dev., 52, 449 (2008). [20] "Process Integration Devices and Structures", The International Technology Roadmaps for Semiconductors, Ghetti and A. Uisconti, "Emerging Constraints to NAND Flash Memory Reliability,"a chapter in Nonvolatile Memories : Materials, Devices, and Applications, Eds, T. Y. Tseng and S. M. Sze, American Scientific Publishers, Stevenson Ranch, CA, [22] D. Ielmimi, "Reliability Issues and Modeling of Flash and Post-flash Memory," Microelectronic Engineering, 86, 1870, [23] T. C. Chang, F. Y. Jian, S. C. Chen, and C. T. Tsai, "Nonvolatile Memory Devices with Nanocrystals and Dielectrics," a chapter in Nonvolatile Memories : Materials, Devices, and Applications, Eds, T. Y. Tseng and S. M. Sze, American Scientific Publishers, Stevenson Ranch, CA, (2012). [24] H. Wegener, A. Lincoln, H. Pao, M. O'Connell, R. Oleksiak, and H. Lawrence, "The Variable-Threshold Transistor, a New Electrically-alterable, Nondestructive READ-only Storage Device, "IEEE IEDM Tech. Dig., p.70 (1967). [25] B. Kashavan and H. C. Lin, "MONOS Memory Element, "IEEE IEDM Tech. Dig., p.140(1968).the M (metal) in MONOS is replaced by S (Semiconductor) in SONOS. [26] S. Tiwari, F. Rana, K. Chan, H. Hanafi, W. Chan, and D. Buchanan, "Volatile and Non-volatile Memories in Silicon with Nano-crystal Storage, "IEEE IEDM Tech. Dig., p.521, [27] K. Yano, T. Ishii, T. Hashimoto, T. Kabayashi, F. Murai, and K. Seki, "Room Temperature Single-electron Memory," IEEE Trans. Electron Dev. 41, 1628, [28] L. Guo, E. Leobandung, and S. Y. Chou, "A Roomtemperature Silicon Single-electronic Metal-oxidesemiconductor Memory with Nano Scale Floating-gate and Ultranarrow Channel," Appl. Phys. Lett., 70, 850, [21] C. M. Compagnoni, A. Spinelli, and A. L. Lacaita, A.

1 02 Zn-doped Silicon Dioxide Resistance Random Access Memory Resistance Random Access Memory : RRAM RRAM SiO 2 IC SiO 2 SiO 2 S

1 02 Zn-doped Silicon Dioxide Resistance Random Access Memory 1 2 2 2 1 3 4 1 2 3 4 Resistance Random Access Memory : RRAM RRAM SiO 2 IC SiO 2 SiO 2 SiO 2 IC IC Abstract Among the next-generation memory