PHN LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC ) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V DS Drain-source

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1 PHN FEATURES SYMBOL QUICK REFERENCE DATA mω isolation transistor mω spindle transistors TrenchMOS technology Logic level compatible Surface mount package D G G G isolation FET S G S S S D D D G G G S S S V DS = V I D = A R DS(ON) mω (V GS = V; isolation FET) R DS(ON) mω (V GS = V; spindle FETs) GENERAL DESCRIPTION This product is used to drive high performance, three phase brushless d.c. motors in computer disk drives. The PHN contains seven, n-channel enhancement mode trenchmos transistors in a surface mounting plastic package. Six of the transistors can be configured as a three phase bridge to drive the spindle of a disk drive motor. The remaining transistor delivers power to the three phase bridge during normal operation. In the event of a power failure occurring whilst the motor is still spinning, this transistor isolates the computer power supply from the back emf generated by the motor. The PHN is supplied in the surface mounting SOT- (SSOP) package. PINNING PIN DESCRIPTION PIN DESCRIPTION, drain, source source gate gate gate, drain source source gate gate source 9, drain gate source source gate -,9,,, drain SOT- (SSOP) Top view May 999 Rev.

2 PHN LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC ) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V DS Drain-source voltage T j = C to C - V V DGR Drain-gate voltage R GS = kω - V V GS Gate-source voltage - ± V I D Peak drain current per device T sp = C (continuous operation) spindle FETs; δ =.% - A Isolation FET (dc) - A I DM Peak current per device (pulse spindle FETs - A peak value) isolation FET - A P tot Power dissipation per device T sp = C spindle FETs; δ =.% -. W isolation FET (dc) -. W P tot Total power dissipation in normal T sp = C - W operation spindle FETs; δ =.% isolation FET (dc) T stg, T j Storage & operating temperature - C THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT R th j-sp Thermal resistance junction to isolation FET - K/W solder point spindle FET - K/W R th j-a Thermal resistance junction to device soldered to FR board, ambient minimum footprint. isolation FET - K/W spindle FET - K/W T sp is the temperature at the soldering point of the drain leads. In normal operation, the isolation FET conducts continuously whilst each of the spindle FETs conducts for.% of the time. The dissipation in the isolation transistor is given by:- P isolation = I xr DS(ON)(isolationFET) The dissipation in each of the spindle transistors is given by:- P spindle =.xi xr DS(ON)(spindleFET) The total dissipation under these conditions is given by:- P tot = P isolation + xp spindle With the motor being driven at A and assuming T j = C, the total dissipation is:- P tot = x.x. +.xx.x.x = W Switching losses are assumed to be negligible. May 999 Rev.

3 PHN ELECTRICAL CHARACTERISTICS T j = C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V (BR)DSS Drain-source breakdown V GS = V; I D = µa - - V voltage V GS(TO) Gate threshold voltage V DS = V GS ; I D = ma.. - V R DS(ON) Drain-source on-state V GS = V; I D = A resistance spindle FET - mω isolation FET - mω R DS(ON) Drain-source on-state V GS =. V; I D = A resistance spindle FET - 9 mω isolation FET - mω R DS(ON) Drain-source on-state V GS = V; I D = A; T j = C resistance spindle FET - mω isolation FET - mω I GSS Gate source leakage current V GS = ± V; V DS = V - na I DSS Zero gate voltage drain V DS = V; V GS = V; - na current T j = C -.. ma Q g(tot) Total gate charge I D = A; V DD = V; V GS = V spindle FET -. - nc isolation FET -. - nc Q gs Gate-source charge spindle FET -. - nc isolation FET -. - nc Q gd Gate-drain (Miller) charge spindle FET -. - nc isolation FET -. - nc t on Turn-on time V DD = V; I D = A; V GS = V; R G = Ω; resistive load spindle FET -. ns isolation FET - ns t off Turn-off time spindle FET - ns isolation FET - ns C iss Input capacitance V GS = V; V DS = V; f = MHz spindle FET - - pf isolation FET - - pf C oss Output capacitance spindle FET - - pf isolation FET - - pf C rss Feedback capacitance spindle FET - - pf isolation FET - - pf May 999 Rev.

4 PHN SOURCE-DRAIN DIODE LIMITING VALUES AND CHARACTERISTICS T j = C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT I F Continuous forward diode T sp = C current spindle FET; δ =.% - - A isolation FET - - A I FRM Repetitive peak forward diode spindle FET - - A current isolation FET - - A V F Diode forward voltage I F =. A; V GS = V spindle FET -. V isolation FET -. V t rr Reverse recovery time I F =. A; -di F /dt = A/µs; V DS = V spindle FET - - ns isolation FET - - ns 9 Normalised Power Derating, Ptot (%) Solder Point temperature, Tsp (C) Fig.. Normalised power dissipation. PD% = P D /P D C = f(t sp ) Normalised On-state Resistance Junction temperature, Tj (C) Fig.. Normalised drain-source on-state resistance. R DS(ON) /R DS(ON) C = f(t j ) Normalised Current Derating, ID (%) Solder Point temperature, Tsp (C) Fig.. Normalised continuous drain current. ID% = I D /I D C = f(t sp ); conditions: V GS V.... Threshold Voltage, VGS(TO) (V)..... minimum typical Junction Temperature, Tj (C) Fig.. Gate threshold voltage. V GS(TO) = f(t j ); conditions: I D = ma; V DS = V GS May 999 Rev.

5 PHN.E- Drain current, ID (A) VDS = V Transient thermal impedance, Zth j-a (K/W) D =..E-..E- minimum....e- typical P D tp D = tp/t.e-. single pulse T.E-... Gate-source voltage, VGS (V) Fig.. Sub-threshold drain current. I D = f(v GS) ; conditions: T j = C. E- E- E- E- E- E- E+ E+ Pulse width, tp (s) Fig.. Transient thermal impedance (spindle FET). Z th j-sp = f(t); parameter D = t p /T Peak Pulsed Drain Current, IDM (A) Transient thermal impedance, Zth j-a (K/W) RDS(on) = VDS/ ID tp = us D =. us... D.C. ms ms.. single pulse P D tp D = tp/t. ms. Fig.. Safe operating area (spindle FET) T sp = C I D & I DM = f(v DS ); I DM single pulse; parameter t p. E- E- E- E- E- E- E+ E+ Pulse width, tp (s) Fig.9. Transient thermal impedance (isolation FET). Z th j-sp = f(t); parameter D = t p /T T. Peak Pulsed Drain Current, IDM (A) RDS(on) = VDS/ ID D.C. tp = us ms ms ms. Fig.. Safe operating area (isolation FET) T sp = C I D & I DM = f(v DS ); I DM single pulse; parameter t p Drain Current, ID (A) VGS = V. V. V. V. V. V. V Fig.. Typical output characteristics (spindle FET) T j = C; I D = f(v DS ); parameter V GS V May 999 Rev.

6 PHN Drain Current, ID (A) VGS =. V V 9. V.. Drain current, ID (A) VDS > ID X RDS(ON). V.. V. V. V Fig.. Typical output characteristics (isolation FET) T j = C; I D = f(v DS ); parameter V GS V.. C..... Gate-source voltage, VGS (V) Fig.. Typical transfer characteristics (spindle FET) I D = f(v GS ) Drain-Source On Resistance, RDS(on) (Ohms).. V. V.V. V V.. Drain current, ID (A) VDS > ID X RDS(ON)..... VGS =. V Drain Current, ID (A) Fig.. Typical on-state resistance (spindle FET) T j = C; R DS(ON) = f(i D ); parameter V GS V.. C..... Gate-source voltage, VGS (V) Fig.. Typical transfer characteristics (isolation FET); I D = f(v GS ) Drain-Source On Resistance, RDS(on) (Ohms). V. V.V. V.. Transconductance, gfs (S) VDS > ID X RDS(ON)... C.. VGS =. V.. 9 Drain Current, ID (A) Fig.. Typical on-state resistance (isolation FET) T j = C; R DS(ON) = f(i D ); parameter V GS V..... Drain current, ID (A) Fig.. Typical transconductance (spindle FET) T j = C; g fs = f(i D ) May 999 Rev.

7 PHN Transconductance, gfs (S) 9 VDS > ID X RDS(ON) C 9 Drain current, ID (A) Fig.. Typical transconductance (isolation FET) T j = C; g fs = f(i D ) 9 Gate-source voltage, VGS (V) ID = A VDD = V Gate charge, QG (nc) Fig.. Typical turn-on gate-charge characteristics (spindle FET); V GS = f(q G ) Capacitances, Ciss, Coss, Crss (pf) Ciss Coss Crss. Fig.. Typical capacitances (spindle FET) C = f(v DS ); conditions: V GS = V; f = MHz Gate-source voltage, VGS (V) 9 ID = A VDD = V Gate charge, QG (nc) Fig.. Typical turn-on gate-charge characteristics (isolation FET); V GS = f(q G ) Capacitances, Ciss, Coss, Crss (pf).. Source-Drain Diode Current, IF (A) VGS = V Ciss.. C Coss. Crss Source-Drain Voltage, VSDS (V) Fig.9. Typical capacitances (isolation FET) C = f(v DS ); conditions: V GS = V; f = MHz Fig.. Typical reverse diode current (spindle FET) I F = f(v SDS ); conditions: V GS = V; parameter T j May 999 Rev.

8 PHN 9 Source-Drain Diode Current, IF (A) VGS = V C Source-Drain Voltage, VSDS (V) Fig.. Typical reverse diode current (isolation FET) I F = f(v SDS ); conditions: V GS = V; parameter T j May 999 Rev.

9 PHN MECHANICAL DATA SSOP: plastic shrink small outline package; leads; body width. mm SOT- D E A X c y H E v M A Z Q pin index A A (A ) A θ L L p detail X e b p w M. mm scale DIMENSIONS (mm are the original dimensions) A UNIT A A A b p c D () E () e H () E L L p Q v w y Z max mm θ o o Note. Plastic or metal protrusions of. mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ SOT- MO-AH EUROPEAN PROJECTION ISSUE DATE Fig.. SOT- (SSOP) surface mounting package. Notes. This product is supplied in anti-static packaging. The leads must be protected against static discharge during transport or handling.. Refer to Integrated Circuit Packages, Data Handbook IC.. Epoxy meets UL9 V at /". May Rev.

10 PHN DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC ). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. May 999 Rev.

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