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1 Chapter 11 Basic I/O Interface The operation of the basic input and output interface Decode any 8-, 16-, and 32-bit I/O device Handshaking Interface and program the 82C55 programmable parallel interface Interface LCD, LED,keyboards, ADC, DAC, and various other devices to the 82C55 Interface and program the 8279 programmable keyboard/display controller Interface and program the serial communication interface adapter Interface both DC and stepper motors to the microprocessor

2 I/O Instructions IN, OUT: transfer information between accumulator register and an I/O device INS, OUTS: transfer strings of data between the memory and an I/O device Fixed address: p8 (8-bit) Variable address: address in DX (16-bit)

3 Input/output instructions Instruction IN Al, p8 IN AX, p8 IN EAX, p8 IN AL, DX IN AX, DX IN EAX, DX INSB, INSW, INSD OUT p8, AL OUT p8, AX OUT p8, EAX OUT DX, AL OUT DX, AX OUT DX, EAX OUTSB, OUTSW, OUTSD Data Width ,16, ,16, 32 Function A byte is input from port p8 into AL A byte is input from the port addressed by DX into AL A byte, or word, or doubleword is input from the port addressed by DX into the extra segment memory location addressed by DI, then DI= DI+/-1, or 2, or 4 A byte is output from AL to port p8 A byte is output from AL to the port addressed by DX A byte, or word, or doubleword is output from the the data segment memory location addressed by SI to the port addressed by DX, then SI= SI+/-1, or 2, or 4

4 Whenever data are transferred by using the IN or OUT instruction, the I/O address, often called a port number, appears on the address bus The 8-bit fixed port number (p8) appears on address bus connections A7-A0 with A15-A8 equal to B The address connections above A15 are undefined for an I/O instruction The 16-bit variable port number (DX) appears on address connection A15-A0

5 The first 256 I/O port addresses (00H-FFH) are accessed by both the fixed and variable I/O instructions All I/O address from 0100H-FFFFH is only accessed by the variable I/O address The INS and OUTS instructions address an I/O device by using the DX register

6 Isolated and Memory-Mapped I/O FFFFF Memory 1M * 8 FFFF I/O 64K * Isolated I/O for the 8086/8088 microprocessors

7 FFFFF Memory + I/O I/O Memory-mapped I/O for the 8086/8088 microprocessors

8 Isolated I/O The addresses for isolated I/O devices are separate from the memory In the isolated I/O scheme, the IN, INS, OUT, and OUTS instructions transfer data between the microprocessor s accumulator or memory and the I/O device Separate control signals for the I/O space are developed (using M/IO and W/R), which indicate an I/O read (/IORC) or an I/O write (/IOWC) operation

9 Memory-Mapped I/O Unlike isolated I/O, memory-mapped I/O does not use the IN, INS, OUT, or OUTS instructions Instead, it uses any instruction that transfers data between the microprocessor and memory A memory-mapped I/O device is treated as a memory location in the memory map

10 PC I/O Map I/O space between ports 0000h and 03FFH are normally reserved for the computer system and the ISA bus The I/O ports located at 0400H-FFFFH are generally available for user applications, main-board functions, and PCI bus

11 FFFF I/O Expansion area The I/O map of a PC illustrating many of the fixed I/O areas FF 03E F0 03EF 03E0 03DF 03D0 03CF F F F FF 02F8 02F F F F F 0000 COM1 Floppy disk CGA adapter LPT 1 Hard disk COM Timer Interrupt controller DMA controller

12 Basic Input and Output Interfaces The basic input device is a set of three-state buffers The basic output device is a set of data latches

13 VCC o 10K* A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 U1 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y Data Bus 1 o 1G 19 o 2G 74LS244 /SEL The basic input interface illustrating the connection of eight switches

14 The Basic Input Interface The external TTL data (toggle switches) are connected to the inputs of the buffers The outputs of the buffers connect to the data bus The microprocessor reads the contents of the 8 switches when the signal /SEL becomes a logic 0 Whenever the IN instruction executes, the contents of the switches are copied into the AL register

15 When the microprocessor executes an IN instruction, the I/O port address is decoded to generate the logic 0 on /SEL A 0 placed on the output control inputs (/1G and /2G) of the 74LS244 buffer causes the data input connections (A) to be connected to the data output (Y) connections If a logic 1 is placed on the output control inputs of the 74LS244 buffer, the device enters the three-state highimpedance mode that effectively disconnects the switches from the data bus

16 The Basic Output Interface When the OUT instruction executes, the data from accumulator register are transferred to the latch via the data bus Each time when the OUT instruction executes, the /SEL signal to the latch activates, capturing the data output to the latch from any 8-bit section of the data bus The data are held until the next OUT instruction executes

17 VCC o 330*8 Data Bus D0 D1 D2 D3 D4 D5 D6 D7 U1 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q o OC CLK 74LS374 The basic output interface connected to a set of LED displays /SEL

18 Handshaking Many I/O devices accept or release information at a much slower rate than the microprocessor The handshaking method synchronizes the I/O device with the microprocessor An example device that requires handshaking is a parallel printer that prints 100 characters per second (CPS) Obviously, a microprocessor can send more than 100 CPS to the printer

19 Data are transferred through a serious of data connections (D7-D0) BUSY indicates that the printer is busy /STB is a clock pulse used to send data into the printer for printing As soon as the printer receives the data, it places a logic 1 on the BUSY pin, indicating that the printer is busy printing data The microprocessor software tests the BUSY pin to decide whether the printer is busy

20 The DB25 connector found on the computers for the parallel printer interface DB25 Pin number Function /STB D0 D1 D2 D3 D4 D5 D6 D7 /ACK BUSY

21 ;a procedure that printers the ASCII contents of BL. ; PRINT PROC NEAR 0000 E4 4B 0002 A FA A C E6 4A 000A CB IN AL, BUSY TEST AL, BUSY_bit JNE PRINT MOV AL, BL OUT PRINTER, AL RET ;get BUSY flag ;test BUSY bit ;if printer busy ;get data from BL ;send data to printer ;return from procedure 000B PRINT ENDP

22 Notes About Interfacing Circuitry TTL: logic 0 (0-0.8V), and logic 1 ( V)

23 Input Devices o VCC 2.2K SPSL TTL Output A single-pole, singlethrow switch interfaced as a TTL device

24 Output Devices o VCC LED 330 Input 2N K Interfacing an LED by using a transistor

25 o VCC LED 330 Input LS04 Interfacing an LED by using an inverter

26 o VCC M Input 6.2K A DC motor interfaced to a system by using a Darlington-pair

27 I/O Port Decoding We decode A31-A0, A23-A0, or A19-A0 for memory and memory-mapped I/O, and A15-A0 for isolated I/O If the I/O devices use only fixed I/O addressing, only A7-A0 is decoded /IORC and /IOWC are used to activate I/O device for a read or write operation On earlier versions of the microprocessor, IO/M= 1 and /RD or /WR are used to activate I/O devices On the newest versions of the microprocessor,the M/IO=0 and W/R are used to activate I/O devices

28 Decoding 8-bit I/O Addresses The fixed I/O instruction uses an 8-bit I/O port address that appears on A15-A0 as 0000H-00FFH If a system will never contain more than 256 I/O devices, we often decode only address connections A7- A0 for an 8-bit I/O port address, ignoring address connection A15-A8 DX register can also address I/O ports 00H-FFH

29 A5 A6 A7 A0 A1 A2 A4 A o o A B C G1 G2A 5 o G2B 15 Y0 o 14 Y1 o 13 Y2 o 12 Y3 o 11 Y4 o 10 Y5 o 9 Y6 o 7 Y7 o /FOH /F1H /F2H /F3H /F4H /F5H /F6H /F7H 74LS10 74LS138 A port decoder that decodes 8-bit I/O ports. This decoder generates active low outputs for ports F0H-F7H

30 A0 A1 A2 A3 A4 A5 A6 A I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 19 O1 o 18 O2 o 17 O3 o 16 O4 o 15 O5 o 14 O6 o 13 O7 o 12 O8 o /FOH /F1H /F2H /F3H /F4H /F5H /F6H /F7H 16L8 A PAL16L8 decoder that generates I/O port signals for port F0H-F7H

31 AUTHOR Barry B. Brey COMPANY BreyCo DATE 7/1/99 CHIP DECODER8 PAL16L8 Pins A0 A1 A2 A3 A4 A5 A6 A7 NC GND Pins NC F7 F6 F5 F4 F3 F2 F1 F0 VCC EQUATIONS /F0= A7*A6*A5*A4*/A3*/A2*/A1*/A0 /F1= A7*A6*A5*A4*/A3*/A2*/A1*A0 /F2= A7*A6*A5*A4*/A3*/A2*A1*/A0 /F3= A7*A6*A5*A4*/A3*/A2*A1*A0 /F4= A7*A6*A5*A4*/A3*A2*/A1*/A0 /F5= A7*A6*A5*A4*/A3*A2*/A1*A0 /F6= A7*A6*A5*A4*/A3*A2*A1*/A0 /F7= A7*A6*A5*A4*/A3*A2*A1*A0

32 Decoding 16-bit I/O Addresses A A15 A14 A13 A11 A10 A9 A8 74LS LS30 A0 A1 A2 A3 A4 A5 A6 A7 8 o I1 I2 I3 I4 I5 I6 I7 I8 9 I9 11 I10 16L8 O1 19 o O2 18 o O3 17 o O4 16 o O5 15 o O6 14 o O7 13 o O8 12 o /EFF8 /EFF9 /EFFA /EFFB /EFFC /EFFD /EFFE /EFFF A PAL 16L8 decoder that decodes 16-bit address EFF8H-EFFFH

33 AUTHOR Barry B. Brey COMPANY BreyCo DATE 7/2/99 CHIP DECODER9 PAL16L8 Pins A0 A1 A2 A3 A4 A5 A6 A7 NAND GND Pins NC EFFFH EFFEH EFFDH EFFCH EEEBH EFFAH EFF9H EFF8H VCC EQUATIONS /EFF8H= A7*A6*A5*A4*A3*/A2*/A1*/A0*/NAND /EFF9H= A7*A6*A5*A4*A3*/A2*/A1*A0*/NAND /EFFAH= A7*A6*A5*A4*A3*/A2*A1*/A0*/NAND /EFFBH= A7*A6*A5*A4*A3*/A2*A1*A0*/NAND /EFFCH= A7*A6*A5*A4*A3*A2*/A1*/A0*/NAND /EFFDH= A7*A6*A5*A4*A3*A2*/A1*A0*/NAND /EFFEH= A7*A6*A5*A4*A3*A2*A1*/A0*/NAND /EFFFH= A7*A6*A5*A4*A3*A2*A1*A0*/NAND

34 8- and 16-bit I/O Ports Being similar to memory write, two I/O banks exist, and any 8-bit I/O write requires a separate write strobe Figure illustrates a system that contains two different 8-bit output devices, located at 8-bit I/O address 40H and 41H Ports 40H and 41H can each be addressed as separate 8-bit ports, or together as one 16-bit port

35 FFFF FFFD FFFB /BHE FFFE FFFC FFFA /BLE (A0) High bank Low bank D15-D D7-D0 The I/O banks found in the 8086, 80186,80286, and 80386SX

36 An I/O port decoder that selects ports 40H and 41H o 74LS374 Port 41H OC CLK U2 D0 D1 D2 D3 D4 D6 D5 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Port 40H O1 O8 I1 I2 A3 A7 A6 /IORC A1 A2 A4 A5 I3 I5 I6 I o o o o o o o o O7 O6 O5 O4 O3 O2 16L8 I4 I8 I10 I U1 D7-D0 D15-D o 74LS OC CLK U3 D0 D1 D2 D3 D4 D6 D5 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q A0 /IOWC

37 AUTHOR Barry B. Brey COMPANY BreyCo DATE 7/1/99 CHIP DECODER8 PAL16L8 Pins BHE IOWC A0 A1 A2 A3 A4 A5 A6 GND Pins A7 NC NC NC NC NC NC VCC EQUATIONS /40= /BLE*/IOWC*/A7*A6*/A5*/A4*/A3*/A2*/A1 /41= /BHE*/IOWC*/A7*A6*/A5*/A4*/A3*/A2*/A1

38 When selecting 16-bit wide I/O port, the /BLE (A0) and /BHE pins have no function because both I/O banks are selected together Figure illustrates a 16-bit input device connected to function at 8-bit I/O addresses 64H and 65H The PAL16L8 decoder does not have a connection for address bit /BLE (A0) and /BHE because these signals do not apply to 16-bit wide I/O devices

39 A 16-bit I/O port decoded at I/O addresses 64H and 65H o 74LS244 Port 65H o G 2G U2 1Y1 1Y2 1Y3 1Y4 2Y1 2Y3 2Y2 2Y4 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 o 74LS244 Port 64H o G 2G U3 1Y1 1Y2 1Y3 1Y4 2Y1 2Y3 2Y2 2Y4 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 O1 O8 I1 I2 A3 A7 A6 /IORC A1 A2 A4 A5 I3 I5 I6 I o o o o o o o o O7 O6 O5 O4 O3 O2 16L8 I4 I8 I10 I U1 D7-D0 D15-D8

40 AUTHOR Barry B. Brey COMPANY BreyCo DATE 7/5/99 CHIP DECODER8 PAL16L8 Pins IORC A1 A2 A3 A4 A5 A6 A7 NC GND Pins NC NC NC NC NC NC NC NC 06X VCC EQUATIONS /6X= /IORC*/A7*A6*A5*/A4*/A3*A2*/A1

41 32-bit Wide I/O ports Figure illustrates a 32-bit input port for the 80386DX or microprocessor The I/O ports decoded by this interface are the 8-bit ports 70H-73H Only 8-bit I/O port address is decoded

42 The Programmable Peripheral Interface The 82C55 has 24 pins for I/O that are programmable in groups of 12 pins Operate in three distinct modes Can interface any TTL-compatible I/O device to the microprocessor Be used for interface to the keyboard and the parallel printer port Provide at least 2.5mA of sink (logic 0) current at each output, with a maximum of 4.0 ma

43 Basic Description of the 82C55 The 82C55 has three I/O ports (labeled A, B and C) programmed as two groups Group A connections consists of port A (PA7-PA0) and the upper half of port C (PC7-PC4), and Group B connections consists of port B (PB7-PB0) and the lower half of port C (PC3-PC0) The 82C55 is selected by its /CS pin for programming and for reading or writing to a port Register selection is accomplished through the A1 and A0 input pins that select an internal register for programming or I/O operation

44 82C D0 D1 D2 D3 D4 D5 D6 D7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA Vcc= pin 26 Gnd= pin /RD /WR A0 A1 RESET /CS PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC The pin-out of the 82C55 peripheral interface adapter

45 I/O port assignments for the 82C55 A1 A Function Port A Port B Port C Command Register

46 Figure shows an 82C55 connected to the 80386SX so that it functions at 8-bit I/O port addresses C0H (port A), C2H (port B), C4H (port C), and C6H (command register) The RESET input to the 82C55 initializes the device whenever the microprocessor is reset A RESET input to the 82C55 causes all ports to be set up as simple input ports using mode 0 operation

47 The 82C55 interfaced to the low bank of the 80386SX microprocessor PA D0 82C55 D1 D2 D3 D4 D5 D6 D7 PA7 PC6 PC7 PB6 PB7 PA1 PA2 PA4 PA3 PA5 PA6 PB0 PB1 PB3 PB2 PB4 PB5 PC0 PC1 PC3 PC2 PC4 PC5 /RD /WR A1 A0 RESET /CS Y0 o 74LS138 A B C o o o o o o o o Y1 Y2 1 Y4 Y5 Y6 Y7 /G2A /G2B G1 o U1 D7-D0 /IORC /IOWC A1 A2 RESET A7 A3 A4 A6 A5 A U2 Port A Port B Port C

48 Programming the 82C55 The 82C55 is programmed through the two internal command registers The bit 7 selects either command byte A or command byte B Group B pins (port B and the lower part of ort C) as either input or output pins Group B operates in either mode 0 or mode 1 mode 0 is the basic input/output mode that allows the pins of group B to be programmed as simple input and latched output connections Mode 1 operation is the strobed operation for group B connections, where data are transferred through port B and handshaking signals are provided by port C

49 Group A pins (port A and the upper part of port C) are programmed as either input or output pins Group A can operate in mode 0, 1, and 2 Mode 2 operation is a bi-directional mode of operation for port A If a 0 is placed in bit position 7 of the command byte, command byte B is selected This command allows any bit of port C to be set (1) or reset (0), if the 82C55 is operated in either mode 1 or 2

50 Command byte A Group B Port C (PC3-PC0) 1= input 0= output Port B 1= input 0= output Mode 0= mode 0 1= mode 1 Port C (PC7-PC4) 1= input 0= output Port A 1= input 0= output Mode 00= mode 0 01= mode 1 1X= mode 2 Group A Programming port A, B, and C of the command byte of the command register in the 82C55

51 X X X Command byte B Bit set/reset 1= set 0= reset Select a bit Set or reset a bit of port C indicated in the selected bit field

52 Mode 0 Operation Mode 0 operation causes the 82C55 to function either as a buffered input device or as a latched output device Figure shows the 82C55 connected to a set of eight 7-segment LED displays In the circuit, both ports A and B are programmed functioning at mode 0, as simple latched output ports Port A provides the segment data inputs to the display Port B provides a means of selecting one display position at a time for multiplexing the displays The 82C55 is interfaced to an 8088 microprocessor through a PAL16L8 so that it functions at I/O port numbers 0700H-0703H

53 AUTHOR Barry B. Brey COMPANY BreyCo DATE 7/6/99 CHIP DECODER8 PAL16L8 Pins A2 A3 A4 A5 A6 A7 A8 A9 A10 GND Pins A11 CS IOM A12 A13 A14 A15 NC NC VCC EQUATIONS /CS= /A15*/A14*/A13*/A12*/A11*A10*A9*A8*/A6*/A5*/A4*/A3/*/A2*/IOM

54 ;programming the 82C55 ; 0000 B0 80 MOV AL, B 0002 BA 0703 MOV DX, 703H ;address command 0005 EE OUT DX, AL ;program 82C55

55 ;Procedure that multiplexes the 8-digit LED display ;This procedure must be called by a program that ;display 7-segment coded data from memory 0006 DISP PROC NEAR USES AX BX DX SI 000A 9C PUSHF ;save flag register ;setup registers for display 0000B BB E B4 7F 0010 BE 00FF R 0013 BA 0701 MOV BX, 8 MOV AH, 7FH MOV SI, OFFSET MEM+7 MOV DX, 701H ;Load count ;load selection pattern ;address data ;address Port B ;display 8 digits A C EE A 001A 8A C EE 001D E8 029A R 0020 D0 CC B B F0 DISP1: MOV AL, AH OUT DX, AL DEC DX MOV AL, [SI] OUT DX, AL CALL DELAY ROR AH, 1 INC DX DEC SI DEC BX JNZ DISP1 ;select a digit ;address Port A ;get 7-segment data ;wait one millisecond ;address next digit ;address Port B ;address next memory data ;adjust count ;repeat 8 times E POPF RET ;restore registers 002C DISP ENDP

56 An LCD Display Interfaced to the 82C55 Figure shows the connection of the Optrex DMC LCD display to an 82C55 The LCD accepts ASCII code as input data, and commands that control its application The data connection, which are attached to the 82C55 port A, are used to output display data and read information from the display The VEE adjusts the contrast The RS (register selection) input selects data (RS= 1) or instruction (RS= 0) The E (enable) input must be a logic 1 for the LCD read or write information The R/W pin selects a read or a write operation

57 Initialize the LCD Test the state of the LCD Write the ASCII data to the LCD Clear the LCD and home the cursor look at Example 11-10, Example 11-11, Example 11-12, Example 11-13, together with Table 11-3

58 A Stepper Motor Interfaced to the 82C55 A stepper is a digital motor because it is moved in discrete steps A circuit that can drive stepper motor is illustrated in Figure with the four phases The circuit uses the 82C55 to provide it with the drive signals that are used to rotate the armature of the motor in either right-hand or left-hand direction Assume that the port A of the 82C55 is programmed in mode 0 as an output device CX holds the number of steps and direction of the rotation

59 最高响应频率 相 ( 位置 ): 33H (AB)-66H (BC)-CCH (CD)-99H (DA)- 33H (AB) 拍 : 四相四拍, 四相八拍 步距角

60 A stepper motor interfaced to the 82C55 PA D0 U1 D1 D2 D3 D4 D5 D6 D7 PA7 PA1 PA2 PA4 PA3 PA5 PA6 /RD /WR A1 A0 RESET /CS D0 D1 D4 D3 D2 D5 D6 D7 /IOWC /IORC RESET A0 A1 82C55 10K*4 +12V A B C D

61 The current position is stored in memory location POS, which must be initialized with 33H, 66H, 0CCH, or 99H If CX> 8000H, the motor spins in the right-hand direction; if CX< 8000H, it spins in the left-hand direction The leftmost bit of CX is removed and the remaining 15 bits contains the number of steps The ROR (step right) or ROL (step left) instruction is used to rotate the binary bit pattern for the next step Stepper motors can also be operated in the half-step mode, which allows eight steps per sequence

62 = 0040 PORT EQU 40H ;assign Port A ;a procedure to control stepper motor ; 0000 STEP PROC NEAR 0000 A R F F C MOV AL, POS CMP CX, 8000H JA RH CMP CX, 0 JE STEP_OUT ;get posion ;no steps 000E STEP1: 000E D0 C0 ROL AL, 1 ;step left 0010 E5 40 OUT PORT, AL 0012 E E2 F EB 09 CALL DELAY LOOP STEP1 JMP STEP_OUT ;wait 1ms ;repeat until CX= RH: E1 7FFF AND CX, 7FFFH ;clear bit D RH1: 001D D0 C8 001F E E E2 F A C3 ROR AL, 1 OUT PORT, AL CALL DELAY LOOP RH1 STEP_OUT: MOV POS, AL RET ;step right ;wait 1ms ;save position 0029 STEP ENDP

63 D C B A AB DA DC CB A AB D C B A B BC DA D CD C Full-step and half-step sequences of stepper motors

64 Key Matrix Interface Figure illustrates a small 4*4 key-matrix that contains 16 switches interfaced to ports A and B of the 82C55 The keys are organized into 4 rows (ROW0-ROW3) and 4 column (COL0-COL3) Each row is connected to 5.0V through a 10K pull-up resistor to ensure that the row is pulled high when no push-button is closed The 82C55 is decoded (PAL program is not shown) at I/O ports 50H-53H for an 8088 microprocessor Port A is programmed as an input port to read the rows, and port B is programmed as an output port to select a column

65 For example, if 1110 is output to port B pins PB3-PB0, column 0 has a logic 0, so the four keys in column 0 are selected Notice, with a logic 0 on PB0, the only switches that can place a logic 0 onto port A are switches 0-3

66 A 4*4 keyboard matrix connected to an 8088 microprocessor through the 82C55 PA D0 U1 D1 D2 D3 D4 D5 D6 D7 PA7 PB6 PB7 PA1 PA2 PA4 PA3 PA5 PA6 PB0 PB1 PB3 PB2 PB4 PB5 /RD /WR A1 A0 RESET /CS D0 D1 D4 D3 D2 D5 D6 D7 /WR /RD RESET A0 A1 O1 O8 I1 I2 A5 A9 A8 A2 A3 A4 A6 A7 I3 I5 I6 I o o o o o o o o O7 O6 O5 O4 O3 O2 16L8 I4 I8 I10 I U2 A10 A11 82C55 IO/M A12 A13 A14 A15 o VCC

67 D0 D1 D2 D3 D4 D5 D6 D U1 D0 D1 D2 D3 D4 D5 D6 D7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA Row0 Row1 Row2 Row A C D E VCC o /RD /WR A0 A1 RESET /RD /WR A0 A1 RESET /CS 3 7 B F 10K * 4 82C55 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB Col0 Col1 Col2 Col3 A 4*4 keyboard matrix connected to an 8088 microprocessor through the 82C55

68 A flowchart of the software required to read a key from the keyboard matrix and de-bounce the key is illustrated in Figure Keys must be de-bounced, which is normally accomplished with a short time delay of from ms The flowchart contains several sections: waiting for the release of a key, waiting for a keystroke, and calculating the position of the key The software uses a procedure called SCAN to scan the keys and another called DELAY to wait for 10ms for de-bouncing The main keyboard procedure is called KEY It is needed to initialize the 82C55 so that port A is an input port and port B is an output port

69 Mode 1 Strobed Input Mode 1 operation causes port A and port B to function as latching input devices, allowing external data to be stored into the port until the microprocessor is ready to receive it Port C is also used in mode 1 operation for control or handshaking signals that help operate port A and port B The strobed input port captures data from the port pins when /STB is activated The /STB signal causes data to be captured in the port and activates the IBF (input buffer full) and INTR (interrupt request) signals

70 Once the microprocessor, through software (IBF) or hardware (INTR), notices that data are strobed into the port, it executes an IN instruction to read the port (/RD) The act of reading the port restores both IBF and INTR to their inactive states until the next datum is strobed into the port

71 Signal Definitions for Mode 1 Strobed Input /STB: the strobe input loads data into the port latch, holding the information until it is input to the microprocessor via the IN instruction IBF: input buffer full is an output indicating that the input latch contains information INTR : interrupt request is an output that requests an interrupt. The INTR pin becomes a logic 1 when the /STB input returns to a logic 1, and is cleared when the data are input from the port by the microprocessor INTE: the interrupt enable signal is neither an input nor an output. It is an internal bit programmed via the port PC4 (port A) or PC2 (port B) bit position PC7, PC6: the port C pins 7 and 6 are general-purpose I/O pins that are available for any purpose

72 Mode 1 Port A Mode 1 Port B Port A Port B INTE A PC4 /STB INTE B PC2 /STB PC5 IBF PC1 IBF PC3 INTR 6 PC0 INTR PC6, PC7 I/O The internal structure of strobed input operation (mode 1) of the 82C55

73 /STB IBF Buffer full INTR (Interrupt requested) /RD Port Data strobed into port Data read by microprocessor The timing diagram of strobed input operation (mode 1) of the 82C55

74 Strobed Input Example A good example of a strobed input device is a keyboard The keyboard encoder de-bounces the key-switches, and provides a strobe signal whenever a key is pressed and the data output contain the ASCII-coded key code Each time that a key is typed on the keyboard, /DAV (data available) is activated for 1.0 us, causing data to be strobed into port A because /DAV is connected to the /STB input of port A Each time a key is typed, it is stored into port A of the 82C55 The /STB input also activates the IBF signal, indicating that data are in port A

75 Keyboard PA0 D0 ASCII PA7 D7 PC4 /DAV 82C55 Using the 82C55 for strobed input operation of a keyboard

76 ;a procedure that reads the keyboard encoder ;and returns the ASCII character in AL. ; = 0020 = 0022 = 0020 BIT5 EQU 20H PORTC EQU 22H PORTA EQU 20H READ PROC NEAR 0000 E A FA 0006 E C3 IN AL, PORTC TEST AL, BIT5 JZ READ IN AL, PORTA RET ;read Port C ;test IBF ;if IBF= 1 ;read data 0009 READ ENDP

77 Mode 1 Strobed Output When data are written to port A or port B as a strobed output device under mode 1, the /OBF (output buffer full) signal becomes a logic 0 to indicate that data are present in the port latch The /OBF signal indicates that data are available to an external I/O device that removes the data by strobing the /ACK (acknowledge) input to the port The /ACK signal returns the /OBF signal to a logic 1, indicating that the buffer is not full

78 Signal Definitions for Mode 1 Strobed Output /OBF: output buffer full is an output that goes low whenever data are output (OUT) to the port A or port B latch. The signal is set to a logic 1 whenever the /ACK pulse returns from the external device /ACK:the acknowledge signal causes the /OBF pin to return to a logic 1 level. The /ACK is a response from an external device, indicating that it has received the data from the 82C55 INTR : interrupt request is an output signal that often interrupt the microprocessor when external device receives the data via the /ACK signal. The pin is qualified by the internal INTE (interrupt enable ) bit

79 INTE: interrupt enable is neither an input nor an output. It is an internal bit programmed to enable or disable the INTR pin via the port PC6 (port A) or PC2 (port B) bit position PC5, PC4: the port C pins 5 and 4 are general-purpose I/O pins that are available for any purpose

80 Mode 1 Port A Mode 1 Port B Port A Port B INTE A PC6 /ACK INTE B PC2 /ACK PC7 /OBF PC1 /OBF PC3 INTR 6 PC0 INTR PC4, PC5 I/O The internal structure of strobed output operation (mode 1) of the 82C55

81 /WR /OBF Buffer full INTR /ACK (Interrupt requested) Port Data sent to port Data removed from port The timing diagram of strobed output (mode 1) of the 82C55

82 Strobed Output Example Illustrated as Figure 11-29, the printer interface shows us how to achieve strobed output synchronization between the printer and the 82C55 Port B is connected to a parallel printer, with eight data inputs for receiving ASCII-coded data A /DS (data strobe) input is to strobe data into the printer An /ACK output is connected to the /ACK input of the 82C55 to acknowledge the receipt of the data PC4 is used with software that generates the /DS signal

83 82C55 Printer PB0 D0 PB7 PC2 PC4 /ACK ASCII D7 /ACK /DS /OBF PC1 The 82C55 connected to a parallel printer interface that illustrates the strobed output mode of operation for the 82C55

84 Example lists the software that sends the ASCIIcoded character in AH to the printer The procedure first tests /OBF to decide whether the printer has removed the data from port B. If not, the procedure waits for the /ACK signal to return from the printer If /OBF= 1, then the procedure sends the contents of AH to the printer through port B and also sends the /DS signal

85 ;A procedure that transfers the ASCII character ;from AH to the printer via port B ; = 0002 = 0062 = 0061 = 0063 BIT1 EQU 2 PORTC EQU 62H PORTB EQU 61H CMD EQU 63H 0000 PRINT PROC NEAR ;check printer ready 0000 E A FA IN AL, PORTC TEST AL, BIT1 JZ PRINT ;get OBF ;test OBF ;if OBF= 0 ;send character to printer A C4 MOV AL, AH ;get data 0008 E6 61 OUT PORTB, AL ;print data ;send data strobe to printer 000A B C E E B E C3 MOV AL, 8 OUT CMD, AL MOV AL, 9 OUT CMD, AL RET ;clear DS ;set DS 0013 PRINT ENDP

86 Mode 2 Bi-directional Operation In mode 2, which is allowed only with group A, port A becomes bi-directional, allowing data to be transmitted and received over the same eight wires

87 1 2 3 PC3 INTR 3 Port A INTE 1 PC7 PC6 /OBF /ACK 1 2 INTE 2 PC4 /STB PC5 IBF PC2,PC1 PC0 I/O The internal structure of mode 2 operation of the 82C55

88 Signal Definitions for Bi-directional Mode 2 INTR : interrupt request is an output used to interrupt the microprocessor for both input and output conditions /OBF: output buffer full is an output indicating that the output buffer contains data for the bi-directional bus /ACK: acknowledge is an input that enables the threestate buffers so that data can appear on port A. If /ACK is a logic 1, the output buffers of port A are at their high-impedance state

89 /STB: the strobe input loads the port A input latch with external data from the bi-directional port A bus IBF: input buffer full is an output used to signal that the input buffer contains data for the external bidirectional bus INTE: the interrupt enable are internal bits (INTE1 and INTE2) that enable the INTR pin. The state of the INTR pin is controlled through port C bits PC6 (INTE1) and PC4 (INTE2) PC2, PC1, and PC0: these pins are general-purpose I/O pins in mode 2 controlled by the bit set and reset command

90 /WR /OBF INTR /ACK /STB IBF Port A /RD 输入数据 输出数据 The timing diagram of mode 2 operation of the 82C55

91 在实际传输过程中, 输入和输出的顺序以及各自操作的次数是任意的, 只要 /WR 在 /ACK 之前发出,/STB 在 /RD 之前发出就可以了 在输出时,CPU 发出写脉冲 /WR, 向 A 口写入数据 /WR 信号使 INTR 变为低电平, 同时使 /OBF 有效 外设接到 /OBF 信号后发出 /ACK 信号, 从 A 口读出数据 /ACK 信号使 /OBF 无效, 并使 INTR 变为高电平, 产生中断请求, 准备输出下一个数据 输入时, 外设向 82C55 送来数据, 同时发 /STB 信号给 82C55, 该信号将数据锁存到 82C55 的 A 口, 从而使 IBF 有效 /STB 信号结束使 INTR 有效, 向 CPU 请求中断 CPU 响应中断后, 发出读信号 /RD, 从 A 口中将数据读走 /RD 信号会使 INTR 和 IBF 信号无效, 从而开始下一个数据的读入过程

92 The Bi-directional Bus The bi-directional bus is used by referencing port A with the IN and OUT instructions To transmit data through the bi-directional bus, the program first tests the /OBF signal to determine whether the output buffer is empty. If it is, then data are sent to the output buffer via the OUT instruction. The external circuitry also monitors the /OBF signal to decide whether the microprocessor has sent data to the bus. As soon as the output circuitry sees a logic 0 on /OBF, it sends back the /ACK signal to remove it from the output buffer. The /ACK signal sets the /OBF bit and enables the three-state output buffers so that data may be read

93 ;a procedure that transmits AH through ;bi-directional port A ; = 0080 = 0062 = 0060 BIT7 EQU 80H PORTC EQU 62H PORTA EQU 60H TRANS PROC NEAR 0000 E A8 80 IN AL, PROTC TEST AL, BIT7 ;get OBF ;test OBF FA JZ TRANS ;if OBF= A C E A C3 MOV AL, AH OUT PORTA, AL RET ;get data ;send data 000B TRANS ENDP

94 To receive data through the bi-directional port A bus, the IBF bit is tested with software to decide whether data have been strobed into the port. If IBF= 1, then data are input using the IN struction. The external interface sends data into the port by using the /STB signal. When /STB is activated, the IBF signal becomes a logic 1, and the data at port A are held inside the port in a latch. When the IN instruction executes, the IBF bit is cleared and the data in the port are moved into AL

95 ;a procedure that reads data from the ;bi-directional port A and returns it in AL ; = 0020 = 0062 = 0060 BIT5 EQU 20H PORTC EQU 62H PORTA EQU 60H READ PROC NEAR 0000 E A8 20 IN AL, PROTC TEST AL, BIT7 ;get IBF ;test IBF FA JZ READ ;if IBF= E C3 IN AL, PORTA RET ;get data 0009 READ ENDP

96 The INTR (interrupt request) pin can be activated from both directions of data flow through the bus. If INTR is enabled by both INTE bits, then the output and input buffers both cause interrupt requests. This occurs when data are strobed into the buffer using /STB or when data are written using OUT

97 The 8279 Programmable Keyboard/display Interface A programmable keyboard and display interfacing component that scans and enables up to a 64-key keyboard and controls up to a 16-digit numerical display The keyboard interface has a build-in first-in, first-out (FIFO) buffer that allows it to store up to eight keystrokes The display section controls up to 16 numeric displays from an internal 16*8 RAM that stores the coded display information

98 The pin-out of the 8279 programmable keyboard/display interface RL2 DB0 VCC RL1 Pin Configuration RL3 CLK IRQ RL4 RL5 RL6 RL7 RESET SL3 SL2 CNTL/STB RL0 SHIFT /WR /RD SL1 SL0 OUTB0 OUTB1 OUTB Vss DB1 DB2 DB3 DB4 DB5 DB7 DB OUTA1 OUTA2 OUTB3 OUTA0 OUTA3 /BD /CS A0

99 Pin Names Name I/O Function DB0-DB7 CLK RESET /CS I/O I I I /RD I /WR I A0 IRQ SL0-SL3 RL0-RL7 SHIFT CNTL/STB OUTA0-OUTA3 OUTB0-OUTB3 /BD I O O I I I O O O Data bus (bi-directional) Clock input Reset input Chip select Read input Write input Buffer address Interrupt Request output Scan lines output Return lines input Shift input Control /strobe input Display (A) outputs Display (B) outputs Blank display output The logic symbol of the 8279 programmable keyboard/display interface

100 Pin definitions for the 8279 A0: the A0 address input selects data or control for reads and writes between the microprocessor and the A logic 0 selects data and a logic 1 selects control or status register /BD: Blank is an output used to blank the displays CLK: Clock is an input that generates the internal timing for the The maximum allowable frequency on the CLK pin is 2MHz CN/ST: Control/strobe is an input normally connected to the Control key on a keyboard /CS: Chip select is an input that enables the 8279 for programming, reading the keyboard and status information, and writing control and display data

101 DB7-DB0: the data bus consists of bi-directional pins that are connected to the data bus on the microprocessor IRQ: interrupt request is an output that becomes a logic 1 whenever a key is pressed on the keyboard. This signal indicates that keyboard data are available for the microprocessor OUTA3-OUTA0: outputs that send data to the displays (most-significant) OUTB3-OUTB0: outputs that send data to the displays (least-significant) /RD: the read input is directly connected to the /IORC or /RD signal from the system. The /RD input causes, when /CS is a logic 0, a read from the data register or status register

102 RESET: the reset input connects to the system RESET signal RL7-RL0: Return lines are inputs used to sense any key depression in the keyboard matrix SHIFT: the shift input normally connects to the Shift key on a keyboard SL3-SL0: the scan line outputs that scan both the keyboard and the displays /WR: write is an input that connects to the write strobe signal that is developed with external logic. The write causes data to be written to either the data registers or control registers within the 8279 Vcc: a power supply pin connected to the system +5.0V Vss: a ground pin connected to the system ground

103 Interfacing the 8279 to the Microprocessor In Figure 11-33, the 8279 is connected to the 8088 microprocessor The 8279 is decoded to function at 8-bit I/O address 10H and 11H, where port 10H is the data port and the port 11H is the control port The circuit uses a PAL16L8 to decode the I/O address for the 8279 Address bus bit A0 selects either the data or control port The /CS signal selects the 8279 and also provides a signal called /WAIT2 that is used to cause two wait states so that this device can function with an 8 MHz 8088

104 D0 D1 D2 D3 D4 D5 D6 D U2 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 RL0 RL1 RL2 RL3 RL4 RL5 RL6 RL /RD /WR /WAIT2 3.0MHz RESET A0 A1 A2 A3 A4 A5 A6 A7 IO/M U1 1 2 I1 3 I2 4 I3 5 I4 6 I5 7 I6 8 I7 9 I8 11 I9 I10 16L8 19 O1 o 18 O2 o 17 O3 o 16 O4 o 15 O5 o 14 O6 o 13 O7 o 12 O8 o /RD /WR /CS CLK RESET A0 IRQ SHIFT 37 CN/ST 23 BD o 32 SL0 33 SL1 34 SL2 SL3 35 OA0 27 OA1 26 OA2 25 OA3 24 OB0 31 OB1 30 OB2 29 OB3 28 The 8279 interfaced to the 8088 microprocessor to function at 8-bit I/O port 10H and 11H

105 TITLE Address Decoder PATTERN Test 14 REVISION A AUTHOR Barry B. Brey COMPANY BreyCo DATE 7/10/99 CHIP DECODER PAL16L8 Pins A1 A2 A3 A4 A5 A6 A7 NC IOM GND Pins NC NC NC NC NC NC NC NC CS VCC EQUATIONS /CS=/A7*/A6*/A5*A4*/A3*/A2*/A1*IOM

106 Keyboard Interface A 64-key keyboard (with no numerical displays) is connected through the 8279 to the 8088 microprocessor The I/O port number decoded is the same as that decoded for Figure The 74LS138 decoder generates eight active low column strobe signals for the keyboard The selection pins SL2-SL0 sequentially scan each column of the keyboard, and the internal circuitry of the 8279 scans the RL pins, searching for a key switch closure

107 64-key matrix U2 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 RL0 RL1 RL2 RL3 RL4 RL5 RL6 RL /RD /WR /CS CLK RESET A0 IRQ 36 SHIFT 37 CN/ST 23 BD o 32 SL0 33 SL1 34 SL2 SL3 35 OA0 27 OA1 26 OA2 25 OA3 24 OB0 31 OB1 30 OB2 29 OB o4o3o2o1o0o9o7o Y Y Y Y Y Y Y Y G2A A B C G1 G2B o o U3 74LS138 R1 10K VCC o 8279 A 64-key keyboard interfaced t othe 8088 microprocessor through the 8279

108 Programming the Keyboard Interface Before any keystroke is detected, the 8279 must be programmed The 8279 has eight control words The first three bits of the number sent to the control port (11H) select one of the eight different control words Table 11-4 list all eight control words and briefly describes them

109 Table 11-4 The 8279 control word summary D7 D6 D5 Function Purpose Mode set Select the number of display position, left or right entry, and type of keyboard scan Clock Programs the internal clock and sets the scan and de-bounce times Read FIFO Selects the type of FIFO read and the address of the read Read display Selects the type of display read and the address of the read Write display Selects the type of display write and the address of the write Display write inhibit Allows half-bytes to be blanked Clear End interrupt Clears the display or FIFO Clears the IRQ signal to the microprocessor

110 000DDMMM: mode set is a command with an opcode of 000 and two fields programmed to select the mode of operation for the PPPPP: the clock command word programs the internal clock divider. To achieve the desired operating frequency of approximately 100KHz, an input clock of 1MHz thus requires a prescaler of for PPPPP, and an input clock of 3MHz thus requires a prescaler of for PPPPP 010Z0AAA: the read FIFO control word selects the address of a keystroke from the internal FIFO buffer. Bits positions AAA select the desired FIFO location from 000 to CCFA: the clear control word clears the display, the FIFO, or both the display and FIFO

111 100ZAAAA: 写显示控制字, 选择某一个显示的写地址 AAAA 寻址单元,Z 选择自动加 1

112 Once the 8279 is initialized, a procedure is required to read data from the keyboard We determine whether a character is typed in the keyboard by looking at the FIFO status register Whenever the control port is addressed by the IN instruction, the contents of the FIFO status word is copied into the AL register

113 D S/E O U F N N N Bits that indicate the number of characters in the FIFO Indicates the FIFO is full Indicates the FIFO has been read while empty Indicates the FIFO is full and has been overrun Indicates multiple key closures Display unavailable because of clear command The 8279 FIFO satatus register

114 ;Initialization dialog for the keyboard interface ;of Figure ; 0000 B0 3E 0002 E6 11 MOV AL, B OUT 11H, AL ;program clock FA 0006 E4 60 MOV AL, 0 OUT 11H, AL ;program mode 0008 B A B6 11 MOV AL, B OUT 11H, AL ;program FIFO

115 ;A procedure that reads data from the FIFO and ;returns it in AL. ; =0007 MASKS EQU READ PROC NEAR 0000 E A FA 0006 E C3 IN AL, 11H TEST AL, MASKS JZ READ IN AL, 10H RET ;read status ;test NNN ;if NNN= 000 ;read FIFO data 0009 READ ENDP

116 Six-Digit Display Interface Figure illustrates the 8279 connected to the 8088 microprocessor and a 6-digit numeric display This interface uses a PAL16L8 to decode the 8279 at I/O ports 20H (data) and 21H (control/status) The segment data are supplied to the displays through the OUTA and OUTB pins of the 8279 These bits are buffered by a segment driver (ULN 2003A) to drive the segment inputs to the display A 74LS138 decoder enables the anode switches of each display position The SL2-SL0 pin2 supply the decoder with the encoded display position from the 8279

117 ;Initialization dialog for the 6-digit display of ;Figure ; 0000 B0 3E 0002 E6 21 MOV AL, B OUT 21H, AL ;program clock 0004 B E6 21 MOV AL, 0 OUT 21H, AL ;program mode 0008 B0 C1 000A B6 21 MOV AL, B OUT 21H, AL ;clear display

118 ;A procedure that displays AH on the display ;position addressed by AL ; = 0080 MASKS EQU 80H 0000 DISP PROC NEAR C E A C E A C3 PUSH AX OR AL, MASKS OUT 21H, AL MOV AL, AH OUT 20H, AL POP AX RET ;save data ;select digit ;display data ;restore data 000B DISP ENDP

119 8254 Programmable Interval Timer The 8254 consists of three-independent 16-bit programmable counters (timers). Each counter is capable of counting in binary or binary-coded decimal (BCD) The timer appears in the PC to do the following: generate a basic timer interrupt that occurs at approximately 18.2Hz; cause the DRAM memory system to be refreshed; provide a timing source to the internal speaker and other devices

120 D VCC D /WR D /RD D4 D /CS A1 D A0 D CLK 2 D OUT 2 CLK GATE 2 OUT CLK 1 GATE GATE 1 GND OUT 1 The pin-out of the 8254

121 INTERNAL BUS D7-D0 8 DATA BUS BUFFER COUNTER 0 CLK 0 GATE 0 OUT 0 /RD /WR A0 A1 /CS o o READ/ WRITE LOGIC o COUNTER 1 CLK 1 GATE 1 OUT 1 CONTROL WORD REGISTER COUNTER 2 CLK 2 GATE 2 OUT 2 The internal structure of the 8254

122 Each timer contains a CLK input, a gate input, and an output (OUT) connection The CLK input provides the basic operating frequency to the timer The gate pin controls the timer in some modes The OUT pin is where we obtain the output of the timer The signals that connect to the microprocessor are the bus pins (D7-D0), /RD, /WR, /CS, and address inputs A1 and A0 The address inputs are present to select any of the four internal registers used for programming, reading, or writing to a counter

123 Table 11-7 Address selection inputs to the 8254 A A Function Counter 0 Counter 1 Counter Control word

124 Pin Definitions A1, A0: the address inputs select one of four internal registers within the 8254 CLK: the clock input is the timing source for each of the internal counters. This input is often connected to the PCLK signal from the microprocessor system bus controller /CS: chip select enables the 8254 for programming, reading, and writing a counter G: the gate input controls the operation of the counter in some modes of operation OUT: a counter output is the wave-form generated by the timer /WR: write causes data to be written to the 8254 and often connects to the write strobe (/IOWC)

125 /RD: read causes data to be read from the 8254 and often connects to the /IORC signal Vcc: power connects to the +5.0V power supply GND: ground connects to the system ground bus

126 Programming the 8254 Each counter is individually programmed by writing a control word, followed by the initial count The control word allows the programmer to select the counter, mode of operation, and type of operation (read/write) The control word also selects either a binary or BCD counter The M2, M1, and M0 select one of the 6 different modes of operation ( ) for the counter The RW1 and RW0 bits determine how the data are read from or written to the counter The SC1 and SC0 bits select a counter or special read back mode of operation

127 SC1 SC0 RW1 RW0 M2 M1 M0 BCD Select a BCD when a logic 1 Select the mode (mode 0 mode 5) Read/write control 00= counter latch command 01= read/write least-significant byte only 10= read/write most-significant byte only 11= read/write least-significant byte first, followed by the most-significant byte Select counter 00= counter 0 01= counter 1 10= counter 2 11= read-back command The control word for the 8254

128 Mode 0 ( 计数结束中断 ): 方式 0 为软件启动, 不自动重复计数的方式 第一个写信号 /WR 有效时向计数器写入控制字 CW, 之后其输出端 OUT 就变低电平 第二个 /WR 有效时装入计数初值, 然后经过一个 CLK 信号的上升沿和下降沿, 初值进入计数器 当计数减到零 计数结束后,OUT 输出变为高电平 在整个计数过程中,GATE 端应始终保持高电平 OUT 输出信号可以作为中断请求信号使用

129 /WR CW N= 4 CLK GATE= 1 OUT 方式 0 的波形

130 Mode 1 ( 可重触发的单稳态触发器 ): 方式 1 是一种软件启动, 不自动重复的工作方式 当写入控制字后,OUT 端输出高电平 在 CPU 写入计数初值后, 计数器并不开始计数, 而是要等 GATE 出现由低到高的跳变 ( 触发 ) 后, 在下一个 CLK 脉冲的下降沿才开始计数, 此时 OUT 端立刻变为低电平 当计数结束后,OUT 端输出高电平, 这样就可以从 OUT 端得到一个负脉冲, 负脉冲宽度为计数初值 N 乘以 CLK 的周期 T CLK 当计数到 0 时, 不用再写入计数初值, 只要用 GATE 的上升沿重新触发一次计数器, 即可产生一个同样宽度的负脉冲 若在形成单个负脉冲的计数的过程中, 外部的 GATE 上升沿提前到来, 则下一个 CLK 脉冲的上升沿使计数器重新装入计数初值, 并紧接着在 CLK 的下降沿重新开始计数 这时负脉冲宽度将会加宽, 宽度为重新触发前的已有宽度与新一轮计数过程的宽度之和

131 /WR CW N= 2 CLK GATE OUT GATE 提前触发, 则输出脉冲加宽 OUT 方式 1 的波形

132 Mode 2 ( 频率发生器 ): 在这种方式下, 计数器既可以用软件启动, 也可以用硬件启动 若写入控制字和计数初值期间 GATE 一直为高电平, 则在写入计数初值后的下一个 CLK 开始计数 ( 软件启动 ) 若送计数器初值时,GATE 为低电平, 则要等到 GATE 信号由低变高时才启动 ( 硬件启动 ) 一旦计数器启动, 可以自动重复工作 在写入方式 2 控制字后,OUT 端变为高电平, 假设此时 GATE= 1, 则装入计数初值后计数器从下一个 CLK 的下降沿开始计数, 经过 N-1 个 CLK 周期后,OUT 端变为低电平, 再经过一个 CLK 周期, 计数值减到零后, OUT 又恢复为高电平

133 /WR CW N= 3 CLK GATE= 1 OUT 方式 2 的波形

134 Mode 3 ( 方波发生器 ): 与方式 2 类似, 也有两种启动方式, 也能够自动重复计数 只是计数到 N/2 时,OUT 变为低, 再接着计数到 0 时, OUT 又变为高, 并开始新一轮计数 此时 OUT 端输出的波形不是负脉冲, 而是方波 若 N 为奇数, 则输出波形不对称, 其中 (N+1)/2 个时钟周期,OUT 为高电平, 而另外 (N-1)/2 个时钟周期, OUT 为低电平

135 /WR CW N= 4 CLK GATE= 1 OUT 方式 3 的波形

136 Mode 4 ( 软件触发选通 ): 不自动重复计数 写入方式 4 控制字后, 输出 OUT 立即变为高电平 若 GATE= 1, 则装入计数初值后计数立即开始 当计数结束时,OUT 输出一个宽度为 T CLK 的负脉冲

137 /WR CW N= 4 CLK GATE= 1 OUT 方式 4 的波形

138 Mode 5 ( 硬件触发选通 ): 不自动重复计数 写入方式 5 控制字后, 输出 OUT 立即变为高电平, 但此时即使 GATE 原来为高, 也不能启动计数, 而必须出现一个 GATE 上升沿跳变, 计数才会开始 计数结束时,OUT 输出一个宽度为 T CLK 的负脉冲

139 /WR CW N= 4 CLK GATE OUT 方式 5 的波形

140 Each counter has an internal latch that is read with the read counter port operation These latches will normally follow the counter If the contents of the counter are needed, the latch can remember the counter by programming the counter latch control word, which causes the contents of the counter to be held in a latch until it is read Whenever a read from the latch or the counter is programmed, the latch tracks the contents of the counter SC1 SC0 0 0 X x X X Select counter 00= counter 0 01= counter 1 10= counter 2 11= read-back command The 8254 read-back control word

141 Generating a Wave-form with the 8254 Figure shows an 8254 connected to function at I/O ports 0700H, 0702H, 0704H, and 0706H of an 80386SX microprocessor The addresses are decoded by using a PAL16L8 that also generates a chip selection signal for the microprocessor that causes two wait states when the 8254 is accessed

142 CLOCK 8MHz o VCC D0 D1 D2 D3 D4 D5 D6 D U2 D0 D1 D2 D3 D4 D5 D6 D7 9 CLK0 o 11 G0 10 OUT0 15 CLK1 o 14 G1 13 OUT1 10K 100 KHz square wave 200 KHz continuous pulses /RD /WR A1 A /RD /WR A0 A1 18 CLK2 o 16 G2 17 OUT2 /WAIT2 21 /CS 8254 M/IO A0 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A U1 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 16L8 19 O1 o 18 O2 o 17 O3 o 16 O4 o 15 O5 o 14 O6 o 13 O7 o 12 O8 o The 8254 interfaced to an 8 MHz 80386SX so as to generate a 100KHz square wave at OUT0 and a 200KHz continuous pulse at OUT1

143 Example lists the program that generates a 100KHz square-wave at OUT0 and a 200KHz continuous pulse at OUT1 We use mode 3 for counter 0 and mode 2 for counter 1 The count programmed into count 0 is 80 and the count for counter 1 is 40 These counts generate the desired output frequencies with an 8 MHz input clock

144 ;a procedure that programs the 8254 timer to function ;as illustrate in Figure ; TIME PROC NEAR PUSH AX PUSH DX ;save registers 0002 BA B EE 0008 B0 74 MOV DX, 706H MOV AL, B OUT DX, AL MOV AL, B ;address control word ;program counter 0 ;for mode 3 ;program counter 1 000A EE OUT DX, AL ;for mode 2 000B BA 0700 MOV DX, 700H ;address control 0 000E B0 50 MOV AL, 80 ;load count of EE C0 OUT DX, AL XOR AL, AL 0013 EE OUT DX, AL 000B BA 0700 MOV DX, 702H ;address control 1 000E B0 50 MOV AL, 40 ;load count of EE C0 OUT DX, AL XOR AL, AL 0013 EE OUT DX, AL POP DX ;restore registers POP AX 000B TIME ENDP

145 DC Motor Speed and Direction Control One application of the 8254 timer is as a motor speed controller for a DC motor The operation of the motor driver circuitry: if the Q output of the flip-flop 74LS112 is a logic 1, the base of Q2 is pulled up to +12V through the base pull-up resistor, and the base of Q1 is open circuited. This means that Q1 is off and Q2 is on, with ground applied to the positive lead of the motor. The bases of both Q3 and Q4 are pulled low to ground through the inverters. This causes Q3 to conduct or turn on and Q4 to turn off, applying +12V to the negative lead of the motor. The logic 1 at the Q output of the flip-flop therefore connects +12V to the negative lead of the motor and ground to the positive lead. This connection causes the motor to spin in its forward direction

146 If the state of the Q output of the flip-flop becomes a logic 0, then the conditions of the transistors are reversed and +12V is attached to the positive lead of the motor, with ground attached to the negative lead If the output of the flip-flop is alternated between a logic 1 and logic 0, the motor spins in either direction at various speed If the duty cycle of the Q output is 50 percent, the motor will not spin at all and exhibits some holding torque because current flows through it Figure shows some timing diagrams and their effects on the speed and direction of the motor Notice how each counter generates pulses at different positions to vary the duty cycle at the Q output of the flip-flop (PWM)

147 Example lists a procedure that controls the speed and direction of the motor The speed is controlled by the value of AH when the procedure is called Because we have an 8-bit number to represent speed, a 50 percent duty cycle, for a stopped motor, is a count of 128 By changing the value in AH when this procedure is called, we can adjust the motor speed As the value in AH approaches 00H, the motor begins to increase its speed in the reverse direction As the value in AH approaches FFH, the motor increases its speed in the forward direction Look at Figure 11-45, 11-46, and Example 11-27

148 Analog-to-Digit (ADC) and Digit-to-Analog (DAC) Converters ADC and DAC are used to interface the microprocessor to the analog world In order to interface the microprocessor to those outside events, we must have an whole understanding of the interface and control of the ADC and DAC, which convert between analog and digital data

149 The DAC0830 DAC The device is an 8-bit converter that transforms an 8- bit binary number into an analog voltage Other converters are available that convert from 10-, 12-, or 16-bit binary numbers into analog voltages

150 1 o CS 2 o WR1 18 o WR2 VREF DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 RFB IOUT2 IOUT o 19 XFER ILE 10 DGND AGND 3 DAC0830 The pin-out of the DAC0830 DAC

151 Internal Structure of the DAC0830 The device contains two latches In many cases, we disable the first latch and only use the second for entering data into the converter, by connecting a logic 1 to ILE and a logic 0 to /CS

152 O O O O O O O O Latch 1 Latch 2 Converter G Q Q Q Q Q Q Q Q O O O O O O O O G Q Q Q Q Q Q Q Q Vref Iout2 Iout1 Rfb ILE /CS /WR1 2 o 3 o 1 /XFER /WR2 2 o 3 o 1 The internal structure of the DAC0830

153 Connecting the DAC0830 to the Microprocessor Figure illustrates the DAC0830 connected to the microprocessor A PAL16L8 is used to decode the DAC0830 at 8-bit port address 20H Whenever an OUT 20H, AL instruction is executed, the contents of data bus connections AD0-AD7 are passed to the converter within the DAC0830 The 741 operational amplifier, along with the 12V reference voltage, causes the full scale output voltage to equal +12V The output of the operational amplifier feeds a driver that powers a 12V DC motor

154 A DAC0830 interfaced to the 8086 microprocessor at 8-bit I/O location 20H U2 DI0 DI1 DI2 DI4 DI3 DI5 IOUT1 AGND DGND DI AD7 AD0 AD3 AD2 AD1 AD4 AD5 AD6 /WR A2 A0 A1 O1 O8 I1 I2 A5 A3 A4 A6 A7 I3 I5 I6 I o o o o o o o o O7 O6 O5 O4 O3 O2 16L8 I4 I8 I10 I U1 DAC0830 IO/M VCC IOUT RFB 8 o o o o 10K CS WR1 WR2 ILE DI7 17 XFER VREF M Q1

155 A/D 转换器的基本原理及接口方法 基本原理 A/D 转换器的主要参数 1 分辨率 : A/D 转换器可转换的二进制位数 2 转换时间 : 输入启动转换信号到转换结束, 最后得到稳定的数字量输出所需的时间 A/D 转换器的外部特性 1 启动线 : 由系统控制器或通过接口发出的一种控制信号, 此信号一到,A/D 转换器立即开始 2 转换结束线 : 转换完毕由 A/D 转换器发出的一种状态信号, 由它申请中断 DMA 传送和中断查询用 3 模拟信号输入线 : 来自被转换的对象, 有单通道 多通道

156 4 数字量输出线 : 由 ADC 将数字量送给 CPU 连接特性 : 1 启动信号是电平还是脉冲 ; 2 芯片内是否有三态门输出锁存器, 若有可直接与 CPU 数据线相连, 否则要外加锁存器 ; 3 输出数字量的形式, 是二进制还是 BCD 码

157 A/D 转换器的基本原理及接口方法 接口方法 (A/D 转换器与 CPU 的连接 ) 1 A/D 转换器的分辨率与 CPU 的数据总线的位数关系 : 转换结束后存放数据时有 左对齐 和 右对齐 之分, 左对齐就是一个数据的最高位放在最左边, 缺位在右边, 并以 0 补齐 右对齐就是一个数据的最低位放在最右边, 缺位在左边, 并以 0 补齐 2 A/D 转换器的输出锁存器 : 若 A/D 转换器内无数据锁存器, 则 A/D 接口电路中应设有数据锁存器方可与数据总线相连 3 A/D 转换转换器的启动信号 : 有电平启动和脉冲启动之分, 如 AD570 是低电平启动, AD574 ADC0809 为脉冲启动

158 A/D 转换接口的主要操作 1 进行通道选择; 2 发启动信号; 3 取回转换结束信号; 4 读取转换的数据; 5 发 S/H 控制信号 A/D 转换器的数据传送方式 1 查询式传送 ; 2 中断方式传送 ; 3 DMA 方式传送 ; 4 对于超高速 A/D, 采用在 A/D 转换器板上设置 RAM 的方法

159 A/D 转换接口的结构形式 1 与 CPU 直接相连 ; 2 采用三态门锁存器与 CPU 相连 ; 3 利用可编程 I/O 接口与 CPU 相连 ; 4 采用 GAL 器件 ( 通用可编程器件 )

160 几种主要的 A/D 芯片

161 12 位 A/D 转换器芯片 AD574A AGND 20V IN 10V IN BIP OF REF IN REF OUT V DD V EE V CC DGND K 10V 基准电源 5K 10K + D/A 转换器 - 比器 AD565A 较 时钟电路 逐位逼近寄存器 (SAR) 控制逻辑 三态输出锁存缓冲器 /8 CS A 0 R/C EC STS D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 MSB LSB

162 AD574 是美国 Analog Device 公司生产的 12 位逐次逼近式模数转换器, 其主要特点是 :1 有参考电压基准和时钟电路, 不需外部时钟就可以工作 ;2 转换速率高,12 位转换 25s,8 位转换 16s;38 位或 16 位微处理器接口, 自带三态输出缓冲电路, 可直接挂在微处理器的数据总线上而无需接口电路 ;4 温度适应范围大, 在 - 55~+125 C 范围内满足线性要求 主要功能引脚介绍如下 : AC: 模拟地 DC: 数字地 CS: 片选信号, 低电平有效 CE: 片使能, 高电平有效 R/C: 读 / 启动信号, 高电平读数据, 低转换 12/8: 数据格式选择, 高电平 12 位数据同时有效, 低电平时第一次输出高 8 位, 第二次输出低四位有效, 中四位为零 A0: 内部寄存器控制输入端, 在 12/8 接地的情况下, 高电平时高 8 位数据有效, 低电平时低 4 位有效, 中间 4 位为零, 高 4 位为高阻态 ; 在 R/C 为低的情况下, 低电平启动 12 位转换, 高电平启动 8 为转换 STS: 工作状态输出端, 高电平表示正在转换, 低电平表示转换完毕

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