Microsoft PowerPoint - C15_LECTURE_NOTE_10.ppt

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1 INPUT/OUTPUT INTERFACE CIRCUITS AND LSI PERIPHERAL DEVICE INPUT/OUTPUT INTERFACE CIRCUITS AND LSI PERIPHERAL DEVICE. Core and Special-Purpose I/O s.2 Byte-Wide Output Ports Using Isolated I/O.3 Byte-Wide Input Ports Using Isolated I/O.4 Input/Output Handshaking and a Parallel Printer.5 82C55A Programmable Peripheral.6 82C55A Implementation of Parallel Input/Output Ports 6 37 微處理機原理與應用 Lecture -2 INPUT/OUTPUT INTERFACE CIRCUITS AND LSI PERIPHERAL DEVICE.7 Memory-Mapped Input/Output Ports.8 82C54 Programmable Interval.9 82C37A Programmable Direct Memory Access Controller. Serial Communication. Programmable Communication Controller.2 Keyboard and Display Programmable Keyboard/Display Controller 6 37 微處理機原理與應用 Lecture -3. Core and Special-Purpose I/O s Special-Purpose I/O interfaces Keyboard interface Display interface Parallel printer interface Serial communication interface Local area network interface Core I/O interfaces Parallel input/output ports Interval timers Direct memory access control 6 37 微處理機原理與應用 Lecture -4.2 Byte-Wide Output Ports Using Isolated I/O.2 Byte-Wide Output Ports Using Isolated I/O I/O Port Port Port Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 I/O Address XXXXXXXXXXX 2 XXXXXXXXXXX 2 XXXXXXXXXXX 2 XXXXXXXXXXX 2 XXXXXXXXXXX 2 XXXXXXXXXXX 2 XXXXXXXXXXX 2 XXXXXXXXXXX 2 Sixty-four-line parallel output circuit for an 888-based microcomputer I/O Address decoding for ports through 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -6

2 .2 Byte-Wide Output Ports Using Isolated I/O Sixty-four-line parallel output circuit for an 886-based microcomputer.2 Byte-Wide Output Ports Using Isolated I/O To which output port in the 888-based microcomputer are data written when the address put on the bus during an output cycle is 82 6? Express the address in binary form, we get A 5 A = A 5L A L = 2 That is A 5L =, A L = and A 3L A 2L A L = Moreover, whenever an output bus cycle is in progress, IO/M is logic, Therefore the enable inputs of the 74F38 decoder are G 2B = A L = G 2A = IO/M = G = A 5L = 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -8.2 Byte-Wide Output Ports Using Isolated I/O These inputs enable the decoder for operation. At the same time, its select inputs are supplied with the code. This input causes output P to switch to logic : P = The gate at the CLK input of port has as its inputs P and WR. When valid output data are on the bus, WR switches to logic. Since P is also, the CLK input of the 74F374 for port switches to logic. At the end of the WR pulse, the clock switches from to, a positive transition. This causes the data on D through D 7 to be latched and become available at output lines O 8 through O 5 of port..2 Byte-Wide Output Ports Using Isolated I/O Write a series of instructions that will output the byte contents of the memory address DATA to output port in the circuit shown in the previous figure of the 888-base microcomputer. To write a byte to output port, the address is A 5 A 4 A = XXXXXXXXXXX 2 Assuming that the don t-care bits are all made logic, we get A 5 A 4 A = 2 = 8 6 The instruction sequence is MOV DX, 8H MOV AL, [DATA] OUT DX, AL 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -.2 Byte-Wide Output Ports Using Isolated I/O Time-delay loop and blinking an LED at an output port.2 Byte-Wide Output Ports Using Isolated I/O Time-delay loop and blinking and LED at an output port MOV DX, 8H ; Initialize address of port MOV AL, H ; Load data with bit 7 as logic ON_OFF OUT DX, AL ; Output the data to port MOV CX, FFFFH ; Load delay count of FFFFH HERE: LOOP HERE ; Time delay loop XOR AL, 8H ; Complement bit 7 of AL JMP ON_OFF ; Repeat to output the new bit 7 Driving an LED connected to an output port 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -2 2

3 .3 Byte-Wide Input Ports Using Isolated I/O Sixty-four-line parallel input circuit for an 888-based microcomputer.3 Byte-Wide Input Ports Using Isolated I/O What is the I/O address of port 7 in the circuit of the previous figure? Assume all unused address bits are at logic For the I/O address decoder to be enable, address bits A 5 and A must be A 5 = and A = To select port 7, the address applied to the CBA inputs of the decoder must be A 3L A 2L A L = Using s for the unused bits gives the address A 5 A L A L = 2 = 8E 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -4.3 Byte-Wide Input Ports Using Isolated I/O For the circuit in the previous figure, write an instruction sequence that inputs the byte contents of input port 7 to the memory location DATA_7 In the previous example we found that the address of port 7 is 8E 6. This address is loaded into the DX register by MOV DX, 8EH Now the contents of this port are input to the AL register by IN AL, DX Finally, the byte of data is copied to memory location DATA_7 by MOV DATA_7, AL.3 Byte-Wide Input Ports Using Isolated I/O Polling the setting of a switch Reading the setting of a switch connected to an input port 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -6.3 Byte-Wide Input Ports Using Isolated I/O Polling the setting of a switch MOV DX, 8H POLL_I7: IN AL, DX SHL AL, JC POLL_I7 CONTINUE:.4 Input/Output Handshaking and a Parallel Printer I/O synchronization is achieved by implementing what is known as handshaking as part of the input/output interface. Three general types of signals at the printer interface: Data Control False Status Status Parallel Printer Port Data Control Status Printer True Send data Send control Parallel printer interface 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -8 3

4 .4 Input/Output Handshaking and a Parallel Printer.4 Input/Output Handshaking and a Parallel Printer Pin Assignment Pin Assignment Strobe 4 Auto Foxt 2 Data 5 Error 3 Data 6 Initialize Data 2 Data 3 Data 4 Data 5 Data Slctin Ground Ground Ground Ground Data: Data, Data,, Data7 Control: Strobe Auto Foxt Initialize Slctin Data 7 Ack Busy Paper Empty Select Ground Ground Ground Ground Status: Ack Busy Paper Empty Select Error Parallel printer port in assignments and types of interface signals 6 37 微處理機原理與應用 Lecture -9 I/O interface that employs handshaking 6 37 微處理機原理與應用 Lecture -2.4 Input/Output Handshaking and a Parallel Printer.4 Input/Output Handshaking and a Parallel Printer 6 37 微處理機原理與應用 Lecture -2 Handshake sequence flowchart Handshaking printer interface circuit 6 37 微處理機原理與應用 Lecture Input/Output Handshaking and a Parallel Printer What are the addresses of the ports that provide the data lines, strobe output, and busy input in the circuit shown in the previous figure? Assume that all unused address bits are s. The I/O address that enable port for the data lines, port for the strobe output, and port 2 for the busy input are found as follows: Address of port = 2 = 8 6 Address of port = 2 = 82 6 Address of port 2 = 2 = Input/Output Handshaking and a Parallel Printer Write a program that will implement the sequence for the circuit in the previous figure. Character data are held in memory starting at address PRNT_BUFF, and the number of characters held in the buffer is identified by the count at address CHAR_COUNT. Use the port address from the previous example. First, the character counter and the character points are setup with the instructions MOV CL, CHAR_COUNT ; (CL) = character count MOV SI, PRNT_BUFF ; (SI) = character pointer 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -24 4

5 .4 Input/Output Handshaking and a Parallel Printer.4 Input/Output Handshaking and a Parallel Printer Next, the BUSY input is checked with the instructions POLL_BUSY MOV DX, 84H ; Keep polling till busy = IN AL, DX AND AL, H JNZ POLL_BUSY The character is copied into AL, and then it is output to port : MOV AL, [SI] ; Get the next character MOV DX, 8H OUT DX, AL ; and output it to port Now, a strobe pulse is generated at port with the instructions MOV AL, H ; STB = MOV DX, 82H OUT DX, AL MOV BX, FH ; Delay for STB duration STROBE: DEC BX JNZ STROBE MOV AL, H ; STB = OUT DX, AL 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture Input/Output Handshaking and a Parallel Printer At this point, the value of PRNT_BUFF must be incremented, and the value of CHAR_COUNT must be decremented: INC SI ; Update character counter DEC CL ; and pointer Finally, a check is made to see if the printer buffer is empty. If it is not empty, we need to repeat the prior instruction sequence. To do this, we execute the instruction JNZ POLL_BUSY ; Repeat till all character ; have been transferred DONE: - The program comes to the DONE label after all characters are transferred to the printer.5 82C55A Programmable Peripheral The 82C55A is an LSI peripheral designed to permit easy implementation of parallel I/O in the 888- and 886-microcomputer system. Flexible parallel interface: Single-bit, 4-bit, and byte-wide input and output ports Level sensitive inputs Latched outputs Strobed inputs or outputs Strobed bidirectional input/outputs Timing of the data transfers to the 82C55A is controlled by the read/write control (RD and WR) signals 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture C55A Programmable Peripheral Block diagram and pin layout of the 82C55A 6 37 微處理機原理與應用 Lecture C55A Programmable Peripheral The source or destination register within the 82C55A is selected by a 2-bit register select code (A A ). The chip-select (CS) input must be logic during all read or write operations to the 82C55A. The reset (RESET) is used to initialize the 82C55A. Three byte-wide ports (port A, port B, port C) can be configured for input or output operation. This gives us a total of 24 I/O lines. The 82C55A contains an 8-bit internal control register for software control. A write bus cycle to the 82C55A with register-select code A A =, and an appropriate control word is used to modify the control register 微處理機原理與應用 Lecture -3 5

6 .5 82C55A Programmable Peripheral.5 82C55A Programmable Peripheral What is the addresses of port A, port B, port C of the 82C55A device? To access port A, A A =, A 5 = A 4 =, A 3 = A 2 = = A 2 =, which gives the port A address as 2 = C 6 Similarly, it can be determined that the address of port B equals C 6, that of port C is C2 6, and the address of the control register is C3 6. Addressing an 82C55A using the microcomputer interface signals 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture C55A Programmable Peripheral Control-word bit functions.5 82C55A Programmable Peripheral Mode Simple I/O operation Mode port pin functions 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture C55A Programmable Peripheral What is the mode and I/O configuration for ports A, B, and C of an 82C55A after its control register is loaded with 82 6? Expressing the control register contents in binary form, we get.5 82C55A Programmable Peripheral The next for bits configure the upper part of port C and port A: D 3 = Upper four bits of port C are outputs. D 4 = Port A is an output port. D 6 D 5 = Mode for both port A and the upper four bits of port C D 7 D 6 D 5 D 4 D 3 D 2 D D = 2 Since D 7 is, the modes of operation of the ports are selected by the control word. D = Lower four bits of port C are outputs. D = Port B is an input port. D 2 = Mode for both port B and the lower four bits of port C 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -36 6

7 .5 82C55A Programmable Peripheral Mode Simple I/O operation.5 82C55A Programmable Peripheral Mode Simple I/O operation Mode control words and corresponding input/output configurations 微處理機原理與應用 Lecture -37 Mode control words and corresponding input/output configurations 微處理機原理與應用 Lecture C55A Programmable Peripheral Mode Simple I/O operation.5 82C55A Programmable Peripheral Mode Simple I/O operation Mode control words and corresponding input/output configurations 微處理機原理與應用 Lecture -39 Mode control words and corresponding input/output configurations 微處理機原理與應用 Lecture C55A Programmable Peripheral Mode Strobed I/O In mode, the A and B ports are configured as two independent byte-wide I/O ports, each of which has a 4-bit control/data port associated with it. The control/data ports are formed from the lower and upper nibbles of port C, respectively. In mode, data applied to an input port must be strobed in with a signal produced in external hardware. An output port in mode is provided with handshake signals that indicate when new data are available at its outputs and when an external device has read these values..5 82C55A Programmable Peripheral Mode Strobed I/O Mode port pin functions 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -42 7

8 .5 82C55A Programmable Peripheral Mode Strobed I/O.5 82C55A Programmable Peripheral Mode Strobed I/O Mode, port A output and input configuration 6 37 微處理機原理與應用 Lecture -43 Mode, port A input and output timing diagram 6 37 微處理機原理與應用 Lecture C55A Programmable Peripheral The following figures show how port B can be configured for mode operation. Describe what happens in the left figure when the STB B input is pulsed to logic. Assume that INTE B is already set to..5 82C55A Programmable Peripheral SOLUTION: As STB B is pulsed, the byte of data at PB 7 through PB is latched into the port B register. This causes the IBF B output to switch to. Since INTE B is, INTR B switches to logic 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture C55A Programmable Peripheral Mode 2 Strobed bidirectional I/O.5 82C55A Programmable Peripheral Mode 2 Strobed bidirectional I/O Mode 2 port pin functions 6 37 微處理機原理與應用 Lecture -47 Mode 2 input/output configuration 6 37 微處理機原理與應用 Lecture -48 8

9 .5 82C55A Programmable Peripheral Mode 2 Strobed bidirectional I/O 6 37 微處理機原理與應用 Lecture -49 Mode 2 bit set/reset format.5 82C55A Programmable Peripheral The interrupt-control flag INTE A for output port A in mode is controlled by PC 6. Using the set/reset feature of the 82C55A, what command code must be written to the control register of the 82C55A to set it to enable the control flag? To use the set/reset feature, D 7 must be logic. Moreover, INTE A is to be set; therefore, D must be logic. Finally, to select PC 6, the code at bits D 3 D 2 D must be. The rest of the bits are don t-care states. This gives us the control word D 7 D 6 D 5 D 4 D 3 D 2 D D = XXX 2 Replacing the don t-care states with the logic level, we get D 7 D 6 D 5 D 4 D 3 D 2 D D = 2 = D 微處理機原理與應用 Lecture C55A Programmable Peripheral Mixed modes.5 82C55A Programmable Peripheral Mixed modes Combined mode 2 and mode (input) control word and I/O configuration Combined mode 2 and mode (output) control word and I/O configuration 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture C55A Programmable Peripheral What control word must be written into the control register of the 82C55A such that port A is configured for bidirectional operation and port B is set up with mode outputs? To configure the operating mode of the ports of the 82C55A, D 7 must be. Port A is set up for bidirectional operation by making D 6 logic. In this case, D 5 through D 3 are don t-care states: D 5 D 4 D 3 = XXX 2 Mode is selected for port B by logic in D 2 and output operation by logic in D. D is a don t-care state. This gives the control word D 7 D 6 D 5 D 4 D 3 D 2 D D = XXXX 2 = 2 = C C55A Programmable Peripheral Write the sequence of instructions needed to load the control register of an 82C55A with the control word formed in the previous example. Assume that the control register of the 82C55A resides at address F 6 of the I/O address space? First we must load AL with C4 6. This is the value of the control word that is to be written to the control register at address F 6. The move instruction used to load AL is MOV AL, C4H These data are output to the control register with OUT instruction OUT FH, AL Because the I/O address of the control register is less than FF 6, this instruction uses direct I/O 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -54 9

10 .5 82C55A Programmable Peripheral When the 82C55A is configured in mode or mode 2 operations, most of the pins of port C perform I/O control functions..6 82C55A Implementation of Parallel Input/Output Ports Mode status information for port C 6 37 微處理機原理與應用 Lecture -55 Mode status information for port C 82C55A parallel I/O ports in an 888-based microcomputer 6 37 微處理機原理與應用 Lecture C55A Implementation of Parallel Input/Output Ports What must be the address bus inputs of the circuit in the previous figure if port C of PPI 4 is to be accessed? To enable PPI 4, the 74F38 must be enabled for operation and its O 7 output switched to logic. This requires enable input G 2B = and chip select code CBA =. This in turn requires from the bus that A = to enable 74F38 and A 5 A 4 A 3 = to select PPI 4 Port C of PPI 4 is selected with A A =, which from the bus requires that A 2 A = The rest of the address bits are don t-care states..6 82C55A Implementation of Parallel Input/Output Ports Assume that in the previous figure, PPI 4 is configured so that port A is an output port, both ports B and C are input ports, and all three ports are set up for mode operation. Write a program that will input that data at port B and C, find the difference (port C) (port B), and output this difference to port A. Port A address = 2 = 38 6 Similarly, Port B address = 3A 6,, Port C address = 3C 6 Therefore, IN AL, 3AH ; Read port B MOV BL, AL ; Save data from port B IN AL, 3CH ; Read port C SUB AL, BL ; Subtract B from C OUT 38H, AL ; Write to port A 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture C55A Implementation of Parallel Input/Output Ports.7 Memory-Mapped Input/Output Ports The full 2-bit address is available for addressing I/O. Therefore, memory-mapped I/O devices can reside anywhere in the Mbyte memory address space of the 888. During I/O operations, memory read and write bus cycles are initiated instead of I/O bus cycles. Memory instructions, not input/output instructions, are used to perform data transfer. 82C55A parallel I/O ports in an 886-based microcomputer 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -6

11 .7 Memory-Mapped Input/Output Ports Memory-mapped 82C55A parallel I/O ports in an 888-based microcomputer 6 37 微處理機原理與應用 Lecture -6.7 Memory-Mapped Input/Output Ports Which I/O port in the previous figure is selected for operation when the memory address output on the bus is 42 6? We begin by converting the address to binary form. This gives A 9 A A = 2 In this address, bits A = and A =. Therefore, the 74F38 address decoder is enabled whenever IO/M =. A 5 A 4 A 3 = This input code switches decoder output O to logic and chip selects PPI for operation. The address bits applied to the port select inputs of the PPI are A 2 A =. These inputs cause port B to be accessed. Thus, the address 42 6 selects port B on PPI for memory-map I/O 微處理機原理與應用 Lecture Memory-Mapped Input/Output Ports Write the sequence of instructions needed to initialize the control register of PPI in the circuit of the previous figure so that port A is an output port, ports B and C are input ports, and all three ports are configured for mode operation. The control byte required to provide this configuration is:.7 Memory-Mapped Input/Output Ports From the circuit diagram, the memory address of the control register for PPI is found to be 2 = 46 6 Since PPI is memory mapped, the following move instructions can be used to initialized the control register: MOV AX, ; Create data segment at H MOV DS, AX MOV AL, 8BH ; Load AL with control byte MOV [46H], AL ; Write control byte to PPI control ; register 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture Memory-Mapped Input/Output Ports Assume that PPI in the previous figure is configured as described in the previous example. Write a program that will input the contents of ports B and C, AND them together, and output the results to port A. The addresses of the three I/O ports on PPI are: Port A = 4 6 Port B = 42 6 Port C = 44 6 Now we set up a data segment at 6 and the program is: AND AX, ; Create data segment at H MOV DS, AX MOV BL, [42H] ; Read port B MOV AL, [44H] ; Read port C AND AL, BL ; AND data at port B and C MOV [4H], AL ; Write to port A 6 37 微處理機原理與應用 Lecture Memory-Mapped Input/Output Ports Memory-mapped 82C55A parallel I/O ports in an 886-based microcomputer 6 37 微處理機原理與應用 Lecture -66

12 .8 82C54 Programmable Interval Block diagram of the 82C54 The 82C54 is an LSI peripheral designed to permit easy implementation of timer and counter functions in a microcomputer system. The 82C54C can be memory-mapped into the memory address space or I/O-mapped into the I/O address space. The microcomputer interface of the 82C54 allows the MPU to read from and write into its internal registers. The 3 counters in 82C54 are each 6 bits in length and operate as down counters 微處理機原理與應用 Lecture C54 Programmable Interval Block diagram of the 82C54 Block diagram and pin layout of the 82C54 interval timer 6 37 微處理機原理與應用 Lecture C54 Programmable Interval Block diagram of the 82C C54 Programmable Interval Architecture of the 82C54 Signals Functions D 7 D 8-bit bidirectional data bus A, A Register address inputs used to select the register to be accessed RD, WR Control signals indicating whether 82C54 is to be read from or written into CS Chip-select input to enable the 82C54 s microprocessor interface CLK Pulses applied to the clock input are used to decrement counter GATE Gate must be switched to logic to enable the counter OUT Clock or pulse output of counter 6 37 微處理機原理與應用 Lecture -69 Internal architecture of the 82C54 interval timer 6 37 微處理機原理與應用 Lecture C54 Programmable Interval Architecture of the 82C C54 Programmable Interval An 82C54 receive the control word 2. What configuration is set up for the timer? SC bits = indicating counter 2 is selected. RW bits = sets counter 2 for the read/write sequence identified as the least significant byte only. The mode code M 2 M M is, this selects mode operation for counter 2. The last bit, BCD, is also set to and selects binary counting. Control word format of the 82C54 interval timer 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -72 2

13 .8 82C54 Programmable Interval Architecture of the 82C C54 Programmable Interval Write an instruction sequence to set up the three counters of the 82C54 in the figure that follows: Counter : Binary counter operating in mode, value = 234H Counter : BCD counter operating in mode 2, value = H Counter 2: Binary counter operating in mode 4, value = FFFH First, we need to determine the base address of the 82C54. The base address, which is also the address of counter, is determined with A A set to. In the figure, we find that to select 82C54, CS must be logic. This requires that A 5 A 4 A 7 A 6 A 5 A 2 = 2 Accessing the registers of the 82C54 interval timer 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture C54 Programmable Interval.8 82C54 Programmable Interval Combining this part of the address with the at A A, gives the base address as 2 = 4H Since the base address of the 82C54 is 4H, and to select the mode register requires A A =, its address is 43H. Similarly, the three counters,, and 2 are at addresses 4H, 4H, 42H, respectively. Lets determine the mode words for the three counters. Mode word for counter = 2 = 3 6 Mode word for counter = 2 = 55 6 Mode word for counter 2 = 2 = B 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture C54 Programmable Interval MOV AL, 3H ; Set up counter mode OUT 43H, AL MOV AL, 55H ; Set up counter mode OUT 43H, AL MOV AL, B8H ; Set up counter 2 mode OUT 43H, AL MOV AL, 234H ; Initialize counter with 234H OUT 4H, AL MOV AL, 2H OUT 4H, AL MOV AL, H ; Initialize counter with H OUT 4H, AL MOV AL, H OUT 4H, AL MOV AL, FFFH ; Initialize counter 2 with FFFH OUT 42H, AL MOV AL, FH OUT 42H, AL.8 82C54 Programmable Interval Write an instruction sequence to read the contents of counter 2 on the fly. The count is to be loaded into the AX register. Assume that the 82C54 is located at I/O address 4H. First, we latch that contents of counter 2 and then read this value from the temporary storage register. MOV AL, XXXXB ; Latch counter 2, XXXX must be as per ; the mode and counter type OUT 43H, AL IN AL, 42H ; Read the low byte MOV BL, AL IN AL, 42H ; Read the high byte MOV AH, AL MOV AL, BL ; (AX) = counter 2 value 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -78 3

14 .8 82C54 Programmable Interval Architecture of the 82C54 Read-back mode permits a programmer to capture the current count values and status information of all three counters with a single command. A read back command has bits D 6 and D 7 both set to..8 82C54 Programmable Interval Architecture of the 82C54 Read-back command examples Read-back command format 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture C54 Programmable Interval Architecture of the 82C C54 Programmable Interval Operating modes of 82C54 counters Status byte format 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture C54 Programmable Interval Operating modes of 82C54 counters Effect of the GATE input for each mode.8 82C54 Programmable Interval The counter in the following figure is programmed to operate in mode. Assuming that the decimal value is written into the counter, compute the time delay (T D ) that occurs until the positive transition takes place at the counter output. The counter is configured for BCD counting. Assume the relationship between the GATE and the CLK signal as shown in the figure. Once loaded, counter needs to count down for pulses at the clock input. During this period, the counter is disabled by logic at the GATE input for two clock periods. Therefore, the time delay is calculated as T D = ( n + + d)( T CLK ) = ( + + 2)( /.938) μs = 86.3 μs 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -84 4

15 .8 82C54 Programmable Interval.8 82C54 Programmable Interval Counter of an 82C54 is programmed to operate in mode and is loaded with the decimal value. The gate and clock inputs are as shown in the figure below. How long is the output pulse? Assume that the counter is configured for BCD counting. The GATE input in the figure show that the counter is operated as a nonretriggerable one-shot. Therefore, the pulse width is T = (counter contents)(clock period) = ()( /.938) μs = 8.38 μs 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture C54 Programmable Interval Counter of an 82C54, as shown, is programmed to operate in mode 2 and is loaded with the decimal value 8. Describe the signal produced at OUT. Assume that the counter is configured for BCD counting. In mode 2 the output goes low for one period of the input clock after the counter contents decrement to. Therefore, T 2 = /.938 MHz = 838 ns and T = 8 x T 2 = 5.94 μs.8 82C54 Programmable Interval The 82C54 counter, as shown, is programmed to operate in mode 3 and is loaded with the decimal value 5. Determine the characteristics of the square wave at OUT. Assume that the counter is configured for BCD counting. T CLK = /.938 MHz = 838 ns T = T CLK (N+)/2 = 838 ns x [(5+)/2] = 6.74 μs T 2 = T CLK (N-)/2 = 838 ns x [(5-)/2] = μs T = T + T 2 = 6.74 μs μs = 2.57μs 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture C54 Programmable Interval The 82C54 counter, as shown, is programmed to operate in mode 4. What value must be loaded into the counter to produce a strobe signal μs after the counter is loaded? The strobe pulse occurs after counting down the counter to zero. The number of input clock periods required for a period of μs is given by N = T/T CLK = μs/(/.938 MHz) = 2 = C 6 = 2 Thus, the counter should be loaded with the number n=b 6 to produce a strobe pulse μs after loading..9 82C37A Programmable Direct The 82C37A is an LSI controller IC that is widely used to implement the direct memory (DMA) function in the 888/886 microcomputer. DMA capability permits devices to perform highspeed data transfers between either two sections of memory or between memory and an I/O device. The memory or I/O bus cycles initiated as part of a DMA transfer are not performed by the MPU; instead, they are performed by DMA controllers, such as 82C37A. A single DMA device supports up to four peripheral devices for DMA operation 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -9 5

16 .9 82C37A Programmable Direct Microprocessor interface of the 82C37A.9 82C37A Programmable Direct Microprocessor interface of the 82C37A Block diagram and pin layout of the 82C37A DMA controller 6 37 微處理機原理與應用 Lecture -9 Microprocessor interface of 82C37A to the 微處理機原理與應用 Lecture C37A Programmable Direct DMA interface of the 82C37A Microprocessor interface of 82C37A to the 微處理機原理與應用 Lecture C37A Programmable Direct DMA interface of the 82C37A 82C37A contains four independent channels, channel through 3. When a peripheral device wants to perform DMA, it makes a request for service at 82C37A DREQ input by switching it to login. During DMA bus cycles, the DMA controller, not the MPU, drives the system bus. The 82C37A generates the address and all control signals to perform the memory or I/O data transfer. The 82C37A performs both the memory-to-i/o and I/O-tomemory DMA bus cycles in just four clock periods. The memory-to-memory data transfer takes 8 clock periods 微處理機原理與應用 Lecture C37A Programmable Direct Internal architecture of the 82C37A 6 37 微處理機原理與應用 Lecture C37A Programmable Direct Internal architecture of the 82C37A The timing and control part of the 82C37A generates the timing and control signals needed by the external bus interface. The priority logic circuitry resolves priority for simultaneous DMA requests from peripheral devices based on either fixed priority or rotating priority scheme. The command control circuit decodes the register commands applied to the 82C37A through the microprocessor interface. Each DMA channel has two address register: the base address register and the current address register. Each DMA channel has two word-count register to specify the number of bytes of data to be transferred 微處理機原理與應用 Lecture -96 6

17 .9 82C37A Programmable Direct Internal architecture of the 82C37A 82C37A has 2 different types of internal registers..9 82C37A Programmable Direct Internal architecture of the 82C37A Name Size Number Base Address Registers 6 bits 4 Base Word Count Registers 6 bits 4 Current Address Registers 6 bits 4 Current Word Count Registers 6 bits 4 Temporary Address Register 6 bits Temporary Word Count Register 6 bits Status Register 8 bits Command Register Temporary Register Mode Register 8 bits 8 bits 6 bits 4 Accessing the registers of the 82C37A Mask Register 4 bits Request Register 6 37 微處理機原理與應用 Lecture bits 6 37 微處理機原理與應用 Lecture C37A Programmable Direct Internal architecture of the 82C37A The command register is used to control operating modes that apply to all channels of the DMA controller. Command register format.9 82C37A Programmable Direct If the command register of an 82C37A is loaded with 6, how does the controller operate? Bit = = Memory-to-memory transfers are disabled Bit = = Channel address increment/decrement normally Bit 2 = = 82C37A is enabled Bit 3 = = 82C37A operates with normal timing Bit 4 = = Channels have fixed priority, channel having the highest priority and channel 3 the lowest priority Bit 5 = = Write operation occurs late in the DMA bus cycle Bit 6 = = DREQ is an active high (logic ) signal Bit 7 = = DACK is an active low (logic ) signal 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture C37A Programmable Direct Internal architecture of the 82C37A The mode register is used to configure operation features of the 82C37A. Mode register format.9 82C37A Programmable Direct Specify the mode byte for DMA channel 2 if it is to transfer data from an input peripheral device to a memory buffer starting at address A 6 and ending at AFFF 6. Ensure that the microprocessor is not completely locked off the bus during the DMA cycle. Moreover, at the end of each DMA cycle, the channel is to be reinitialized so that the same buffer is filled when the next DMA operation is initiated. For DMA channel 2, B B = Transfer of data from an I/O device to memory represents a write bus cycle. Therefore, B 3 B 2 = 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -2 7

18 .9 82C37A Programmable Direct Selecting autoinitialization will set up the channel to automatically reset. Making bit 4 equal to enables this feature: B 4 = The address that points to the memory buffer must increment after each data transfer. Therefore B 5 = To ensure that the 888 is not locked off the bus during the complete DMA cycle, we will select the single-transfer mode: B 7 B 6 = Thus, the mode register byte is B 7 B 6 B 5 B 4 B 3 B 2 B B = 2 = C37A Programmable Direct Internal architecture of the 82C37A The request register is used to respond to software-initiated requests for DMA services. Any channel used to software-initiated DMA must be programmed for block-transfer mode of operation 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -4 Request register format.9 82C37A Programmable Direct Internal architecture of the 82C37A The 4-bit mask register is used to mask out (to ignore hardware request) the DREQ input to the DMA channels..9 82C37A Programmable Direct Internal architecture of the 82C37A The status register contains the information about the operating state of the four channels of the 82C37A. Single-channel and four-channel mask-register command format 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -6 Status register.9 82C37A Programmable Direct Write an instruction sequence to issue a master clear to the 82C37A and then enable all its DMA channels. Assume that the device is located at base I/O address DMA < FH. The master clear command is performed by simply writing into the register a relative address D 6. For instance, the instruction OUT DMA+DH, AL To enable the DMA request inputs, all 4 bits of the mask register must be cleared. The clear-mask register command is issued by performing a write to the register at relative address E 6. OUT DMA+EH, AL.9 82C37A Programmable Direct DMA interface for the 888-based microcomputer using the 82C37A 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -8 8

19 . Serial Communication Synchronous and asynchronous data communication. Serial Communication Synchronous and asynchronous data communication Synchronous communications interface and data-transmission format 6 37 微處理機原理與應用 Lecture -9 Asynchronous communications interface and data-transmission format 6 37 微處理機原理與應用 Lecture -. Serial Communication Simplex, half-duplex, and full-duplex communication links. Serial Communication Simplex, half-duplex, and full-duplex communication links Microcomputer RS-232 Transmit line RS-232 Printer Microcomputer Transmit/Receive line CRT RS-232 RS-232 terminal with keyboard Simplex communication link Half-duplex communication link 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -2. Serial Communication Simplex, half-duplex, and full-duplex communication links Microcomputer RS-232 Transmit line Receive line Full-duplex communication link RS-232 CRT terminal with keyboard. Serial Communication Baud rate and the baud-rate generator The rate at which data transfers take place over the receive and transmit lines is known as the baud rate. By baud rate we mean the number of bits of data transferred per second. Baud rate is set by a part of the serial communication interface called the baud-rate generator 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -4 9

20 . Serial Communication The data transfer across an asynchronous serial data communications line is observed and the bit time is measured as.883 ms. What is the baud rate? Baud rate is calculated from the bit time as Baud rate = / t BT = /.833 ms = 2 bps 6 37 微處理機原理與應用 Lecture -5. Serial Communication The RS-232C interface The RS-232C interface is a standard hardware interface for implementing asynchronous serial data communication ports on devices such as printers, CRT terminals, keyboards, and modems. Three signal lines can be used to connect the peripheral to the MPU via RS-232C interface: a receive-data line, a transmit-data line, and signal common. The RS-232C standard defines a 25-pin interface. The RS-232C is specified to operate correctly over a distance of up to feet 微處理機原理與應用 Lecture -6. Serial Communication The RS-232C interface. Serial Communication The RS-232C interface 6 37 微處理機原理與應用 Lecture -7 RS-232 interface pins and functions A DTE-to-DTE serial communication connection 6 37 微處理機原理與應用 Lecture -8. Programmable Communication Controller USART Universal Synchronous and Asynchronous Receiver Transmitter The programmability of the USART provides for a very flexible asynchronous communication interface. Typical USART can be configured through software for communication of data using formats with character length between 5 and 8 bits, with even or odd parity, and with,.5, or 2 stop bits. A USART has the ability to automatically check characters during data reception to detect the occurrence of parity, framing, and overrun errors.. Programmable Communication Controller 825A USART 825A USART includes 4 key sections Bus interface section Transmit section Receive section Modem-control section A UART can not stand alone in a communication operation; its operation must typically be controlled by a microprocessor. Data transfers over the bidirectional data bus (D through D 7 ) are controlled by the signals C/D, RD, WR, CS 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -2 2

21 . Programmable Communication Controller 825A USART. Programmable Communication Controller 825A USART C/D RD WR CS Operation 825A Data Data bus Data bus 825A Data Status Data bus Data bus Control X Data bus 3-state X X X Data bus 3-state Read/Write operations Block diagram and pin layout of the 825A 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -22. Programmable Communication Controller What type of data transfer is taking place over the bus if the control signals are at CS =, C/D =, RD =, and WR =? Looking at the previous table, we see that CS = means that the 825A s data bus has been enabled for operation. Since C/D is and RD is, status information is being read from the 825A.. Programmable Communication Controller 825A USART The baud rate of the 825A must be externally generated and applied to the Rx c input of the receiver. Through software the 825A can be set up to internally divide the clock signal input by, 6 or 64 to obtain the desired baud rate. The receiver performs serial data to parallel data operation while the transmitter performs parallel to serial data operation 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -24. Programmable Communication Controller 825A USART Receiver and transmitter driven at the same baud rate 6 37 微處理機原理與應用 Lecture -25. Programmable Communication Controller 825A USART The 825A can be configured for various modes of operation through software. Control registers: Mode-control register Command register Status register Instruction format Baud rate factor (D, D ) Character length (L, L2) Parity enable (PE) Even parity check (EP) Number of stop bits (S, S2) 6 37 微處理機原理與應用 Lecture -26 2

22 . Programmable Communication Controller What value must be written to the mode-control register in order to configure the 825A such that it works as an asynchronous communication controller with the baud rate clock internally divided by 6? Character size is 8 bits; parity is odd; and one stop bit is used. Baud rate factor: B B = Character length: L 2 L = Odd parity: EP PEN = Stop bit: S 2 S = Therefore, the complete control word is D 7 D 6 D = 2 = 5E 6. Programmable Communication Controller 825A USART Command register format Transmit enable, TxEN Data terminal, DTR Receiver enable, RxEN Send break character, SBRK Error reset, ER Request to send, RTS Internal reset, IR Enter hunt mode, EH 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -28. Programmable Communication Controller 825A USART Status register format Parity error, PE Overrun error, OE Framing error, FE. Programmable Communication Controller 825A USART 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture A initialization flowchart. Programmable Communication Controller The circuit in the figure below implements serial I/O for the 888 microprocessor using an 825A. Write a program that continuously reads serial characters from the RS-232 interface, complements the received characters with software, and sends them back through the RS-232 interface. Each character is received and transmitted as an 8-bit character using 2 stop bits and no parity.. Programmable Communication Controller Solution We must first determine the addresses for the registers in the 825A that can be accessed from the microprocessor interface. Chip select (CS) is enabled for I/O read or write operations to addresses for which A 7 A 6 A 5 A 4 A 3 A 2 A A = Bit A of the address bus is used to select between the data and control (or status) registers. As shown in the figure below, the addresses for the data and control register are XX8H and XX8H 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture

23 . Programmable Communication Controller Solution Next we must determine the mode word to select an 8-bit character with 2 stop bits and no parity. As shown in the figure below, the mode word is EEH. Here we have used a baud-rate factor of 6, which means that the baud rate is given as Baud rate = Baud-rate clock/6 = 9,2/6 = 2 bps To enable the transmitter as well as receiver operation of the 825A, the command word is equal to 5H.. Programmable Communication Controller Solution Flow chart and program for the initialization of the 825A is shown below 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -34. Programmable Communication Controller Solution The receive operation starts by reading the contents of the status register at address 8H and checking if the LSB, Rx RDY is at logic. If it is not, the routine keeps reading and checking until it does become. Next we read the data register at 8H for the received data. The byte of data received is complemented and then saved for transmission. The transmit operation also starts by reading the status register at address 8H and checking if bit, Tx RDY, is logic. If it is not, we again keep reading and checking until it becomes. Next, the byte of data that was saved for transmission is written to the data register at address 8H. This causes it to be transmitted at the serial interface. The receive and transmit operations are repeated by jumping back to the point where the receive operation begins.. Programmable Communication Controller 825/645 UART 825 and 645 are newer devices than the 825A UART and implement a more versatile I/O operation. New functions include a built-in programmable baud-rate generator, double buffering on communication data registers, and enhanced status and interrupt signaling 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -36. Programmable Communication Controller 825/645 UART. Programmable Communication Controller 825/645 UART DLAB A 2 A A Register Pin layout and RS-232 interface of the 825/645 UART 6 37 微處理機原理與應用 Lecture -37 Receiver buffer (read), Transmitter Holding Register (write) Interrupt Enable X Interrupt identification (read only) X Line Control X Modem Control X Line Status X Modem Status X Scratch Division Latch (least significant byte) Division Latch (most significant byte) Register-select codes of the 825/645 UART 6 37 微處理機原理與應用 Lecture

24 . Programmable Communication Controller 825/645 UART. Programmable Communication Controller 825/645 UART Desired Baudrate Divisor Used to Generate 6 x Clock Percent Error Difference Between Desired and Actual Bit Bit Word Length bits 6 bits bits 8 bits Register bit functions and word-length select bits of the 825/645 UART Baud rates and corresponding divisors of the 825/645 UART 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -4. Programmable Communication Controller What count must be loaded into the divisor latch registers to set the data communication rate to 24 baud? What register-select code must be applied to the 825/645 when writing the bytes of the divider count into the DLL and DLM register? For 24 baud rate, the divisor is 8. When writing into DLL, the address must take A 2 A A = 2 with DLAB = and the value that is written is DLL = 8 = 5H For DLM, the address must take A 2 A A = 2 with DLAB = and the value is DLM = = H 6 37 微處理機原理與應用 Lecture -4. Programmable Communication Controller 825/645 UART RS-232 interface with EIA drivers 6 37 微處理機原理與應用 Lecture Keyboard and Display The size of the keyboard array is usually described in terms of the number of rows and columns. The microcomputer scans the keyboard array to determine which key is pressed. Keyboard debouncing is achieved by resampling the column lines a second time, about ms later, to assure the the same column line is at the logic level. Two-key lockout method and N-key rollover method are usually used to resolve the problem of multiple key depression. The way in which the display is driven by the microcomputer is said to be multiplexed 微處理機原理與應用 Lecture Keyboard and Display Keyboard Keyboard interface to a microcomputer 6 37 微處理機原理與應用 Lecture

25 .2 Keyboard and Display Display.2 Keyboard and Display Seven-segment LED Display interface to a microcomputer 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -46 Seven-segment display Programmable The 8279 can drive an 8x8 keyboard switch array and a 6-digit, eight-segment display has four signal sections: The MPU interface The key data inputs The display data outputs Scan lines used by both the keyboard and display The operation of the 8279 must be configured through software. Eight command words are provided for this purpose Programmable Block diagram and pin layout of the 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture Programmable The scan lines (SL -SL 3 ) are used as row-drive signals for the keyboard and digit-drive signals for the display. The scan line can be configure for two different modes of operation through software Decoded mode Encoded mode Programmable Decoded-mode scan line signals 6 37 微處理機原理與應用 Lecture -49 Encoded-mode scan line signals System configuration using the 886 and 微處理機原理與應用 Lecture -5 25

26 Programmable Programmable If logic is detected at a return line during key scanning, the number of the column is coded as 3-bit binary number and combined with the 3-bit row number to make a 6-bit key code. This key code input is first debounced and then loaded into an 8x8 key code FIFO within the Two other input signals, CNTR and SHIFT, are also stored as part of the key code when a switch closure is detected. MSB CNTL SHIFT SCAN RETURN LSB Keyboard and display signal timing 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture -52 Key code byte format Programmable A status register is provided within the 8279 that contains the flags indicating the status of the key code FIFO Programmable The command word is used to set the mode of operation for the keyboard and display. MSB D D K K K Command word format LSB 6 37 微處理機原理與應用 Lecture -53 Status register D 6 37 微處理機原理與應用 Lecture -54 D Display operation 8 8-bit character display Left entry 6 8-bit character display Left entry 8 8-bit character display Right entry 6 8-bit character display Right entry Display mode select code Programmable The command word K K K Keyboard operation Encoded Scan Keyboard 2-Key Lockout Decoded Scan Keyboard 2-Key Lockout Encoded Scan Keyboard N-Key Rollover Decoded Scan Keyboard N-Key Rollover Encoded Scan Sensor Matrix Decoded Scan Sensor Matrix Strobed Input, Encoded Display Scan Strobed Input, Decoded Display Scan Keyboard select codes Programmable What should be the value of command word if the display is to be set for eight 8-segment digits with right entry and the keyboard for decoded scan with N-key rollover? The three MSBs of the command word are always. The next 2 bits, DD, must be set to for eight 8-segment digits with right entry. Finally, the three LSBs are set to for decoded keyboard scan with N-key rollover. This gives Command word = DDKKK = 2 = 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture

27 Programmable The command word is used to set the frequency of operation of the It is designed to run at khz; however, in most applications a much higher frequency signal is available to supply its CLK input. For this reason, a 5-bit programmable prescaler is provided within the 8279 to divide down the input frequency. MSB P P P P P Command word format LSB Programmable The command word 6 is used for initialization of the It is used to initialize the complete display memory, the FIFO status, and the interrupt request output line. MSB C D C D C D C F C A C D C D C D Command word 6 format LSB X All zeros (X = Don t Care) AB = Hex 2 ( ) All ones 6 37 微處理機原理與應用 Lecture -57 Enable clear display when = (or by C A = ) C D coding 6 37 微處理機原理與應用 Lecture Programmable What clear operations are performed if the value of command word 6 written to the 8279 is D2 6? First, we express the command word in binary form. This gives Command word 6 = D2 6 = 2 Note that the three C D bits are. This combination causes display memory to be cleared. The C F bit is also set, and this causes the FIFO status and IRQ output to be reset Programmable Only one bit of command word 7 is functional. This bit is labeled E and is an enable signal for what is called the special-error mode. When this mode is enabled and the keyboard has N-key rollover selected, a multiple-key depression causes the S/E flag of the FIFO status register to be set. This flag can be read by the microprocessor through software. MSB E X X X X Command word 7 format LSB 6 37 微處理機原理與應用 Lecture 微處理機原理與應用 Lecture Programmable The command word 2 is used to issue the read FIFO command for accessing the the key code FIFO. MSB LSB AI X A A A X = Don t Care Command word 7 format The command word 4 is used to send new data to the display RAM. MSB LSB AI A A A A Command word 4 format The command word 3 is used the read the contents of the display RAM MSB LSB AI A A A A Command word 3 format 6 37 微處理機原理與應用 Lecture -6 27