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INTERRUPT INTERFACE OF THE 8088 AND 8086 MICROPROCESSOR INTERRUPT INTERFACE OF THE 8088 AND 8086 MICROPROCESSOR 11.1 Interrupt Mechanism, Types and Priority 11.2 Interrupt Vector Table 11.

1 INTERRUPT INTERFACE OF THE 8088 AND 8086 MICROPROCESSOR INTERRUPT INTERFACE OF THE 8088 AND 8086 MICROPROCESSOR 11.1 Interrupt Mechanism, Types and Priority 11.2 Interrupt Vector Table 11.3 Interrupt Instructions 11.4 Enabling/Disabling of Interrupts 11.5 External Hardware-Interrupt Interface Signals 11.6 External Hardware-Interrupt Sequence 微處理機原理與應用 Lecture 11-2

2 INTERRUP INTERFACE OF THE 8088 AND 8086 MICROPROCESSOR C59A Programmable Interrupt 11.8 Interrupt Interface Circuits Using the 82C59A 11.9 Software Interrupts Nonmaskable Interrupt Reset Internal Interrupt Function 微處理機原理與應用 Lecture Interrupt Mechanism, Types and Priority Interrupts provide a mechanism for quickly changing program environment. Transfer of program control is initiated by the occurrence of either an event internal to the MPU or an event in its external hardware. The section of program to which control is passed is called the interrupt service routine. The 8088 and 8086 microprocessor are capable of implementing any combination of up to 256 interrupts. Interrupts are divided into five groups: External hardware interrupts Nonmaskable interrupts Software interrupts Internal interrupts reset 微處理機原理與應用 Lecture 11-4

3 11.1 Interrupt Mechanism, Types and Priority Interrupt program context switching mechanism 微處理機原理與應用 Lecture Interrupt Mechanism, Types and Priority Hardware, software, and internal interrupts are serviced on a priority basis. Each interrupts is given a different priority level by assigning it a type number. Type 0 identifies the highest-priority interrupt, and type 255 identifies the lowest-priority interrupt. Tasks that must not be interrupted frequently are usually assigned to higher-priority levels and those that can be interrupted to lower-priority levels. Once an interrupt service routine is initiated, it could be interrupted only by a function that corresponds to a higher-priority level 微處理機原理與應用 Lecture 11-6

4 11.1 Interrupt Mechanism, Types and Priority Types of interrupts and their priority Increasing priority Reset Internal interrupts and exceptions Software interrupts Nonmaskable interrupts External hardware interrupts 微處理機原理與應用 Lecture Interrupt Vector Table An address pointer table is used to link the interrupt type numbers to the locations of their service routines in the program-storage memory. The address pointer table contains 256 address pointers (vectors), which are identified as vector 0 through vector 255. One pointer corresponds to each of the interrupt types 0 through 255. The address pointer table is located at the lowaddress end of the memory address space. It starts at and ends at 003FE 16. This represents the first 1 Kbytes of memory 微處理機原理與應用 Lecture 11-8

5 11.2 Interrupt Vector Table Interrupt vector table of the 8088/ 微處理機原理與應用 Lecture Interrupt Vector Table EXAMPLE At what address are CS 50 and IP 50 stored in memory? Solution: Each vector requires four consecutive bytes of memory for storage. Therefore, its address can be found by multiplying the type number by 4. Since CS 50 and IP 50 represent the words of the type 50 interrupt pointer, we get Address = 4 x 50 = 200 converting to binary form gives Address = = C8 16 Therefore, IP 50 is stored at 000C8 16 and CS 50 at 000CA 微處理機原理與應用 Lecture 11-10

6 11.3 Interrupt Instructions Mnemonic Meaning Format Operation Flags affected CLI Clear interrupt flag CLI 0 (IF) IF STI Set interrupt flag STI 1 (IF) IF INT n Type n software interrupt INT n (Flags) ((SP)-2) 0 TF, IF (CS) ((SP) 4) (2+4xn) (CS) (IP) ((SP) 6 ) (4xn) (IP) TF, IF IRET Interrupt return IRET ((SP)) (IP) ((SP)+2) (CS) ((SP)+4) (Flags) (SP) + 6 (SP) All INTO Interrupt on overflow INTO INT 4 steps TF, IF HLT Halt HLT Wait for an external interrupt or reset to occur None WAIT Wait WAIT Wait for TEST input to go active 微處理機原理與應用 Lecture Enabling/Disabling of Interrupts An interrupt-enable flag bit (IF) is provided within the 8088/8086 MPUs. The ability to initiate an external hardware interrupt at the INTR input is enabled by setting IF or masked out by resetting it. Executing the STI or CLI instructions, respectively, does this through software. During the initiation sequence of a service routine for an external hardware interrupt, the MPU automatically clears IF. This masks out the occurrence of any additional external hardware interrupts 微處理機原理與應用 Lecture 11-12

7 11.5 External Hardware-Interrupt Interface Signals Minimum-mode interrupt interface Key interrupt interface signals: INTR and INTA Minimum-mode 8088 and 8086 system external hardware interrupt interface 微處理機原理與應用 Lecture External Hardware-Interrupt Interface Signals Maximum-mode interrupt interface 8288 bus controller is added in the interface. The INTA and ALE signals are produced by the The bus priority lock signal LOCK is also added. This signal ensures that no other device can take over control of the system bus until the interrupt-acknowledge bus cycle is completed. Maximum-mode 8088 and 8086 system external hardware interrupt interface 國立台灣大學生物機電系微處理機原理與應用 Lecture 林達德

8 11.5 External Hardware-Interrupt Interface Signals Maximum-mode interrupt interface Interrupt bus status code to the 8288 bus controller 微處理機原理與應用 Lecture External Hardware-Interrupt Sequence COMPLETE CURRENT INSTRUCTION INTERNAL INTERRUPT? NMI NO YES YES INTR NO NO YES IF 0 1 ACKNOWLEDGE INTERRUPT READ TYPE NUMBER TF 0 1 COMPLET CURRENT INSTRUCTION EXECUTE NEXT INSTRUCTION LET TEMP = TF 微處理機原理與應用 Lecture 11-16

9 11.6 External Hardware-Interrupt Sequence CLEAR IF & TF PUSH CS & IP CALL INTERRUPT SERVICE ROUTINE EXECUTE USER INTERRUPT ROUTINE POP IP & CS Flow chart of the interrupt processing sequence of the 8088 and 8086 microprocessor POP FLAGS RESUME INTERRUPT PROCEDURE 微處理機原理與應用 Lecture External Hardware-Interrupt Sequence Interrupt-acknowledge bus cycle 微處理機原理與應用 Lecture 11-18

10 11.6 External Hardware-Interrupt Sequence Interrupt service routine To save registers and parameters on the stack Main body of the service routine To restore register and parameters from the stack Return to main program 微處理機原理與應用 Lecture PUSH XX PUSH YY PUSH ZZ..... POP ZZ POP YY POP XX IRET 11.6 External Hardware-Interrupt Sequence EXAMPLE The circuit in the next slide is used to count interrupt requests. The interrupting device interrupts the microprocessor each time the interrupt-request input signal transitions from 0 to 1. The corresponding interrupt type number generated by the 74LS244 is 60H. a. Describe the hardware operation for an interrupt request. b. What is the value of the type number sent to the microprocessor? c. Assume that (CS)=(DS)=1000H and (SS)=4000H; the main program is located at offsets of 200H; the count is held at 100H; the interrupt-service routine starts at offset 1000H from the beginning of another code segment at 2000H:0000H; and the stack starts at an offset of 500H from the stack segment. Make a map showing the memory address space. d. Write the main program and the service routine 微處理機原理與應用 Lecture 11-20

11 11.6 External Hardware-Interrupt Sequence EXAMPLE 微處理機原理與應用 Lecture External Hardware-Interrupt Sequence Solution: a. A positive transition at the CLK input of the flip-flop (interrupt request) make the Q output of the flip-flop logic 1 and presents a positive level signal at the INTR input of the When 8088 recognized this as an interrupt request, it responds by generating the INTA signal. The logic 0 output on the line clears the flip-flop and enables the 74LS244 buffer to present the type number to the This number is read of the data bus by the 8088 and is used to initiate the interrupt-service routine. b. From the inputs and outputs of the 74LS244, we see the type number is AD 7 AD 1 AD 0 = 2Y 4 2Y 3 2Y 2 2Y 1 1Y 4 1Y 3 1Y 2 1Y 1 = AD 7 AD 1 AD 0 = 60H 微處理機原理與應用 Lecture 11-22

12 11.6 External Hardware-Interrupt Sequence Solution: c. The memory organization is in the right figure 微處理機原理與應用 Lecture External Hardware-Interrupt Sequence Solution: d. The flowcharts of the main program and interrupt-service routine Main Program Set up data segment, stack segment, and stack pointer SRVRTN Save processor status Set up the interrupt vector Increment the count Enable interrupts Restore processor status Wait for interrupt Return 微處理機原理與應用 Lecture 11-24

13 11.6 External Hardware-Interrupt Sequence Solution: 微處理機原理與應用 Lecture C59A Programmable Interrupt The 82C59A is an LSI peripheral IC that is designed to simplify the implementation of the interrupt interface in the and 8086-based microcomputer system. The 82C59A is known as a programmable interrupt controller or PIC. The operation of the PIC is programmable under software control. The 82C59A can be cascaded to expand from 8 to 64 interrupt inputs 微處理機原理與應用 Lecture 11-26

14 C59A Programmable Interrupt Block diagram of the 82C59A Block diagram and pin layout of the 82C59A 微處理機原理與應用 Lecture C59A Programmable Interrupt Internal architecture of the 82C59A 微處理機原理與應用 Lecture 11-28

15 C59A Programmable Interrupt Internal architecture of the 82C59A Eight functional parts of the 82C59A The data bus buffer The read/write logic The control logic The in-service register The interrupt-request register The priority resolver The interrupt-mask register The cascade buffer/comparator 微處理機原理與應用 Lecture C59A Programmable Interrupt Programming the 82C59A Two types of command words are provided to program the 82C59A: the initialization command words (ICW) and the operational command words (OCW). ICW commands (ICW 1, ICW 2, ICW 3, ICW 4 ) are used to load the internal control registers of the 82C59A to define the basic configuration or mode in which it is used. The OCW commands (OCW 1, OCW 2, OCW 3 ) permit the 8088 or 8086 microprocessor to initiate variations in the basic operating modes defined by the ICW commands. The MPU issues commands to the 82C59A by initiating output (I/O-mapped) or write (Memory-mapped) cycles 微處理機原理與應用 Lecture 11-30

16 C59A Programmable Interrupt Programming the 82C59A ICW1 ICW2 NO (SNGL=1) IN CASCADE MODE? YES (SNGL=0) ICW3 NO (IC4=0) IS ICW4 NEEDED? YES (IC4=1) ICW4 READY TO ACCEPT INTERRUPT REQUESTS 微處理機原理與應用 Lecture Initialization sequence of the 82C59A C59A Programmable Interrupt Initialization command words ICW 微處理機原理與應用 Lecture 11-32

17 C59A Programmable Interrupt EXAMPLE What value should be written into ICW 1 in order to configure the 82C59A so that ICW 4 is needed in the initialization sequence, the system is going to use multiple 82C59As, and its inputs are to be level sensitive? Assume that all unused bits are to be logic 0. Solution: Since ICW 4 is to be initialized, D 0 must be logic 1, D 0 = 1 For cascaded mode of operation, D 1 must be 0, D 1 = 0 And for level-sensitive inputs, D 3 must be 1, D 3 = 1 Bits D 2 and D 5 through D 7 are don t-care states and are 0. D 2 = D 5 = D 6 = D 7 = 0 Moreover, D 4 must be fixed at the 1 logic level, D 4 = 1 This gives the complete command word D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 = = 微處理機原理與應用 Lecture C59A Programmable Interrupt Initialization command words ICW 2 is used for type number determination 微處理機原理與應用 Lecture 11-34

18 C59A Programmable Interrupt EXAMPLE What should be programmed into register ICW 2 if the type numbers output on the bus by the device are to range from F0 16 through F7 16? Solution: To set the 82C59A up so that type numbers are in the range of F0 16 through F7 16, its device code bits must be D 7 D 6 D 5 D 4 D 3 = The lower three bits are don t-care states and all can be 0s. This gives the word D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 = = F 微處理機原理與應用 Lecture C59A Programmable Interrupt Initialization command words ICW 3 is required only for cascaded mode of operation 微處理機原理與應用 Lecture 11-36

19 C59A Programmable Interrupt EXAMPLE Assume that a master PIC is to be configured so that its IR 0 through IR 3 inputs are to accept inputs directly from external devices, but IR 4 through IR 7 are to be supplied by the INT outputs of slaves. What code should be used for the initialization command word ICW 3? Solution: For IR 0 through IR 3 to be configured to allow direct inputs from external devices, bits D 0 through D 3 of ICW 3 must be logic 0: D 3 D 2 D 1 D 0 = The other IR inputs of the master are to be supplied by INT outputs of slaves. Therefore, their control bits must be all 1: D 7 D 6 D 5 D 4 = This gives the complete command word D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 = = F 微處理機原理與應用 Lecture C59A Programmable Interrupt Initialization command words ICW 4 is used to configure device for use with the 8088 or 8086 and selects various features in its operation 微處理機原理與應用 Lecture 11-38

20 C59A Programmable Interrupt Operational command words OCW 1 is used to access the contents of the interrupt-mask register (IMR). Setting a bit to logic 1 masks out the associated interrupt input 微處理機原理與應用 Lecture C59A Programmable Interrupt EXAMPLE What should be the OCW 1 code if interrupt inputs IR 0 through IR 3 are to be masked and IR 4 through IR 7 are to be unmasked? Solution: For IR 0 through IR 3 to be masked, their corresponding bits in the mask register must be make logic 1: D 3 D 2 D 1 D 0 = On the other hand, for IR 4 through IR 7 to be unmasked, D 4 through D 7 must be logic 0: D 7 D 6 D 5 D 4 = This gives the complete command word D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 = = 0F 微處理機原理與應用 Lecture 11-40

21 C59A Programmable Interrupt Operational command words OCW 2 is used to select appropriate priority scheme and assigns an IR level for the scheme 微處理機原理與應用 Lecture C59A Programmable Interrupt EXAMPLE What OCW 2 must be issued to the 82C59A if the priority scheme rotate on nonspecific EOI command is to be selected? Solution: To enable the rotate on nonspecific EOI command priority scheme, bits D 7 through D 5 must be set to 101. Since a specific level does not have to be considered, the rest of the bits in the command word can be 0. This gives OCW 2 as D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 = = A 微處理機原理與應用 Lecture 11-42

22 C59A Programmable Interrupt Operational command words OCW 3 permits reading of the contents of the ISR or IRR registers through software 微處理機原理與應用 Lecture C59A Programmable Interrupt EXAMPLE Write a program that will initialize an 82C59A with the initialization command words ICW 1, ICW 2, ICW 3 derived in the previous examples, and ICW 4 is equal to 1F 16. Assume that the 82C59A resides at address A in the memory address space. Solution: Since the 82C59A resides in the memory address space, we can use a series of move instructions to write the initialization command words into its registers. Note that the memory address for an ICW is A if A 0 = 0, and it is A if A 0 = 1. However, before doing this, we must first disable interrupts. This is done with the instruction CLI ; Disable interrupts 微處理機原理與應用 Lecture 11-44

23 C59A Programmable Interrupt Next we will create a data segment starting at address : MOV AX, 0 ;Create a data segment at 00000H MOV DS, AX Now we are ready to write the command words to the 82C59A: MOV AL, 19H ;Load ICW1 MOV [0A000H], AL ;Write ICW1 to 82C59A MOV AL, 0F0H ;Load ICW2 MOV [0A001H], AL ;Write ICW2 to 82C59A MOV AL, 0F0H ;Load ICW3 MOV [0A001H], AL ;Write ICW3 to 82C59A MOV AL, 1FH ;Load ICW4 MOV [0A001H], AL ;Write ICW4 to 82C59A Initialization is now complete and the interrupts can be enabled STI ;Enable interrupts 微處理機原理與應用 Lecture Interrupt Interface Circuits Using the 82C59A Minimum-mode interrupt interface for the 8088 microcomputer using the 82C59A 微處理機原理與應用 Lecture 11-46

24 11.8 Interrupt Interface Circuits Using the 82C59A Minimum-mode interrupt interface for the 8086 microcomputer using the 82C59A 微處理機原理與應用 Lecture Interrupt Interface Circuits Using the 82C59A For applications that require more than eight interrupt-request inputs, several 82C59As are connected into a master/slave configuration. Master/slave connection of the 82C59A interface 國立台灣大學生物機電系微處理機原理與應用 Lecture 林達德

25 11.8 Interrupt Interface Circuits Using the 82C59A Maximum-mode interrupt interface for the 8088 microcomputer using the 82C59A 微處理機原理與應用 Lecture Interrupt Interface Circuits Using the 82C59A EXAMPLE Analyze the circuit in the following figure and write an appropriate main program and a service routine that counts as a decimal number the positive edges of the clock signal applied to the IR 0 input of the 82C59A 微處理機原理與應用 Lecture 11-50

26 11.8 Interrupt Interface Circuits Using the 82C59A Solution: Lets first determine the I/O addresses of the 82C59A registers: A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 = for A 1 = 0, M/IO = 0 and = for A 1 = 1, M/IO = 0 These two I/O addresses are FF00H and FF02H, respectively. The address FF00H is for the ICW 1 and FF02H is for the ICW 2, ICW 3, ICW 4, and OCW 1 command words. The command words are: ICW 1 = = 13H ICW 2 = = 48H ICW 3 = not needed ICW 4 = = 03H OCW 1 = = FEH 微處理機原理與應用 Lecture Interrupt Interface Circuits Using the 82C59A Software organization: 微處理機原理與應用 Lecture 11-52

27 11.8 Interrupt Interface Circuits Using the 82C59A Flowcharts of the main program and service routine: Main Program Set up data segment, stack segment, and stack pointer SRV72 Save processor status Set up the interrupt vector Increment the count Initialize 82C59A Restore processor status Enable interrupts Return Wait for interrupt 微處理機原理與應用 Lecture Interrupt Interface Circuits Using the 82C59A Program: ;MAIN PROGRAM CLI ;Start with interrupt disabled START: MOV AX, 0 ;Extra segment at 00000H MOV ES, AX MOV AX, 1000H ;Data segment at 01000H MOV DS, AX MOV AX, 0FF00H ;Stack segment at 0FF00H MOV SS, AX MOV SP, 100H ;Top of stack at 10000H MOV AX, OFFSET SRV72 ;Get offset for SRV72 MOV [ES:120H], AX ;Set up the IP MOV AX, SEG SRV72 ;Get CS for the service routine MOV [ES:122H], AX ;Set up the CS 微處理機原理與應用 Lecture 11-54

28 11.8 Interrupt Interface Circuits Using the 82C59A Program: MOV DX, 0FF00H ;ICW1 address MOV AL, 13H ;Edge trig input, single 8259A OUT DX, AL MOV DX, 0FF02H ;ICW2, ICW4, OCW1 address MOV AL, 48H ;ICW2, type 72 OUT DX, AL MOV AL, 03H ;ICW4, AEOI, nonbuf mode OUT DX, AL MOV AL, 0FEH ;OCW1, mask all but IR0 OUT DX, AL STI ;Enable the interrupts 微處理機原理與應用 Lecture Interrupt Interface Circuits Using the 82C59A Program: SRV72: PUSH AX ;Save register to be used MOV AL, [COUNT] ;Get the count INC AL ;Increment the count DAA ;Decimal adjust the count MOV [COUNT], AL ;Save the new count POP AX ;Restore the register used IRET ;Return from interrupt 微處理機原理與應用 Lecture 11-56

29 11.9 Software Interrupts The 8088 and 8086 microcomputer systems are capable of implementing up to 256 software interrupts. The INT n instruction is used to initiate a software interrupt. The software interrupt service routine vectors are also located in the memory locations in the vector table. Software interrupts are of higher priority than the external interrupts and are not masked out by IF. The software interrupts are actually vectored subroutine calls 微處理機原理與應用 Lecture Nonmaskable Interrupt The nonmaskable interrupt (NMI) is initiated from external hardware. Differences between NMI and other external interrupts: NMI can not be masked out with the interrupt flag. Request for NMI service are signaled to the 8088/8086 microprocessor by applying logic 1 at the NMI input, not the INTR input. NMI input is positive edge-triggered. Therefore, a request for NMI is automatically latched internal to the MPU. NMI automatically vectors from the type 2 vector location in the pointer table ( ~000A 16 ) Typically, the NMI is assigned to hardware events that must be responded to immediately, such power failure 微處理機原理與應用 Lecture 11-58

30 11.11 Reset The RESET input of the 8088 and 8086 microprocessors provides a hardware means for initializing the microcomputer. Reset interface and timing sequence of the 微處理機原理與應用 Lecture Reset 8088 signal status 8086 signal status Bus and control signal status of the 8088/8086 during system reset 微處理機原理與應用 Lecture 11-60

31 11.11 Reset When the MPU recognizes the RESET input, it initiates its internal initialization routine. At completion of initialization, the flags are all cleared, the registers are set to the values in the following table. CPU COMPONENT Flags Instruction pointer CS Register DS Register SS Register ES Register Queue 微處理機原理與應用 Lecture Clear 0000H FFFFH 0000H 0000H 0000H Empty CONTENT Reset The external hardware interrupts are disabled after the initialization. Program execution begins at address FFFF0 16 after reset. This storage location contains an instruction that will cause a jump to the startup (boot-strap) program that is used to initialize the reset of the microcomputer system s resources, such as I/O ports, the interrupt flag, and data memory. After the system-level initialization is complete, another jump can be performed to the starting point of the microcomputer s operating system or application program 微處理機原理與應用 Lecture 11-62

32 11.12 Internal Interrupt Functions Four of the 256 interrupts of the 8088 and 8086 are dedicated to internal interrupt functions. Internal interrupts differ from external hardware interrupts in that they occur due to the result of executing an instruction, not an event that takes place in external hardware. Internal interrupts are not masked out with IF flag. Internal interrupts of the 8088 and 8086 MPU: Divide error (Type number 0) Single step (Type number 1) Breakpoint interrupt (Type number 3) Overflow error (Type number 4) 微處理機原理與應用 Lecture Internal Interrupt Functions Internal interrupt vector locations 微處理機原理與應用 Lecture 11-64

Microsoft PowerPoint - STU_EC_Ch08.ppt

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