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查询供应商捷多邦, 专业 PCB 打样工厂,24 小时加急出货 Order this document by /D The operational amplifier provides rail to rail operation on both the input and output. The output can swing within 5 mv of each rail.

V and ground), yet can operate with a supply of up to 7. V and ground.

1 查询供应商捷多邦, 专业 PCB 打样工厂,24 小时加急出货 Order this document by /D The operational amplifier provides rail to rail operation on both the input and output. The output can swing within 5 mv of each rail. This rail to rail operation enables the user to make full use of the entire supply voltage range available. It is designed to work at very low supply voltages (. V and ground), yet can operate with a supply of up to 7. V and ground. Output current boosting techniques provide high output current capability while keeping the drain current of the amplifier to a minimum. Low Voltage, Single Supply Operation (. V and Ground to 7. V and Ground) High Input Impedance: Typically 4 fa Input Current Typical Unity Gain 5. V = 5. V = 4. MHz High Output Current (ISC = 5 5. V, V) Output Voltage Swings within 5 mv of Both V Input Voltage Range Includes Both Supply Rails High Voltage Gain: db V No Phase Reversal on the Output for Over Driven Input Signals Input Offset Trimmed to.5 mv Typical Low Supply Current (ID =.2 ma/per Amplifier, Typical) 6 Ω Drive Capability Extended Operating Temperature Range ( 4 to 5 C) APPLICATIONS Single Cell NiCd/Ni MH Powered Systems Interface to DSP Portable Communication Devices Low Voltage Active Filters Telephone Circuits Instrumentation Amplifiers Audio Applications Power Supply Monitor and Control Compatible with VCX Logic Inputs Input Stage Offset Voltage Trim Simplified Block Diagram Buffer with V Level Shift Saturation Detector Base Current Boost Output Stage Base Current Boost This device contains 98 active transistors per amplifier. Outputs Device LOW VOLTAGE RAIL TO RAIL DUAL OPERATIONAL AMPLIFIER Output Inputs VEE P D SEMICONDUCTOR TECHNICAL DATA 8 P SUFFIX PLASTIC PACKAGE CASE D SUFFIX PLASTIC PACKAGE CASE 75 (SO 8) PIN CONNECTIONS (Dual, Top View) ORDERING INFORMATION Operating Temperature Range T A = 4 to +5 C Output 2 Inputs 2 Package Plastic DIP SO 8 This document contains information on a new product. Specifications and information herein Motorola, Inc. 998 Rev

2 MAXIMUM RATINGS Rating Symbol Value Unit Supply Voltage ( to VEE) ÁÁÁÁ ÁÁÁÁÁ VS 7. ÁÁÁ V ESD Protection Voltage at any Pin ÁÁÁÁ ÁÁÁÁÁ VESD 2 ÁÁÁ V Human Body Model ÁÁÁÁÁÁÁÁÁÁ Voltage at Any Device Pin ÁÁÁÁ VDP ÁÁÁÁÁ VS ±.3 ÁÁÁ V Input Differential Voltage Range ÁÁÁÁ VIDR ÁÁÁÁÁ to VEEÁÁÁ V Common Mode Input Voltage Range Output Short Circuit Duration Maximum Junction Temperature Storage Temperature Range Maximum Power Dissipation ÁÁÁÁ VCM ÁÁÁÁÁ to VEEÁÁÁ V ÁÁÁÁ ts ÁÁÁÁÁ (Note ) ÁÁÁ s ÁÁÁÁ TJ ÁÁÁÁÁ 5 ÁÁÁ C ÁÁÁÁ Tstg ÁÁÁÁÁ 65 to 5ÁÁÁ C ÁÁÁÁ PD ÁÁÁÁÁ (Note ) ÁÁÁ mw NOTES:. Power dissipation must be considered to ensure maximum junction temperature (T J ) is not exceeded. 2. ESD data available upon request. DC ELECTRICAL CHARACTERISTICS ( = 5. V, VEE = V, VCM = VO = /2, RL to /2,, unless otherwise noted.) Characteristic Symbol Min Typ Max Unit ÁÁÁÁÁÁ Input Offset Voltage (VCM = to ) VIO =. V TA = 4 to 5 C = 3. V TA = 4 to 5 C = 5. V TA = 4 to 5 C ÁÁÁÁÁÁ Input Offset Voltage Temperature Coefficient (RS = 5 Ω) TA = 4 to 5 C ÁÁÁÁÁ Input Bias Current ( =. to 5. V) VIO/ T ÁÁÁÁÁ I IIB I ÁÁÁÁ ÁÁÁÁ 4 ÁÁÁÁ ÁÁÁ fa ÁÁÁÁÁ Common Mode Input Voltage Range ÁÁÁÁÁ VICR ÁÁÁÁ VEE ÁÁÁÁ ÁÁÁÁ ÁÁÁ V ÁÁÁÁÁ Large Signal Voltage Gain ÁÁ kv/v AVOL =. V () RL = kω 25 RL =. kω 5. 5 = 3. V () RL = kω 5 5 RL =. kω 25 = 5. V () RL = kω 5 5 RL =. kω mv µv/ C

3 DC ELECTRICAL CHARACTERISTICS (continued) ( = 5. V, VEE = V, VCM = VO = /2, RL to /2,, unless otherwise noted.) Characteristic Symbol Min Typ Max Unit ÁÁÁÁÁ Output Voltage Swing, High (VID = ±.2 V) ÁÁ V VOH =. V () RL = kω.9.95 RL = 6 Ω =. V (TA = 4 to 5 C) RL = kω.85 RL = 6 Ω.8 = 3. V () RL = kω RL = 6 Ω = 3. V (TA = 4 to 5 C) RL = kω 2.85 RL = 6 Ω 2.75 = 5. V () RL = kω RL = 6 Ω = 5. V (TA = 4 to 5 C) RL = kω 4.85 RL = 6 Ω 4.7 ÁÁÁÁÁÁ Output Voltage Swing, Low (VID = ±.2 V) VOL =. V () RL = kω.5.2 RL = 6 Ω..5 =. V (TA = 4 to 5 C) RL = kω. RL = 6 Ω.5 = 3. V () RL = kω.5.2 RL = 6 Ω..8 = 3. V (TA = 4 to 5 C) RL = kω. RL = 6 Ω.5 = 5. V () RL = kω.5.2 RL = 6 Ω.5. = 5. V (TA = 4 to 5 C) RL = kω. RL = 6 Ω.2 Common Mode Rejection (Vin = to 5. V) CMR 6 75 db VOL 6 75 µv/v ÁÁÁÁÁÁÁÁÁ Output Short Circuit Current (Vin Diff = ±. V) ISC ma =. V Source Sink 3 26 = 3. V Source Sink = 5. V Source Sink ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Power Supply Current (Per Amplifier, VO = V) ID =. V.2.75 = 3. V.5 2. = 5. V =. V (TA = 4 to 5 C) 2. = 3. V (TA = 4 to 5 C) 2.25 = 5. V (TA = 4 to 5 C) 2.5 V ma

4 AC ELECTRICAL CHARACTERISTICS ( = 5. V, VEE = V, VCM = VO = /2,, unless otherwise noted.) Characteristic Symbol Min Typ Max Unit ÁÁÁÁÁÁ Slew Rate (VS = ±2.5 V, VO = 2. to 2. V, RL = 2. kω, AV =.) SR Positive Slope Negative Slope Unity Gain Bandwidth BW MHz =. V = 3. V = 5. V Gain Margin ÁÁÁÁÁ (RL = kω, CL = pf) Am 6.5 db Phase Margin (RL = kω, CL = pf) φm Deg ÁÁÁ 6 ÁÁÁÁÁÁ Channel Separation (f =. Hz to 2 khz, ÁÁÁÁÁ RL = 6 Ω) CS 2 db ÁÁ Power Bandwidth ÁÁÁÁÁ (VO = 4. Vpp, RL =. kω, THD.%) ÁÁÁÁÁ BWP 2 khz ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ Total Harmonic Distortion (VO = 4.5 Vpp, RL = 6 Ω, AV =.) THD % f =. khz.4 f = khz. ÁÁÁÁÁ Differential Input Resistance (VCM = V) ÁÁÁÁÁÁÁÁ ÁÁÁÁ >. ÁÁÁÁ Rin ÁÁÁ terraω ÁÁÁÁÁ Differential Input Capacitance (VCM = V) ÁÁÁÁÁ Cin ÁÁÁÁ ÁÁÁÁ 2. ÁÁÁÁ ÁÁÁ pf ÁÁÁÁÁ Equivalent Input Noise Voltage ( =. V, VCM = V, VEE = Gnd, ÁÁ nv/ Hz en RS = Ω) f =. khz 3 f = khz 6 V/µs Figure. Representative Block Diagram IN IN+ Offset Voltage Trim Output Voltage Saturation Detector Clamp Out Body Bias

5 GENERAL INFORMATION The dual operational amplifier is unique in its ability to provide. V rail to rail performance on both the input and output by using a SMARTMOS process. The amplifier output swings within 5 mv of both rails and is able to provide 5 ma of output drive current with a 5. V supply, and ma with a. V supply. A 5. MHz bandwidth and a slew rate of 3. V/µs is achieved with high speed depletion mode NMOS (DNMOS) and vertical PNP transistors. This device is characterized over a temperature range of 4 C to 5 C. CIRCUIT INFORMATION Input Stage One volt rail to rail performance is achieved in the at the input by using a single pair of depletion mode NMOS devices (DNMOS) to form a differential amplifier with a very low input current of 4 fa. The normal input common mode range of a DNMOS device, with an ion implanted negative threshold, includes ground and relies on the body effect to dynamically shift the threshold to a positive value as the gates are moved from ground towards the positive supply. Because the device is manufactured in a p well process, the body effect coefficient is sufficiently large to ensure that the input stage will remain substantually saturated when the inputs are at the positive rail. This also applies at very low supply voltages. The. V rail to rail input stage consists of a DNMOS differential amplifier, a folded cascode, and a low voltage balanced mirror. The low voltage cascoded balanced mirror provides high st stage gain and base current cancellation without sacrificing signal integrity. Also, the input offset voltage is trimmed to less than. mv because of the limited available supply voltage. The body voltage of the input DNMOS differential pair is internally trimmed to minimize the input offset voltage. A common mode feedback path is also employed to enable the offset voltage to track over the input common mode voltage. The total operational amplifier quiescent current drop is.3 ma/amp. Output Stage An additional feature of this device is an on demand base current cancellation amplifier. This feature provides base drive to the output power devices by making use of a buffer amplifier to perform a voltage to current conversion. This is done in direct proportion to the load conditions. This on demand feature allows these amplifiers to consume only a few micro amps of current when the output stage is in its quiescent mode. Yet it provides high output current when required by the load. The rail to rail output stage current boost circuit provides 5 ma of output current with a 5. V supply (For a. V supply output stage will do ma) enabling the operational amplifier to drive a 6 Ω load. A buffer is necessary to isolate the load current effects in the output stage from the input stage. Because of the low voltage conditions, a DNMOS follower is used to provide an essentially zero voltage level shift. This buffer isolates any load current changes on the output stage from loading the input stage. A high speed vertical PNP transistor provides excellent frequency performance while sourcing current. The operational amplifier is also internally compensated to provide a phase margin of 6 degrees. It has a unity gain of 5. MHz with a 5. V supply and 4. MHz with a. V supply. LOW VOLTAGE OPERATION The will operate at supply voltages from.9 to 7. V and ground. When using the at supply voltages of less than.2 V, input offset voltage may increase slightly as the input signal swings within approximately 5 mv of the positive supply rail. This effect occurs only for supply voltages below.2 V, due to the input depletion mode MOSFETs starting to transition between the saturated to linear region, and should be considered when designing high side dc sensing applications operating at the positive supply rail. Since the device is rail to rail on both input and output, high dynamic range single battery cell applications are now possible.

V sat, OUTPUT SATURATION VOLTAGE (mv) 2 4 6 6 4 2. k Figure 2. Output Saturation versus Load Resistance = 5. V VEE = V RL to /2 k k RL, LOAD RESISTANCE (kω).

5 Saturation VEE = 5. V TA = 55 C VEE 4. 8. 2 6 2 24 I IB, INPUT CURRENT (pa).... Figure 4. Input Current versus Temperature 25 5 75 25 A VOL, GAIN (db) 8 6 4 2. Figure 5.

6 V sat, OUTPUT SATURATION VOLTAGE (mv) k Figure 2. Output Saturation versus Load Resistance = 5. V VEE = V RL to /2 k k RL, LOAD RESISTANCE (kω). M VEE M V sat, OUTPUT SATURATION VOLTAGE (V).5. Figure 3. Drive Output Source/Sink Saturation Voltage versus Load Current Source Saturation TA = 55 C IO, OUTPUT CURRENT (ma). Sink.5 Saturation VEE = 5. V TA = 55 C VEE I IB, INPUT CURRENT (pa).... Figure 4. Input Current versus Temperature A VOL, GAIN (db) Figure 5. Gain and Phase versus Frequency = 2.5 V RL = k Phase Gain. k k Phase Margin = 6 k. M M φ m, EXCESS PHASE (DEGREES) f, FREQUENCY (Hz) Figure 6. Transient Response Figure 7. Slew Rate 2 mv/div =.5 V VEE =.5 V ACL =. CL = pf RL = k. V/DIV (mv) = 2.5 V ACL =. CL = pf RL = 6 Ω t, TIME (5 µs/div) t, TIME (. µs/div)

7 PD max, MAXIMUM POWER DISSIPATION (mw) Figure 8. Maximum Power Dissipation versus Temperature SO 8 Pkg DIP Pkg AVOL, OPEN LOOP GAIN (db) Figure 9. Open Loop Voltage Gain versus Temperature 6 5 = 2.5 V 4 RL = 6 Ω V O, OUTPUT VOLTAGE (V pp ) Figure. Output Voltage versus Frequency = 2.5 V AV =. RL = 6 Ω. k k k. M f, FREQUENCY (khz) CMR, COMMON MODE REJECTION (db) Figure. Common Mode Rejection versus Frequency = 2.5 V. k k k f, FREQUENCY (khz). M PSR, POWER SUPPLY REJECTION (db) Figure 2. Power Supply Rejection versus Frequency = 2.5 V =.5 V VEE =.5 V 2 Either or VEE. k k k f, FREQUENCY (khz) IISCI, OUTPUT SHORT CIRCUIT CURRENT (ma) Figure 3. Output Short Circuit Current versus Output Voltage = 2.5 V Sink Source VS VO (V)

8 IISCI, OUTPUT SHORT CIRCUIT CURRENT (ma) Figure 4. Output Short Circuit Current versus Temperature 8 Sink = 2.5 V Source ICC, SUPPLY CURRENT PER AMPLIFIER (ma) Figure 5. Supply Current per Amplifier versus Supply Voltage with No Load ±.5 ±. ±.5 ±2., VEE, SUPPLY VOLTAGE (V) TA = 55 C ±2.5 5 Figure 6. Input Offset Voltage Temperature Coefficient Distribution 5 Figure 7. Input Offset Voltage Distribution PERCENTAGE OF AMPLIFIERS (%) = 3. V VO =.5 V VEE = V 6 Amplifiers Tested from 2 Wafer Lots PERCENTAGE OF AMPLIFIERS (%) = 3. V VO =.5 V VEE = V 6 Amplifiers Tested from 2 Wafer Lots TCVIO, INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT (µv/ C) INPUT OFFSET VOLTAGE (mv) THD, TOTAL HARMONIC DISTORTION (%).... Figure 8. Total Harmonic Distortion versus Frequency with. V Supply AV = AV = AV = AV =. Vout =.5 Vpp RL = 6 Ω VEE =. V. k k f, FREQUENCY (Hz) k THD, TOTAL HARMONIC DISTORTION (%). AV =... Figure 9. Total Harmonic Distortion versus Frequency with 5. V Supply Vout =.4 Vpp RL = 6 Ω AV = AV = AV =.. k k f, FREQUENCY (Hz) VEE = 5. V k

9 SR, SLEW RATE (V/ µ s) Figure 2. Slew Rate versus Temperature VEE =. V + Slew Rate VEE =. V Slew Rate VEE = 5. V + Slew Rate VEE = 5. V Slew Rate GBW, GAIN BANDWIDTH PRODUCT (MHz) Figure 2. Gain Bandwidth Product versus Temperature VEE = 5. V f = khz AVOL, GAIN (db) RL = 6 Ω 2 CL = 4 k k Figure 22. Voltage Gain and Phase versus Frequency VEE =. V VEE =. V VEE = 5. V VEE = 5. V. M M f, FREQUENCY (Hz) m, PHASE MARGIN ( ) φ Figure 23. Gain and Phase Margin versus Temperature VEE = 5. V RL = 6 Ω CL = pf Phase Margin Gain Margin AV, GAIN MARGIN (db) m, PHASE MARGIN ( ) φ Figure 24. Gain and Phase Margin versus Differential Source Resistance VEE = 5. V RL = 6 Ω CL = pf Phase Margin Gain Margin AV, GAIN MARGIN (db) m, PHASE MARGIN ( ) φ Figure 25. Feedback Loop Gain and Phase versus Capacitive Load Phase Margin Gain Margin VEE = 5. V RL = 6 Ω A V, GAIN MARGIN (db). k k k. M RT, DIFFERENTIAL SOURCE RESISTANCE (Ω) CL, CAPACITIVE LOAD (pf)

10 CS, CHANNEL SEPARATION (db) Figure 26. Channel Separation versus Frequency AV = AV = 4 VEE = 5. V RL = 6 Ω 2 VO = 4. Vpp 3 3 k 3 k k 3 k f, FREQUENCY (Hz) VO, OUTPUT VOLTAGE (Vpp) RL= 6 Ω Figure 27. Output Voltage Swing versus Supply Voltage ±.5 ±. ±.5 ±2. ±2.5 ±3. ±3.5, VEE, SUPPLY VOLTAGE (V) en, EQUIVALENT INPUT NOISE VOLTAGE (nv/ Hz) Figure 28. Equivalent Input Noise Voltage versus Frequency VEE = 5. V. k k k f, FREQUENCY (Hz) m, PHASE MARGIN ( ) φ Figure 29. Gain and Phase Margin versus Supply Voltage RL = 6 Ω CL = Phase Margin Gain Margin VEE, SUPPLY VOLTAGE (V) A V, GAIN MARGIN (db) VEE, USEABLE SUPPLY VOLTAGE (V) Figure 3. Useable Supply Voltage versus Temperature AVOL db RL = 6 Ω AVOL, OPEN LOOP GAIN (db) Figure 3. Open Loop Gain versus Supply Voltage VEE, SUPPLY VOLTAGE (V) RL = 6 Ω 5. 6.

11 Figure 32.. V Oscillator RT 47 k CT. nf Ra 36 k +. V FO. khz. Vpp Rb 36 k R2 22 k F O 2(Ra Rb) -2R C T T In* *- R2 Figure 33.. V Voiceband Filter C2 4 pf Rf k.5 V R2 k C 8 nf R k +.5 V Af VO f L 2RC 2 Hz fl fh f H 2R f C f 4. khz A f R f R2

12 Figure 34. Power Supply Application 5 V 5. V Vref FB 47 pf 22 k 5 6 MC Output A Output B k 332. k. k Provides current sense amplification and eliminates leading edge spike. From Current Sense Figure 35.. V Current Pump IO IL RL 75 VL R5 2.4 k. V R4. k R3. k R. k VO R2 3.3 k For best performance, use close tolerance resistors. IO IL IO/ IL 435 ma 463 µa 22 ma 492 µa 2 x 6

13 OUTLINE DIMENSIONS P SUFFIX PLASTIC PACKAGE CASE ISSUE K NOTE 2 T SEATING PLANE H 8 5 B 4 F A L C J N M D K G.3 (.5) M T A M B M NOTES:. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, 982. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G 2.54 BSC. BSC H J K L 7.62 BSC.3 BSC M N D SUFFIX PLASTIC PACKAGE CASE 75 6 (SO 8) ISSUE T A E B C A 8 e D B 5 4 H A.25 M C B S A S.25 M B M SEATING PLANE. h X 45 C L NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y4.5M, DIMENSIONS ARE IN MILLIMETER. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION.5 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.27 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS DIM MIN MAX A A..25 B C.9.25 D E e.27 BSC H h.25.5 L

14 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

15 Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4, P.O. Box 545, Denver, Colorado or Nishi Gotanda, Shagawa ku, Tokyo, Japan Customer Focus Center: Mfax : RMFAX@ .sps.mot.com TOUCHTONE ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, Motorola Fax Back System US & Canada ONLY Ting Kok Road, Tai Po, N.T., Hong Kong HOME PAGE:

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查询 MC33502 供应商 捷多邦, 专业 PCB 打样工厂,24 小时加急出货 Order this document by MC33502/D The MC33502 operational amplifier provides rail to rail operation on both t

查询 MC33502 供应商捷多邦, 专业 PCB 打样工厂,24 小时加急出货 Order this document by MC33502/D The MC33502 operational amplifier provides rail to rail operation on both t