High precision 5 µV zero drift, low-power op amp

Transcription

1 OA1ZHA, OA2ZHA, OA4ZHA High precision 5 µv zero drift, low-power op amp Datasheet - production data Features Very high accuracy and stability: offset voltage 5 µv max at 25 C, 8 µv over full temperature range (- C to 125 C) Rail-to-rail input and output Low supply voltage: V Low power consumption: µa max. at 5 V Gain bandwidth product: khz High tolerance to ESD: 4 kv HBM Extended temperature range: - to +125 C Micro-packages: SC7-5, DFN8 2x2, and QFN16 3x3 Benefits High precision op amp without the need of calibration Accuracy virtually unaffected by temperature change Applications Wearable Fitness and healthcare Medical instrumentation Description The series of low power, high precision op amp, offer very low input offset voltages with virtually zero drift. are respectively the single, dual and quad operational amplifier versions, with pinout compatible with industry standards. The series offers rail-to-rail input and output, excellent speed/power consumption ratio, and khz gain bandwidth product, while consuming less than µa at 5 V. All devices also feature an ultra-low input bias current. The family is the ideal choice for wearable, fitness and healthcare applications. Table 1. Device summary Order code Temperature range Package Packaging Marking OA1ZHA22C SC7-5 K44 OA2ZHA22Q DFN8 2x2 K33 - to +125 C Tape and reel OA2ZHA34S MiniSO8 K143 OA4ZHA33Q QFN16 3x3 K193 March 14 DocID25994 Rev 1 1/34 This is information on a product in full production.

2 Contents Contents 1 Package pin connections Absolute maximum ratings and operating conditions Electrical characteristics Application information Operation theory Time domain Frequency domain Operating voltages Input pin voltage ranges Rail-to-rail input Input offset voltage drift over temperature Rail-to-rail output Capacitive load PCB layout recommendations Optimized application recommendation EMI rejection ration (EMIRR) Application examples Oxygen sensor Precision instrumentation amplifier Low-side current sensing Package information SC7-5 package information DFN8 2x2 package information MiniSO8 package information QFN16 3x3 package information Revision history /34 DocID25994 Rev 1

3 Package pin connections 1 Package pin connections Figure 1. Pin connections for each package (top view) SC7-5 DFN8 2x2 MiniSO8 QFN16 3x3 1. The exposed pads of the DFN8 2x2 and the QFN16 3x3 can be connected to VCC- or left floating. DocID25994 Rev 1 3/34 34

4 Absolute maximum ratings and operating conditions 2 Absolute maximum ratings and operating conditions Table 2. Absolute maximum ratings (AMR) Symbol Parameter Value Unit V cc Supply voltage (1) 6 V id Differential input voltage (2) ±V cc V V in Input voltage (3) V cc- -.2 to V cc+ +.2 I in Input current (4) 1 ma T stg Storage temperature -65 to +15 C Thermal resistance junction-to-ambient (5)(6) SC7-5 5 R thja DFN8 2x2 57 C/W MiniSO8 19 QFN16 3x3 39 T j Maximum junction temperature 15 C ESD HBM: human body model, OA1ZHA only (7) 4 kv MM: machine model, OA1ZHA only (8) 3 V CDM: charged device model 1.5 CDM: charged device model, QFN16 3x3 TBD kv Latch-up immunity ma 1. All voltage values, except differential voltage, are with respect to network ground terminal. 2. The differential voltage is the non-inverting input terminal with respect to the inverting input terminal. 3. V cc - V in must not exceed 6 V, V in must not exceed 6 V. 4. Input current must be limited by a resistor in series with the inputs. 5. Short-circuits can cause excessive heating and destructive dissipation. 6. R th are typical values. 7. Human body model: 1 pf discharged through a 1.5 kresistor between two pins of the device, done for all couples of pin combinations with other pins floating. 8. Machine model: a pf cap is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5 ), done for all couples of pin combinations with other pins floating. Table 3. Operating conditions Symbol Parameter Value Unit V cc Supply voltage 1.8 to 5.5 V icm Common mode input voltage range V cc- -.1 to V cc+ +.1 V T oper Operating free air temperature range - to +125 C 4/34 DocID25994 Rev 1

5 Electrical characteristics 3 Electrical characteristics V CC + = 1.8 V with V CC - = V, V icm = V CC /2, T = 25 C, and R L = 1 k connected to V CC /2 (unless otherwise specified) Table 4. Electrical characteristics Symbol Parameter Conditions Min. Typ. Max. Unit DC performance V io Input offset voltage T = 25 C C < T< 125 C 8 V io /T Input offset voltage drift (1) - C < T< 125 C 1 3 nv/ C I ib Input bias current (V out = V CC /2) I io Input offset current (V out = V CC /2) CMR A vd V OH V OL I out I CC AC performance GBP Common mode rejection ratio log (V icm /V io ), V ic = V to V CC, V out = V CC /2, R L > 1 M Large signal voltage gain V out =.5 V to (V cc -.5 V) High level output voltage Low level output voltage I sink (V out = V CC) I source (V out = V) Supply current (per channel, V out = V CC /2, R L > 1 M Gain bandwidth product T = 25 C 5 (2) - C < T< 125 C 3 (2) T = 25 C 1 (2) - C < T< 125 C 6 (2) T = 25 C C < T< 125 C 11 T = 25 C C < T< 125 C 11 T = 25 C 3 - C < T< 125 C 7 T = 25 C 3 - C < T< 125 C 7 T = 25 C C < T< 125 C 6 T = 25 C C < T< 125 C 4 T = 25 C 28 - C < T< 125 C F u Unity gain frequency 3 m Phase margin R L = 1 k, C L = 1 pf 55 degrees G m Gain margin 17 db SR Slew rate (3).17 V/s t s Settling time To.1%, V in = 1 Vp-p, R L = 1 k, C L = 1 pf V pa db mv ma µa khz 5 µs DocID25994 Rev 1 5/34 34

6 Electrical characteristics Table 4. Electrical characteristics (continued) Symbol Parameter Conditions Min. Typ. Max. Unit e n Equivalent input noise voltage f = 1 khz f = 1 khz 6 6 nv Hz C s Channel separation f = 1 Hz 1 db t init Initialization time T = 25 C 5 - C < T< 125 C 1 s 1. See Section 4.5: Input offset voltage drift over temperature. Input offset measurements are performed on x1 gain configuration. The amplifiers and the gain setting resistors are at the same temperature. 2. Guaranteed by design. 3. Slew rate value is calculated as the average between positive and negative slew rates. 6/34 DocID25994 Rev 1

7 Electrical characteristics V CC + = 3.3 V with V CC - = V, V icm = V CC /2, T = 25 C, and R L = 1 k connected to V CC /2 (unless otherwise specified) Table 5. Electrical characteristics Symbol Parameter Conditions Min. Typ. Max. Unit DC performance V io Input offset voltage T = 25 C C < T< 125 C 8 V io /T Input offset voltage drift (1) - C < T< 125 C 1 3 nv/ C I ib I io CMR A vd V OH V OL Input bias current (V out = V CC /2) Input offset current (V out = V CC /2) Common mode rejection ratio log (V icm /V io ) V ic = V to V CC, V out = V CC /2 R L > 1 M Large signal voltage gain V out =.5 V to (V cc -.5 V) High level output voltage Low level output voltage I out I sink (V out = V CC ) I CC AC performance GBP I source (V out = V) Supply current (per channel, V out = V CC /2, R L > 1 M Gain bandwidth product T = 25 C 6 (2) - C < T< 125 C 3 (2) T = 25 C 1 (2) - C < T< 125 C 6 (2) T = 25 C C < T< 125 C 115 T = 25 C C < T< 125 C 11 T = 25 C 3 - C < T< 125 C 7 T = 25 C 3 - C < T< 125 C 7 T = 25 C C < T< 125 C 12 T = 25 C C < T< 125 C 1 T = 25 C 29 - C < T< 125 C F u Unity gain frequency 3 m Phase margin R L = 1 k, C L = 1 pf 56 degrees G m Gain margin 19 db SR Slew rate (3).19 V/s t s Settling time To.1%, V in = 1 Vp-p, R L = 1 k, C L = 1 pf V pa db mv ma A khz 5 s DocID25994 Rev 1 7/34 34

8 Electrical characteristics Table 5. Electrical characteristics (continued) Symbol Parameter Conditions Min. Typ. Max. Unit e n Equivalent input noise voltage f = 1 khz f = 1 khz nv Hz C s Channel separation f = 1 Hz 1 db t init Initialization time T = 25 C 5 - C < T< 125 C 1 s 1. See Section 4.5: Input offset voltage drift over temperature. Input offset measurements are performed on x1 gain configuration. The amplifiers and the gain setting resistors are at the same temperature. 2. Guaranteed by design. 3. Slew rate value is calculated as the average between positive and negative slew rates. 8/34 DocID25994 Rev 1

9 Electrical characteristics V CC + = 5 V with V CC - = V, V icm = V CC /2, T = 25 C, and R L = 1 k connected to V CC /2 (unless otherwise specified) Table 6. Electrical characteristics Symbol Parameter Conditions Min. Typ. Max. Unit DC performance V io Input offset voltage T = 25 C C < T< 125 C 8 V io /T Input offset voltage drift (1) - C < T< 125 C 1 3 nv/ C I ib I io CMR SVR A vd EMIRR (3) V OH V OL Input bias current (V out = V CC/ /2) Input offset current (V out = V CC/ 2) Common mode rejection ratio log (V icm /V io ) V ic = V to V CC/, V out = V CC/ /2 R L > 1 M Supply voltage rejection ratio log (V CC/ /V io ) V CC/ = 1.8 to 5.5 V, V out = V CC/ /2, R L > 1 M Large signal voltage gain V out =.5 V to (V cc -.5 V) EMI rejection ratio EMIRR = - log (V RFpeak /V io ) High level output voltage Low level output voltage I out I sink (V out = V CC/ ) I CC I source (V out = V) Supply current (per channel, V out = V CC/ /2, R L > 1 M T = 25 C 7 (2) - C < T< 125 C 3 (2) T = 25 C 1 (2) - C < T< 125 C 6 (2) T = 25 C C < T< 125 C 115 T = 25 C C < T< 125 C 1 T = 25 C C < T< 125 C 11 V RF = 1 mv p, f = MHz 84 V RF = 1 mv p, f = 9 MHz 87 V RF = 1 mv p, f = 18 MHz 9 V RF = 1 mv p, f = MHz 91 T = 25 C 3 - C < T< 125 C 7 T = 25 C 3 - C < T< 125 C 7 T = 25 C C < T< 125 C 14 T = 25 C C < T< 125 C 12 T = 25 C 31 - C < T< 125 C V pa db db mv ma A DocID25994 Rev 1 9/34 34

10 Electrical characteristics AC performance GBP Gain bandwidth product R L = 1 k, C L = 1 pf F u Unity gain frequency 3 m Phase margin 53 degrees G m Gain margin R L = 1 k, C L = 1 pf 19 db SR Slew rate (4).19 V/s t s e n Settling time Equivalent input noise voltage Table 6. Electrical characteristics (continued) Symbol Parameter Conditions Min. Typ. Max. Unit To.1%, V in = 1 mvp-p, R L = 1 k, C L = 1 pf f = 1 khz f = 1 khz khz 1 s C s Channel separation f = 1 Hz 1 db nv Hz t init Initialization time T = 25 C 5 - C < T< 125 C 1 s 1. See Section 4.5: Input offset voltage drift over temperature. Input offset measurements are performed on x1 gain configuration. The amplifiers and the gain setting resistors are at the same temperature. 2. Guaranteed by design. 3. Tested on SC-7 package 4. Slew rate value is calculated as the average between positive and negative slew rates. 1/34 DocID25994 Rev 1

11 Electrical characteristics Figure 2. Supply current vs. supply voltage Supply Current (µa) T=- C T=125 C 5 V ICM =V CC / Supply voltage (V) Population Figure 3. Input offset voltage distribution at V CC = 5 V Vcc=5V, Vicm=2.5V Input offset voltage (µv) Figure 4. Input offset voltage distribution at V CC = 3.3 V 6 Figure 5. Input offset voltage distribution at V CC = 1.8 V 6 5 Vcc=3.3V, Vicm=1.65V 5 Vcc=1.8V, Vicm=.6V Population 3 Population Input offset voltage (µv) Input offset voltage (µv) Figure 6. Vio temperature co-efficient distribution (- C to 25 C) Figure 7. Vio temperature co-efficient distribution (25 C to 125 C) T=- C to 25 C Vcc=5V, Vicm=2.5V 5 to 125 C Vcc=5V, Vicm=2.5V Population 3 Population Input offset voltage drift [µv/ C] Input offset voltage drift [µv/ C] DocID25994 Rev 1 11/34 34

12 Electrical characteristics Figure 8. Input offset voltage vs. supply voltage Figure 9. Input offset voltage vs. input common mode at V CC = 1.8 V T=125 C 3 2 T=125 C Vio (µv) T=- C Vio (µv) T=- C Vicm=Vcc/2-4 Vcc=1.8V Vcc(V) Vicm (V) Figure 1. Input offset voltage vs. input common mode at V CC = 2.7 V Figure 11. Input offset voltage vs. input common mode at V CC = 5.5 V Vio (µv) T=- C T=125 C Vcc=2.7V Vicm (V) Vio (µv) T=125 C T=- C Vcc=5.5V Vicm (V) Figure 12. Input offset voltage vs. temperature Figure 13. V OH vs. supply voltage Output swing (mv from Vcc+) T=125 C T=- C Rl=1k Vicm=Vcc/ Vcc (V) 12/34 DocID25994 Rev 1

13 Electrical characteristics Figure 14. V OL vs. supply voltage Figure 15. Output current vs. output voltage at V CC = 1.8 V 3 Output swing (mv from Vcc-) T=125 C T=- C Rl=1k Vicm=Vcc/ Vcc (V) Output Current (ma) T=- C T=125 C T=- C T=125 C Vcc=1.8V Output Voltage (V) Figure 16. Output current vs. output voltage at V CC = 5.5 V 3 Figure 17. Input bias current vs. common mode at V CC = 5 V 1 Output Current (ma) 1-1 T=- C T=125 C T=125 C IiB (pa) IiBp IiBn - T=- C Vcc=5.5V Output Voltage (V) -75 Vcc=5V Common Mode Voltage (V) Figure 18. Input bias current vs. common mode at V CC = 1.8 V 1 75 Figure 19. Input bias current vs. temperature at V CC = 5 V IiBp 5 25 IiBp IiB (pa) -25 IiBn IiB (pa) IiBn Vcc=1.8V Common Mode Voltage (V) Vcc=5V Temperature ( C) DocID25994 Rev 1 13/34 34

14 Electrical characteristics Figure. Bode diagram at V CC = 1.8 V Figure 21. Bode diagram at V CC = 2.7 V T=- C Gain 15 T=- C Gain 15 Gain (db) T=125 C Phase ( ) Gain (db) T=125 C Phase ( ) - Phase -1 - Phase -1 - Vcc=1.8V, Vicm=.9V, G=-1 Rl=1k, Cl=1pF, Vrl=Vcc/ Vcc=2.7V, Vicm=1.35V, G=-1 Rl=1k, Cl=1pF, Vrl=Vcc/ Frequency (khz) Frequency (khz) Figure 22. Bode diagram at V CC = 5.5 V Figure 23. Open loop gain vs. frequency T=- C Gain 15 8 Phase 8 Gain (db) - Phase T=125 C Phase ( ) Gain (db) 6 Gain 6 Phase ( ) - Vcc=5.5V, Vicm=2.75V, G=-1 Rl=1k, Cl=1pF, Vrl=Vcc/ Frequency (khz) Vcc=5V, Vicm=2.5V, Rl=1k, Cl=1pF Frequency (khz) Figure 24. Positive slew rate vs. supply voltage Figure 25. Negative slew rate vs. supply voltage.3. Positive Slew Rate (V/µs).2.1. T=- C T=125 C Rl=1k, Cl=1pF Vin: from.3v to Vcc-.3V SR calculated from 1% to 9% Supply Voltage (V) Negative Slew Rate (V/µs) T=- C T=125 C Rl=1k, Cl=1pF Vin: from Vcc-.3V to.3v SR calculated from 1% to 9% Supply Voltage (V) 14/34 DocID25994 Rev 1

15 Electrical characteristics Figure Hz to 1 Hz noise Figure 27. Noise vs. frequency noise density (nv/(hz)) Vcc = 5.5V Vicm=Vcc/2 Noise.1Hz_1Hz equivalent to.2 µvpp 1 1m 1 1 Frequency (Hz) Equivalent Input Voltage Noise (nv/hz) Vcc=3.3V Vcc=5.5V Vcc=1.8V Vicm=Vcc/2 Tamb=25 C 1 1k 1k Frequency (Hz) Figure 28. Noise vs. frequency and temperature Figure 29. Output overshoot vs. load capacitance Equivalent Input Voltage Noise (nv/hz) Vicm=Vcc/2 Vcc=5.5V 25 C 125 C - C 1 1k 1k Frequency (Hz) Overshoot (%) Vcc=5.5V, 5 1mVpp, Rl=1k Load capacitance (pf).1 Figure 3. Small signal Figure 31. Large signal.5 2. Output Voltage (V). -.5 Vcc = 5.5V Rl=1k Cl=1pF Output Voltage (V). -2. Vcc = 5.5V Rl=1k Cl=1pF Time (µs) Time (µs) DocID25994 Rev 1 15/34 34

16 Electrical characteristics Vout (V) Figure 32. Positive overvoltage recovery at V CC = 1.8 V Vin Vout Vcc=1.8V, Vicm=.9V, G=11 Rl=1k, Cl=1pF µ -5µ 5µ 1µ 15µ µ 25µ 3µ 35µ µ Time (s) Figure 34. Negative overvoltage recovery at V CC = 1.8 V 1.. Vin (V) Figure 33. Positive overvoltage recovery at V CC = 5 V Vout (V) Vin Vout Vcc=5.5V, Vicm=2.75V, G=11 Rl=1k, Cl=1pF µ -5µ 5µ 1µ 15µ µ 25µ 3µ 35µ µ Time (s) Figure 35. Negative overvoltage recovery at V CC = 5 V 3.. Vin (V) Vin Vout Vin Vout.1.5 Vout (V) Vin (V) Vout (V) Vin (V) Vcc=1.8V, Vicm=.9V, G= Rl=1k, Cl=1pF µ -5µ 5µ 1µ 15µ µ 25µ 3µ 35µ µ Time (s) -.5 Vcc=5.5V, Vicm=2.75V, G= Rl=1k, Cl=1pF µ -5µ 5µ 1µ 15µ µ 25µ 3µ 35µ µ Time (s) Figure 36. PSRR vs. frequency Figure 37. Output impedance vs. frequency PSRR (db) PSRR +PSRR Vcc=5.5V, Vicm=2.75V, G=1 Rl=1k, Cl=1pF, Vripple=1mVpp Frequency (Hz) Output Impedance () Vcc=2.7V to 5.5V Osc level=3mv RMS G=1 Ta=25C 1 1k 1k 1k 1M Frequency (Hz) 16/34 DocID25994 Rev 1

17 Application information 4 Application information 4.1 Operation theory The OA1ZHA, OA2ZHA and OA4ZHA are high precision CMOS op amp. They achieve a low offset drift and no 1/f noise thanks to their chopper architecture. Chopper-stabilized amps constantly correct low-frequency errors across the inputs of the amplifier. Chopper-stabilized amplifiers can be explained with respect to: Time domain Frequency domain Time domain The basis of the chopper amplifier is realized in two steps. These steps are synchronized thanks to a clock running at khz. Figure 38. Block diagram in the time domain (step 1) Figure 39. Block diagram in the time domain (step 2) Figure 38 shows step 1, the first clock cycle, where V io is amplified in the normal way. Figure 39 shows step 2, the second clock cycle, where Chop1 and Chop2 swap paths. At this time, the V io is amplified in a reverse way as compared to step 1. At the end of these two steps, the average V io is close to zero. The A2(f) amplifier has a small impact on the V io because the V io is expressed as the input offset and is consequently divided by A1(f). DocID25994 Rev 1 17/34 34

18 Application information In the time domain, the offset part of the output signal before filtering is shown in Figure. Figure. V io cancellation principle The low pass filter averages the output value resulting in the cancellation of the V io offset. The 1/f noise can be considered as an offset in low frequency and it is canceled like the V io, thanks to the chopper technique Frequency domain The frequency domain gives a more accurate vision of chopper-stabilized amplifier architecture. Figure 41. Block diagram in the frequency domain The modulation technique transposes the signal to a higher frequency where there is no 1/f noise, and demodulate it back after amplification. 1. According to Figure 41, the input signal V in is modulated once (Chop1) so all the input signal is transposed to the high frequency domain. 2. The amplifier adds its own error (V io (output offset voltage) + the noise V n (1/f noise)) to this modulated signal. 3. This signal is then demodulated (Chop2), but since the noise and the offset are modulated only once, they are transposed to the high frequency, leaving the output signal of the amplifier without any offset and low frequency noise. Consequently, the input signal is amplified with a very low offset and 1/f noise. 4. To get rid of the high frequency part of the output signal (which is useless) a low pass filter is implemented. To further suppress the remaining ripple down to a desired level, another low pass filter may be added externally on the output of the OA1ZHA, OA2ZHA and OA4ZHA device. 18/34 DocID25994 Rev 1

19 Application information 4.2 Operating voltages OA1ZHA, OA2ZHA and OA4ZHA CMOS op amp can operate from 1.8 to 5.5 V. The parameters are fully specified for 1.8 V, 3.3 V, and 5 V power supplies. However, the parameters are very stable in the full V CC range and several characterization curves show the OA1ZHA, OA2ZHA and OA4ZHA op amp characteristics at 1.8 V and 5.5 V. Additionally, the main specifications are guaranteed in extended temperature ranges from - to +125 C. 4.3 Input pin voltage ranges OA1ZHA, OA2ZHA and OA4ZHA CMOS op amp can operate from 1.8 to 5.5 V. The parameters are fully specified for 1.8 V, 3.3 V, an have internal ESD diode protection on the inputs. These diodes are connected between the input and each supply rail to protect the input MOSFETs from electrical discharge. If the input pin voltage exceeds the power supply by.5 V, the ESD diodes become conductive and excessive current can flow through them. Without limitation this over current can damage the device. In this case, it is important to limit the current to 1 ma, by adding resistance on the input pin, as described in Figure 42. Figure 42. Input current limitation 4.4 Rail-to-rail input OA1ZHA, OA2ZHA and OA4ZHA CMOS op amp have a rail-to-rail input, and the input common mode range is extended from V CC- -.1 V to V CC+ +.1 V. DocID25994 Rev 1 19/34 34

20 Application information 4.5 Input offset voltage drift over temperature The maximum input voltage drift variation over temperature is defined as the offset variation related to the offset value measured at 25 C. The operational amplifier is one of the main circuits of the signal conditioning chain, and the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 C can be compensated during production at application level. The maximum input voltage drift over temperature enables the system designer to anticipate the effect of temperature variations. The maximum input voltage drift over temperature is computed using Equation 1. Equation 1 V io = max V io T V io 25C T T 25C where T = - C and 125 C. The OA1ZHA, OA2ZHA and OA4ZHA CMOS datasheet maximum value is guaranteed by measurements on a representative sample size ensuring a C pk (process capability index) greater than Rail-to-rail output The operational amplifier output levels can go close to the rails: to a maximum of 3 mv above and below the rail when connected to a 1 k resistive load to V CC / Capacitive load Driving large capacitive loads can cause stability problems. Increasing the load capacitance produces gain peaking in the frequency response, with overshoot and ringing in the step response. It is usually considered that with a gain peaking higher than 2.3 db an op amp might become unstable. Generally, the unity gain configuration is the worst case for stability and the ability to drive large capacitive loads. Figure 43 and Figure 44 show the serial resistor that must be added to the output, to make a system stable. Figure 45 shows the test configuration using an isolation resistor, R iso. /34 DocID25994 Rev 1

21 Application information Figure 43. Stability criteria with a serial resistor at V DD = 5 V 1 Stable Figure 44. Stability criteria with a serial resistor at V DD = 1.8 V 1 Stable Serial Resistor (Ohm) 1 1 Unstable Serial Resistor (Ohm) 1 1 Unstable 1 Vcc=5V, Vicm=2.5V,, Rl=1 k, G= , Capacitive Load (nf) 1 Vcc=1.8V, Vicm=.9V,, Rl=1 k, G= , Capacitive Load (nf) Figure 45. Test configuration for R iso 4.8 PCB layout recommendations Particular attention must be paid to the layout of the PCB, tracks connected to the amplifier, load, and power supply. The power and ground traces are critical as they must provide adequate energy and grounding for all circuits. Good practice is to use short and wide PCB traces to minimize voltage drops and parasitic inductance. In addition, to minimize parasitic impedance over the entire surface, a multi-via technique that connects the bottom and top layer ground planes together in many locations is often used. The copper traces that connect the output pins to the load and supply pins should be as wide as possible to minimize trace resistance. DocID25994 Rev 1 21/34 34

22 Application information 4.9 Optimized application recommendation OA1ZHA, OA2ZHA and OA4ZHA CMOS op amp are based on chopper architecture. As they are switched devices, it is strongly recommended to place a.1 F capacitor as close as possible to the supply pins. A good decoupling has several advantages for an application. First, it helps to reduce electromagnetic interference. Due to the modulation of the chopper, the decoupling capacitance also helps to reject the small ripple that may appear on the output. OA1ZHA, OA2ZHA and OA4ZHA CMOS op amp have been optimized for use with 1 k in the feedback loop. With this, or a higher value of resistance, these devices offer the best performance. 4.1 EMI rejection ration (EMIRR) The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational amplifiers. An adverse effect that is common to many op amp is a change in the offset voltage as a result of RF signal rectification. OA1ZHA, OA2ZHA and OA4ZHA CMOS op amp have been specially designed to minimize susceptibility to EMIRR and show an extremely good sensitivity. Figure 46 shows the EMIRR IN+ of the OA1ZHA, OA2ZHA and OA4ZHA measured from 1 MHz up to 2.4 GHz. Figure 46. EMIRR on IN+ pin 1 1 EMIRR In+(dB) 8 6 Vcc=5.5V, G=1 Prf=-1dBm Frequency (MHz) 22/34 DocID25994 Rev 1

23 Application information 4.11 Application examples Oxygen sensor The electrochemical sensor creates a current proportional to the concentration of the gas being measured. This current is converted into voltage thanks to R resistance. This voltage is then amplified by OA1ZHA, OA2ZHA and OA4ZHA CMOS op amp (see Figure 47). Figure 47. Oxygen sensor principle schematic The output voltage is calculated using Equation 2: Equation 2 V out R 2 = I R V io R 1 As the current delivered by the O2 sensor is extremely low, the impact of the V io can become significant with a traditional operational amplifier. The use of the chopper amplifier of the OA1ZHA, OA2ZHA and OA4ZHA is perfect for this application. In addition, using OA1ZHA, OA2ZHA and OA4ZHA op amp for the O2 sensor application ensures that the measurement of O2 concentration is stable even at different temperature thanks to a very good V io /T. DocID25994 Rev 1 23/34 34

24 Application information Precision instrumentation amplifier The instrumentation amplifier uses three op amp. The circuit, shown in Figure 48, exhibits high input impedance, so that the source impedance of the connected sensor has no impact on the amplification. Figure 48. Precision instrumentation amplifier schematic The gain is set by tuning the R g resistor. With R1 = R2 and R3 = R4, the output is given by Equation 3. Equation 3 V out = V 2 V 1 R 4 2R f R 2 R g The matching of R1, R2 and R3, R4 is important to ensure a good common mode rejection ratio (CMR). 24/34 DocID25994 Rev 1

25 Application information Low-side current sensing Power management mechanisms are found in most electronic systems. Current sensing is useful for protecting applications. The low-side current sensing method consists of placing a sense resistor between the load and the circuit ground. The resulting voltage drop is amplified using OA1ZHA, OA2ZHA and OA4ZHA CMOS op amp (see Figure 49). Figure 49. Low-side current sensing schematic V out can be expressed as follows: Equation 4 R g2 R g2 R f2 V out R shunt I R f R g2 R f2 = + I + p I + n R f1 V io R g1 R g2 R f2 R f1 R g1 R f1 R g1 Assuming that R f2 = R f1 = R f and R g2 = R g1 = R g, Equation 4 can be simplified as follows: Equation 5 R f V out = R shunt I V io R f I io R g R f R g The main advantage of using the chopper of the OA1ZHA, OA2ZHA and OA4ZHA, for a low-side current sensing, is that the errors due to V io and I io are extremely low and may be neglected. Therefore, for the same accuracy, the shunt resistor can be chosen with a lower value, resulting in lower power dissipation, lower drop in the ground path, and lower cost. Particular attention must be paid on the matching and precision of R g1, R g2, R f1, and R f2, to maximize the accuracy of the measurement. DocID25994 Rev 1 25/34 34

26 Package information 5 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK is an ST trademark. 26/34 DocID25994 Rev 1

27 Package information 5.1 SC7-5 package information Figure 5. SC7-5 package mechanical drawing DIMENSIONS IN MM SIDE VIEW GAUGE PLANE COPLANAR LEADS SEATING PLANE TOP VIEW Symbol Table 7. SC7-5 package mechanical data Millimeters Dimensions Inches Min. Typ. Max. Min. Typ. Max. A A1.1.4 A b c D E E e e L < 8 8 DocID25994 Rev 1 27/34 34

28 Package information 5.2 DFN8 2x2 package information Figure 51. DFN8 2x2 package mechanical drawing Table 8. DFN8 2x2x.6 mm package mechanical data (pitch.5 mm) Dimensions Symbol Millimeters Inches Min. Typ. Max. Min. Typ. Max. A A1.5.2 A b D D E E e.5. L ddd /34 DocID25994 Rev 1

29 Package information Figure 52. DFN8 2x2 footprint recommendation DocID25994 Rev 1 29/34 34

30 Package information 5.3 MiniSO8 package information Figure 53. MiniSO8 package mechanical drawing Table 9. MiniSO8 package mechanical data Dimensions Symbol Millimeters Inches Min. Typ. Max. Min. Typ. Max. A A A b c D E E e L L L k 8 8 ccc.1.4 3/34 DocID25994 Rev 1

31 Package information 5.4 QFN16 3x3 package information Figure 54. QFN16 3x3 package mechanical drawing DocID25994 Rev 1 31/34 34

32 Package information Table 1. QFN16 3 x 3 mm package mechanical data (pitch.5 mm) Dimensions Symbol Millimeters Inches Min. Typ. Max. Min. Typ. Max. A A1.5.2 A3..8 b D D E E e.5. L /34 DocID25994 Rev 1

33 Revision history 6 Revision history Table 11. Document revision history Date Revision Changes 4-Mar-14 1 Initial release. DocID25994 Rev 1 33/34 34

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