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1 ISSN , CODEN RUXUEW Journal of Software, Vol18, No7, July 2007, pp DOI: /jos Tel/Fax: by Journal of Software All rights reserved 2 1,2+, 1,2, 1 1, 1 (, ) 2 (, ) Hardware/Software Interface Design of Godson-2 Simultaneous Multithreading Processor LI Zu-Song 1,2+, XU Xian-Chao 1,2, HU Wei-Wu 1, TANG Zhi-Min 1 1 (Institute of Computing Technology, The Chinese Academy of Sciences, Beijing , China) 2 (Graduate University, The Chinese Academy of Sciences, Beijing , China) + Corresponding author: Phn: ext 9318, {lisoon,xuxianchao,hww,tang}@ictaccn Li ZS, Xu XC, Hu WW, Tang ZM Hardware/Software interface design of godson-2 simultaneous multithreading processor Journal of Software, 2007,18(7): htm Abstract: With the development of VLSI (very large scale integrated circuit) technology, a single chip can contain over one billion transistor Multithreading technique is the developing trend of high performance processor in the future How to design hardware/software interface has become a major problem for multithreading processor According to simultaneous multithreading processor requirement and the original Godson-2 architecture, the hardware/software interface for Godson-2 simultaneous multithreading processor is advanced and defined Based on this interface, the corresponding Linux for Godson-2 SMT (simultaneous multithreading) processor is designed and implemented on Linux 2420 The SPEC CPU2000 and some other benchmark programs are used to compare the performance of Godson-2 SMT processor with the superscalar processor The results show that the Godson-2 SMT processor designed with the interface can get a much better performance The hardware/software interface and operating system design in this paper are also very useful for the multi-core processor design Key words: Godson-2; simultaneous multithreading; microarchitecture; Linux operating system :,,,, 2,, Linux 2420 Supported by the National Natural Science Foundation of China for Distinguished Young Scholars under Grant No ( ); the National High-Tech Research and Development Plan of China under Grant Nos2002AA110010, 2005AA110010, 2005AA ( (863)); the National Basic Research Program of China under Grant No2005CB ( (973)); the Knowledge Innovation Program of the Chinese Academy of Sciences under Grant NoKGCX2-109 ( ); the Basic Research Foundation of the Institute of Computing Technology, the Chinese Academy of Sciences under Grant No ( ) Received ; Accepted

2 : SPEC CPU2000, 2, : 2 ; ; ;Linux : TP302 : A Linux PC, 2 [1] 64 RISC(reduced instruction set computing), CACHE (load speculation) (split read) 2 CPU 2000, CPU 2,,,,, (implicit multithreading) (explicit multithreading) [2],,,,,,, (simultaneous multithreading, SMT) [3 5], 2, :, ( );,,,, : ; , : 2,, CACHE, (program counter, PC), CACHE 2 1,,,

3 1808 Journal of Software Vol18, No7, July 2007 PC,, TLB(translation lookaside buffer) CP0,, CACHE CACHE BTB(branch target buffer) DTLB(data translation lookaside buffer),,,,,,,,,, 4 Reorder buffer Fetch Pre-Decode Decode Fix-Point register rename Floating- Point register rename Dispatch queue Fix-Point reservation station Floating- Point reservation station Fix-Point register file Floating- Point register file Fix-Point functional units Floating- Point functional units Memory management units Fig1 Microarchitecture of Godson-2 simultaneous multithreading processor ,,, 2 CPU, 2 : 2 (symmetrical multiprocessor, SMP) (SMT), CPU SMP 2, 2, CPU, Linux Intel Hyper-thread [6] SMT SMP, TLB CACHE :SMP CPU TLB CACHE; SMT CPU TLB CACHE,SMT SMP TLB CACHE SMT,,, SMT,, SMT, SMP : 1) 2,, SMT, 2, 2 CPU 2) SMT, 2,SMT,,,,, CPU,

4 : CPU, 2 CPU CPU,, CPU CPU 3) CPU SMT, CPU, CPU, CPU, CPU, CPU,SMT CPU CPU 4),SMT, CPU,, CPU, CPU ll/sc, 2 ll/sc,, 3 SMT, 4 2 SMT, 31 SMT, 2, CPU 2 modech imm,crt a1 kill :modech imm imm,0,3 ;crt a1 CPU, a1 ; kill CPU 2 CPU, CPU, CPU, 2,: CPU,, ; CPU, SMT, 2 la a1, second_start_pc modech 3 crt a1 Fig2 Mode switch example codes 2,modech 3, CPU, CPU,, CPU, crt ;crt CPU,, 2 CPU kill, CPU, 1 CPU modech 0, 2

5 1810 Journal of Software Vol18, No7, July , : 1), CPU 2) 1 CPU, CPU 1 : CPU, CPU,,,,,,Intel, 2, 1 CPU : 1 CPU,,,, 2 2, 1 CPU, CPU,,, ; 2, 2 CPU, 2 CPU, count compare count 1, count compare, 2 CPU 33 CPU SMP,CPU CPU 2 CPU CPU CPU, 2 CPU CPU 1) CPU SMP, CPU 4 :RESCHEDULE,SMP_ FUNCTION,STOP,INVALIDATE_TLB, : RESCHEDULE CPU CPU CPU, CPU,, CPU RESCHEDULE,, ; SMP_FUNCTION CPU CPU, CPU CPU, CPU ; STOP CPU CPU,, CPU, ; INVALIDATE_TLB CPU TLB :, CPU TLB, CPU, TLB

6 : ) 2 CPU 2 CPU CPU, CPU CPU, CPU 2 CPU : 3, CPU CPU CPU CPU CPU, ; CPU, CPU CPU 1, CPU CPU, ;, CPU CPU CPU, CPU CPU Interrupt Interrupt CPU0 interrupt control register Interrupt bits Mask bits Interrupt bits Mask bits CPU1 interrupt control register CPU0 CPU1 Fig3 Message passing mechanism in Godson-2 simultaneous multithreading processor 3 2 CPU CPU, CPU CPU, 2 mtc0_t a1,a2 mfc0_t a1,a2 CPU mtc0 a1,a2,mfc0 a1,a2, mtc0_t a1,a2 mfc0_t a1,a2 CPU CP0 CPU, mfc0_t CPU CPU,, mtc0_t CPU CPU, CPU, : CPU CPU, CPU CPU,, CPU, CPU, CPU 34, Linux, 2 Linux : 1,Linux up/down, down :,, ;,,, 2 Linux,,Linux spin_lock SMP SMT CPU

7 1812 Journal of Software Vol18, No7, July 2007, Linux, spin_lock, CPU, SMT, down spin_lock 0,,, 3,, ll/sc :, ll,ll llbit,, sc sc llbit, llbit 0,sc ll sc,,llbit 0 2,,, llbit, CPU, SMT, acquire/release/try_acquire [7],,,,acquire, RICS, 2, ll/sc, llbit 0,, wait a1, acquire/release/try_acquire Spin_lock 4, wait, 1: ll a1,offset (base) blez a1,2f sub a1,1 sc a1,offset (base) beqz a1,1b nop bneqz a1,3f nop lui a1,0xffff 2: wait a1 bal 1b 3: Fig4 Spin_lock example codes 4 Spin_lock 4 2 2, 2, 2 CPU SMP, SMP, 2 2 SMP, 2 Linux SMP,,, Linux, SMP 2 Linux SMP CPU, 2 Linux

8 : Linux SMP :(1) Linux CPU, CPU, CPU, CPU, ;(2) Linux CPU, CPU;(3) Linux, ;(4) CPU CPU,, CPU,Linux CPU CPULinux CPU, CPU, Linux SMP,, 3, Linux 2 3 1) Linux SMP, 2 Linux SMP 5 Setup_arch () Initialize some kernel functions and data structures Parse_options () CPU_probe () Check CPU type Prom_init () Get the parameters supplied by bios Load_mmu () Initialize the memory-related functions according to the CPU type Start_kernel () The common initialization entry Arch/mips/kernel/Heads The first kernel instructions Init_arch () Arch/mips/setupc Start_kernel () Init/mainc Trap_init () Initialize the trap handlers Init_IRQ () Initialize the IRQ handlers and enable the interrupt of some devices Sched_init () Initialize the data related with schedule Softirq_init () Initialize the data related with the soft irq Time_init () Enable the timer interrupt Console_init () Initialize the console Kmem_cache_init () etc Smp_init () Initialize the other CPUs Rest_init () Fig5 SMP initialization procedure in Linux 5 Linux SMP

9 1814 Journal of Software Vol18, No7, July 2007 init_arch(), Linux start_kernel() start_kernel() setup_arch(),, CPU, 2, 2, Linux-godson ( 2 Linux ), 2 CPU 2, CPU,, CPU Linux-godson, CPU CPU,start_kernel() sched_init(),mem_init(),,start_kernel() smp_init(), CPU, Linux smp_init(), smp_init() 6 smp_boot_cpus() CPU, CPU CPU, CPU, smp_commence(),linux SMP CPU, smp_boot_cpus() smp_commence(), Linux smp_commence(),, smp_boot_cpus() //init/mainc static void init smp_init (void) { /* Get other processors into their bootup holding patterns */ smp_boot_cpus(); wait_init_idle=cpu_online_map; clear_bit (current processor, &wait_init_idle); /* Don t wait me*/ smp_threads_ready=1; smp_commence(); /* Wait for the other cpus to set up their idle processes */ printk ( Waiting on wait_init_idle (map=0x%lx)\n,wait_init_idle); while (wait_init_idle) { cpu_relax(); barrier(); } printk( All processors have done init_idle\n ); } Fig6 The codes of smp_init function 6 Smp_init, 2 7 CPU IDLE,,smp_boot_cpus() 1, CPU CPU ;, 2 modech, crt CPU smp_bootstrap smp_bootstrap, CPU sp, start_secondary CPU, CPU CPU,

10 : , CPU smp_bootstrap CPU 1,, CPU CPU CPU, smp_init Smp_boot_cpus() 1 Create secondary CPU s idle process and malloc kernel stack for this idle process 2 Send kernel stack point and entry to secondary CPU and launch it CPU2 starts from smp_bootstrap Execute start_secondary and initualize CPU2 3 Wait until secondary CPU boots up Set booted signal 4 Build mapping of secondary CPU physical num to logical num Wait synchronization signal of main CPU and continue End Fig7 Initialization procedure of the secondary logic CPU of Godson-2 simultaneous multithreading processor 7 2 CPU 2) Linux spin_lock, Linux ll/sc 2, Linux, 3) CPU,Linux SMP CPU,, 1 2 CPU,, 1, CPU Linux Table 1 CPU message passing functions in Linux 1 Linux CPU Function smp_send_reschedule smp_call_function smp_send_stop Flush_tlb_all Flush_tlb_mm Flush_tlb_range Flush_tlb_page Description Send RESCHEDULE to other CPUs Send SMP_FUNCTION to other CPUs Send STOP to other CPUs Send INVALIDATE_TLB to other CPUs Send INVALIDATE_TLB to other CPUs Send INVALIDATE_TLB to other CPUs Send INVALIDATE_TLB to other CPUs 2 CPU, 19 ( CPU ), 19 :, CPU 23 CP0 ( CPU ), CPU, 23 CP0 CPU 2 CPU core_ipi_send() 8 mfc0_t mtc0_t CPU 23 CP0,, action

11 1816 Journal of Software Vol18, No7, July 2007 //arch/mips/kernel/smpc void core_send_ipi(int CPU, unsigned int action) { spin_lock(&smp_interrupt_lock); asm( set mips3\n\t mfc0_t k0,$23\n\t or k0,k0,%0\n\t mtc0_t k0,$23\n\t set mips0\n\t :: r (action) ); spin_unlock(&smp_interrupt_lock); } Fig8 Interrupt sending function for Godson-2 simultaneous multithreading processor 8 2 CPU 5 2 RTL(register transfer level) 2, Linux , 2 Linux, 9, IPC(instructions per cycle) 311%, 2 IPC Superscalar SMT Chat Eon+eon Twolf+twolf Crafty+crafty Art+art Eon+twolf Crafty+art Average Benchmark programs Fig9 Multi-Process benchmark performance of SMT, compared with superscalar processor 9 6, 2, 2 2 RTL,, Linux , SPEC CPU2000 Linux, CPU, 2 SMP,,

12 : ,, References: [1] Hu WW, Zhang FX, Li ZS Microarchitecture of the Godson-2 processor Journal of Computer Science and Technology, 2005,20(2): [2] Ungerer T, Robic B, Silc J Multithreaded processors The Computer Journal, 2002,45(3): [3] Tullsen DM, Eggers SJ, Levy HM Simultaneous multithreading: Maximizing on-chip parallelism In: Proc of the 22nd Annual Int l Symp on Computer Architecture New York: ACM Press, [4] Tullsen DM, Eggers SJ, Emer JS, Levy HM, Lo JL, Stamm RL Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor In: Proc of the 23rd Annual Int l Symp on Computer Architecture New York: ACM Press, [5] Eggers SJ, Emer JS, Levy HM, Lo JL, Stamm RL, Tullsen DM Simultaneous multithreading: A platform for next-generation processors IEEE Micro, 1997,17(5):12 19 [6] Marr DT, Binns F, Hill DL, Hinton G, Koufaty DA, Alan Miller J, Upton M Hyper-Threading technology architecture and microarchitecture Int l Technology Journal Q1, 2002,6(1):4 15 [7] Tullsen DM, Lo JL, Eggers SJ, Levy HM Supporting fine-grained synchronization on a simultaneous multithreading processor In: Proc of the 5th Annual Int l Symp on High-Performance Computer Architecture Washington: IEEE Computer Society, (1977 ),,,,,,VLSI (1968 ),,,,,CCF,,,VLSI (1979 ),,,, (1966 ),,,,,,

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2/80 2 2/80 2 3/80 3 DSP2400 is a high performance Digital Signal Processor (DSP) designed and developed by author s laboratory. It is designed for multimedia and wireless application. To develop application