Edge-Triggered Rising Edge-Triggered ( Falling Edge-Triggered ( Unit 11 Latches and Flip-Flops 3 Timing for D Flip-Flop (Falling-Edge Trigger) Unit 11

Latches and Flip-Flops 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop 11.6 J-K Flip-Flop 11.7 T Flip-Flop 11.8 Flip-Flops with additional Inputs Unit 11 Latches and Flip-Flops 1 Edge-Triggered D Flip-Flop Unit 11 Latches and Flip-Flops 2

Edge-Triggered Rising Edge-Triggered ( Falling Edge-Triggered ( Unit 11 Latches and Flip-Flops 3 Timing for D Flip-Flop (Falling-Edge Trigger) Unit 11 Latches and Flip-Flops 4

D Flip-Flop (Rising-Edge Trigger) Unit 11 Latches and Flip-Flops 5 Unit 11 Latches and Flip-Flops 6

Review Question (page 311) What change must be made to Figure 11-15(a) to implement a falling-edge triggered D flip-flop? Complete the following timing diagram for the modified flip-flop. Unit 11 Latches and Flip-Flops 7 Setup and Hold Times setup time ( ) hold time ( ) Unit 11 Latches and Flip-Flops 8

Determination of Minimum Clock Period inverter flip-flop setup time hold time flip-flop Unit 11 Latches and Flip-Flops 9 Determination of Minimum Clock Period (Cont d) flip-flop Unit 11 Latches and Flip-Flops 10

Latches and Flip-Flops 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop 11.6 J-K Flip-Flop 11.7 T Flip-Flop 11.8 Flip-Flops with additional Inputs Unit 11 Latches and Flip-Flops 11 S-R Flip-Flop Unit 11 Latches and Flip-Flops 12

S-R Flip-Flop implementation master slave S-R S-R flip-flop master slave master slave master slave master Unit 11 Latches and Flip-Flops 13 Timing for S-R Flip-Flop Unit 11 Latches and Flip-Flops 14

Review Question (page 311) A reset-dominant flip-flop behaves like an S-R flipflop, except that the input S=R=1 is allowed, and the flip-flop is reset when S=R=1. Derive the characteristic equation for a reset-dominant flipflop Show how a reset-dominant flip-flop can be constructed by adding gate(s) to an S-R flip-flop. Unit 11 Latches and Flip-Flops 15 Latches and Flip-Flops 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop 11.6 J-K Flip-Flop 11.7 T Flip-Flop 11.8 Flip-Flops with additional Inputs Unit 11 Latches and Flip-Flops 16

J-K Flip-Flop Unit 11 Latches and Flip-Flops 17 J-K Flip-Flop Timing Q changes on the rising edge Unit 11 Latches and Flip-Flops 18

Master-Slave J-K Flip-flop S-R latch master-slave J-K flip-flop master slave Unit 11 Latches and Flip-Flops 19 Review Question (page 311) Complete the following timing diagram for the flipflop of Figure 11-20(a). Unit 11 Latches and Flip-Flops 20

Latches and Flip-Flops 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop 11.6 J-K Flip-Flop 11.7 T Flip-Flop 11.8 Flip-Flops with additional Inputs Unit 11 Latches and Flip-Flops 21 T Flip-Flop toggle Unit 11 Latches and Flip-Flops 22

Timing Diagram for T Flip-flop falling edge trigger Unit 11 Latches and Flip-Flops 23 Implementation of T Flip-flop T flip-flop Unit 11 Latches and Flip-Flops 24

Latches and Flip-Flops 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop 11.6 J-K Flip-Flop 11.7 T Flip-Flop 11.8 Flip-Flops with additional Inputs Unit 11 Latches and Flip-Flops 25 Flip-Flops with additional Inputs clear (ClrN) and preset (PreN) Unit 11 Latches and Flip-Flops 26

Timing Diagram for D Flip-Flop with Asynchronous Clear and Preset Unit 11 Latches and Flip-Flops 27 Review Question (page 312) a) Complete the following timing diagram for a J-K flip-flop with a falling-edge trigger and asynchronous ClrN and PreN inputs. Unit 11 Latches and Flip-Flops 28

Review Question (page 312) b) Complete the timing diagram for the following circuit. Note that the Ck inputs on the two flip-flops are different. Unit 11 Latches and Flip-Flops 29 D Flip-Flop with Clock Enable (synchronous) Unit 11 Latches and Flip-Flops 30

Two Potential Problems Unit 11 Latches and Flip-Flops 31 D Flip-flop with Clock Enable D-CE flip-flop Q + =Q Q + =D Q + = QCE + DCE Unit 11 Latches and Flip-Flops 32

Review Question (page 312) Complete the following diagrams for the fallingedge triggered D-CE flip-flop of Figure 11-27(c). Assume Q begins at 1. a) First draw Q based on your understanding of the behavior of a D flip-flop with clock enable. b) Now draw the internal signal D from Figure 11-27(c), and confirm that this gives the same Q as in a). Unit 11 Latches and Flip-Flops 33 Summary ( ) next state next state Q + current state Q Q + gated D latch Q + latch D flip-flop Q + flip-flop Unit 11 Latches and Flip-Flops 34

Characteristic Equations latchesflip-flops Unit 11 Latches and Flip-Flops 35 Review Question (page 313) Covert by adding external: a) a D flip-flop to a J-K flip-flop. b) a T flip-flop to a D flip-flop. c) a T flip-flop to a D flip-flop with clock enable. Unit 11 Latches and Flip-Flops 36