Microsoft PowerPoint - IGZO-TFT(中山物理)-上網版

InGaZnO Thin Film Transistor Display InGaZnO- 薄膜電晶體平面顯示器張鼎張中山大學物理系

AM-LCD Structure

Electro-Optic Response of TN-LC Cell 6-bit => 64 voltage levels (262,000 colors) 8-bit => 256 voltage levels (16.7 million colors)

AMLCD (TFT-LCD)(Active Matrix ) 高解析度, 高反應速度, 高畫質

TFT-LCD Signal Driving Source Driver Gate Driver

顯示原理

Definition of Resolution 1-pixel including R,G,B 3 sub-pixels (or dots) 1-G-subpixel

E-paper displays High reflectivity High resolution. Low energy consumption. Thin, mobile and flexible displays.

Electrophoretic Displays 電子紙的顯示材料中, 又以軟性電泳顯示材料最被看好電泳意指在電場力量作用下造成物理移動現象, 使顯示介質呈現不同的色階因為其具低耗電量高對比度廣視角並可以自由捲曲等特點, 已成為電子紙材料的主流

Electrophoretic Displays Bendable clock Flexible newspaper newspaper

Electrowetting Display the change in solid/electrolyte contact angle due to an applied potential difference between the solid and the electrolyte

Electrowetting Display 主動式電濕潤顯示器彩色閱讀器

AM-OLED Active-Matrix Organic Light Emitting Diode

Structure & Cross Section of TFT-OLED 高分子材料一般對於電洞的傳遞速率都較對電子的傳遞速率快, 所以要提升效率必須在負極與發光層之間, 引進電子傳遞層, 以增加電子注入及傳導的效率電荷載子在不同層間的傳導性質, 可以決定發光的效率

Organic Light Emitting Diode Wide viewing angle Brightness and color OLED LCD Thickness Movement

OLED-Introduction 1. Self-emissive 2. Very thin form factor 3. High luminance 4. High luminous efficiency 5. High contrast 6. Fast response time 7. Wide viewing angle 8. Low power consumption 9. Wide temperature operation range 10. Potential of flexible substrate

Ability to supply current to OLED (>10 ma/cm 2 ) I ON = 5-10 ma (V GS < 10 V, V DS < 5 V) mobility > 10 cm 2 /V s

Comparison between PMOLED and AMOLED Column Driver Data Driver OLED panel Scan Driver Cathode Lines Row Driver Anode Lines (a) Passive matrix mode (b) Active matrix mode (PM-OLED) (AM-OLED or TFT-OLED)

Comparison between PMOLED and AMOLED Metal Electrode Organic Layer ITO Substrate (a) Passive matrix mode (PMOLED) Encapsulation TFT driver TFT driver TFT driver OLED OLED OLED (b) Active matrix mode (AMOLED or TFT- OLED)

MOSFET 金氧半場效電晶體 Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET) Gate ( 閘極 ) Al Source( 源極 ) n SiO 2 Drain( 汲極 ) n p 半導體 :N- 型 :Negative( 電子 ) P- 型 :Positive( 電洞 ) Si 基板

I D V G =3 V D V G =2 V G =1 V G =0 Gate ( 閘極 ) V D + Al Source( 源極 ) SiO Drain( 汲極 ) 2 n n p Si 基板

I D V G =3 V G =2 V G = 0.5 V V D V G =1 V G =0 Gate ( 閘極 ) 空乏區 V D + Al Source( 源極 ) SiO Drain( 汲極 ) 2 n n p Si 基板

I D V G =3 V G =2 V G = 1 V V D V G =1 V G =0 Gate ( 閘極 ) V D + Al Source( 源極 ) SiO Drain( 汲極 ) 2 n n p Si 基板 Inversion layer 反轉層

I D V G =3 V G =2 V G = 2 V V D V G =1 V G =0 Gate ( 閘極 ) V D + Al Source( 源極 ) SiO Drain( 汲極 ) 2 n ε n p Si 基板

I D V G =3 V G =2 V G = 3 V V D V G =1 V G =0 Gate ( 閘極 ) V D + Al Source( 源極 ) SiO Drain( 汲極 ) 2 n ε n p Si 基板 g m I V d g (Transconductsnce) 電晶體閘極控制能力

Transistor G G S D S D S D G a-si poly-si c-si Grain Boundar y Grain

Effect of TFT TFT LC Cap. Storage Cap. Voltage Source Use TFT as a switch to sample & hold voltage signal. When TFT is OFF, the voltage can be hold in the capacitors. The storage capacitor is used to depreciate the LC capacitance variation and also help to hold the voltage.

4 種典型 TFT 結構 Coplanar Inverted Coplanar Staggered Inverted Staggered

I-V V transfer characteristic Comparison Drain current [A] 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 Vds = 5 V Drain current 10-14 -10-5 0 5 10 15 Gate-source voltage [V] 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 Vds = 5 V -10-5 0 5 10 15 Gate-source voltage [V] Drain current 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 Vds = 5 V 10-14 -10-5 0 5 10 15 Gate-source voltage [V] Crystalline Polysilicon TFT Amorphous TFT

AMLCD Pixel-TFT Performance Requirements ACTIVE MATRIX EQUIVALENT CIRCUIT Ability to deliver ±5V to pixel V DS = 10 V I ON, I OFF requirements: VGA SXGA Charge time 32 s 15 s Pixel capacitance 1 pf 0.5 pf TFT drive current ~ 1 A ~ 1 A TFT leakage < 1 pa < 0.5 pa - I ON sufficient to charge C pixel within 1 line time V GS = 20 to 25 V - I OFF sufficient to maintain voltage on C pixel for 1 frame time C pixel Vpixel I leakage V pixel = 20 mv (6-bit gray scale) = 16.7 ms (60 Hz refresh rate)

Amorphous Structure Silicon thin film Grain Boundary Poly-Si Structure Grain

Aperture Ratio in a-si and p-si TFTs

TFT Technology Comparison AMORPHOUS SILICON low carrier mobility ( n <1 cm 2 /V s) separate IC drivers needed (TAB-IC pitch limited to ~150 ppi) low-temperature (<350 o C) process low-cost glass substrates POLYCRYSTALLINE SILICON higher mobilities ( n, p >30 cm 2 /V s) smaller pixel TFTs integration of driver circuitry high-temperature (>450 o C) process high-strain-point glass or quartz substrates

LTPS TFT-LCD LTPS display with integrated driver System on panel

Silicon Thin Film Amorphous Silicon Polycrystalline Silicon Grain Boundary Grain Merits Issue a-si TFT Good uniformity Low mobility (1cm 2 /Vs) Low cost process (4-5 mask) Sensitive to light & temperature 37 poly-si TFT High mobility (100cm 2 /Vs) Circuit integration High investment and process cost Non-uniformity issue

Comparison with Oxide TFT a-si TFT poly-si TFT Oxide TFT (IGZO) Uniformity Good Poor Good Mobility ~1cm 2 /Vs ~100cm 2 /Vs Circuit Integration 10~100cm 2 /V s No Yes Yes NO. of Mask 4~5 5~11 4~5 Cost/Yield Low/high High/low Low/high Process Temp. 150 ~ 350 o C 450 ~ 550 o C 150 ~ 350 o C

InGaZnO

It has been reported that the low-mobility a-si:h TFTs cannot drive larger LCDs (e.g. 55 inches) operating at high frame rates above 120 Hz; the required mobility will be even higher for displays with higher resolution, a faster frame rate and a larger panel size. 41

Advantages of Oxide TFT High mobility High speed/frequency Low operation voltage for portable devices Good transparency to visible light Lower density-of-states (DOS) compared to a-si Low temperature fabrication Flexible devices Roll-to-roll fabrication compatible Relatively low fabrication cost

ZnO-based oxide semiconductor for high mobility (IGZO TFT) ZnO TFTs ZnO thin film can be very easily crystallized during the deposition process, leading to the formation of grain boundary defects IGZO TFTs In :The conduction band of IGZO materials is closely related to the In 5s orbital, which has isotropic properties. Interestingly, the spherical symmetry of the 5s orbital makes the structural disordering no longer critical Ga : act as a carrier suppressor of the IZO conducting oxide and network stabilizer

O 2 pressure during the deposition

Novel multi-component oxide TFTs The Zr Hf or Sn atoms replacing the Ga atoms in the IGZO matrix were shown to act as a strong oxygen binder of the amorphous oxide network, leading to the improvement of the bias stability of the resulting TFTs (less carrier concentration). Hf-In-Zn Oxide (HIZO) Zr-In-Zn Oxide (ZIZO) Zinc indium tin oxide (ZISO)

Application of oxide TFTs into active matrix display Toppan Printing Inc. reported 4 full-color QVGA e-paper driven by IGZO TFTs on a PEN plastic substrate (2008) A full-color 6.5 flexible AMOLED on a plastic substrate was recently demonstrated by Samsung mobile displays (2009)

An IGZO-TFT driven 3.5 QCIF+ (176 220 pixels) AMOLED display was fabricated by LG Electronics Inc (2008) Samsung SDI reported the fabrication of a 12.1 WXGA AMOLED using sputtered IGZO TFTs on a glass substrate (2009) Park et al. reported a prototype transparent 2.5 AMOLED on a glass substrate, which is driven by ALD-deposited ZnO TFTs (2009)

Instability of a-igzo TFT Bias induced instability Temperature induced instability Ambient gas induced instability Light induced instability Process induced instability Structure induced instability (BCE Etching stopper Inverted coplanar) Passivation layer induced instability

Bias induced instability Charge trapping model: Normalized Drain Current (A) 10-4 10-5 Vg = 60 (0s) Vg = 60 (60s) 10-6 Vg = 60 (180s) 10-7 Vg = 60 (300s) Vg = 60 (600s) 10-8 Vg = 60 (1000s) 10-9 10-10 10-11 10-12 10-13 10-14 10-15 -15-10 -5 0 5 10 15 Gate Voltage (V) Vt shift (V) 12 10 8 6 4 2 passivation IGZO S oxide D G Glass substrate 60 V Experiment Simulation SiO2 a-igzo 200 400 600 8001000 Time (s)

Temperature induced instability 在高溫下進行閘極正偏壓操作會導致更多的載子被捕獲所以 Vt 飄移量會更多 Vt shift (V) 16 14 12 10 8 6 4 2 Experiment (295K) Experiment (318K) Experiment (333K) Experiment (348K) Experiment (363K) Fitting (295K) Fitting (318K) Fitting (333K) Fitting (348K) Fitting (363K) 200 400 600 800 1000 Time (s) S P B S SiO 2 PV IGZO oxide G Glass substrate Vg= 60 V Temperature: 295K 318K 333K 348K 363K D

Ambient gas induced instability (O 2 ) 氧氣吸附會與主動層之自由載子反應形成 O 2 - 進而減少其載子濃度導致 V T 向右偏移 O 2 760 torr Normalized Drain Current (A) 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 O2 desorption O 2 adsorption 100s O 2 adsorption 1000s O 2 adsorption 2000s O 2 adsorption 10800s O 2 adsorption induced positive Vt shift -15-10 -5 0 5 10 15 Gate Voltage (V)

Ambient gas induced instability (H 2 O) PBTS (Vg= 50 V, 85 ) 在水氣環境下操作元件會因為偏壓導致水氣吸附造成明顯之寄生電晶體現象 H2O induced parasitical transistor

Light induced instability passivation S IGZO oxide G Glass substrate D NID 10-6 Dark (STD) F Red (STD) F 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 R & G & B Green (STD) F Blue (STD) F 元件照光會在主動層產生電子電洞對, 造成光漏電流, 若照光的能量越大, 越容易激發電子產生更多電子電洞對, 因此漏電現象更嚴重 Under illumination -15-10 -5 0 5 10 15 VG

Passivation layer induced instability Normalized Drain Current (A) 10-4 10-5 10-6 Plasma damage during the deposition 10-7 process by PECVD 10-8 10-9 10-10 10-11 10-12 10-13 10-14 H doping and the plasma damage during the deposition process without PV with SiOx PV with SiON PV -15-10 -5 0 5 10 15 Gate Voltage (V)

Overview Dark Box, Cryogenic Probe Station and Measurement Instrument

Dark Box Inside Cascade Microtech M150 Triaxial Probe 4 for DC measure 6-in thermal chuck (RT~473K), enable to measure 12-in Si wafer

Pulse I-V measurement

Chamber Atmosphere Control Air Oxygen Nitrogen Vacuum Superconducting magnet (2T) Components Triaxial Probe 5 Optical Fiber 1 2-in triaxial chuck 4K~400K RT~600K Ceramic Probe

本實驗室 2010 IGZO-TFT paper list 1. Influence of positive bias stress on N 2 O plasma improved InGaZnO thin film transistor. Appl. Phys. Lett. 96, 242105 ( 2010) 2. Behaviors of InGaZnO thin film transistor under illuminated positive gate-bias stress. Appl. Phys. Lett. 97, 112104 (2010) 3. Light-induced instability of an InGaZnO thin film transistor with and without SiOx passivation layer formed by plasma-enhanced-chemicalvapor-deposition. Appl. Phys. Lett. 97, 192103 ( 2010) 4. Bias-induced oxygen adsorption in zinc tin oxide thin film transistors under dynamic stress. Appl. Phys. Lett. 96, 262104 ( 2010)

Behaviors of InGaZnO thin film transistor under illuminated positive gate-bias stress P B S P B I S SiO 2 PV SiO 2 PV S IGZO oxide G D S IGZO oxide G D Glass substrate Glass substrate Vg= 60 V Vg= 60V All the measurement are under darkness

1. 在照光環境下之閘極正偏壓劣化分析 Normalized Drain Current (A) Normalized Drain Current (A) 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-3 Vg = 60 (0s) 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 Positive Bias Stress Vg = 60 (60s) Vg = 60 (180s) Vg = 60 (300s) Vg = 60 (600s) Vg = 60 (1000s) -15-10 -5 0 5 10 15 light V g =60 (0s) light V g =60 (60s) light V g =60 (180s) light V g =60 (300s) light V g =60 (600s) light V g =60 (1000s) Gate Voltage (V) Positive Bias Illuminated Stress -15-10 -5 0 5 10 15 Gate Voltage (V) 照光下之元件劣化比較不嚴重, 主要在於閘極正偏壓下之元件劣化機制主要為 charge trapping, 但在照光環境下, 被捕獲之載子會被激發出原有之缺陷能態所以 Vt 之飄移量不如暗態嚴重 Vt shift (V) 10 8 6 4 2 0 Vg = 60 V, Dark stress Vg = 60 V, Light stress 200 400 600 800 1000 Stress Time (s) Behaviors of InGaZnO thin film transistor under illuminated positive gatebias stress. Appl. Phys. Lett. 97, 112104 (2010)

Dark / light illumination recovery 8 V G = 60V V G = 60V (light recover) Vt shift 6 4 Dark / light recover 2 0 Dark stress 0 500 1000 1500 2000 2500 3000 3500 Time (s)

機制驗證利用 charge trapping model 可以萃取出載子被捕捕獲以及調出缺陷所需之有效能量 Ea, 而實驗結果顯示載子被捕獲所需之能量比較大代表載子跳出缺陷能階比較容易, 因此在照光時, 載子之行為表現會比較趨向於跳出缺陷而不是被捕獲 τ=τ 0 exp(ea/kt) ln trap s 16 15 14 13 12 11 10 trapping V GS = 60V Charge trapping Ea (0.38eV) > Charge detrapping Ea (0.23eV) E τ,trap,trap. = 0.38 ev Thermioni c emission FN tunneling 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 1000/T ln det. 7.5 7.0 6.5 6.0 E τ,det,det. = 0.23 ev Gate floating detrapping 5.5 Thermion ic 5.0 emission FN 4.5 tunneling 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 1000/T Ec (a-igzo)

Light-induced instability of an InGaZnO thin film transistor without passivation layer without SiOx passivation layer with SiOx passivation layer SiO 2 PV S IGZO oxide G Glass substrate D S IGZO oxide G Glass substrate D

Initial electrical characteristics in the dark

Under light illumination Without SiO 2 passivation layer S IGZO oxide G Glass substrate D With SiO 2 passivation layer SiO 2 PV S IGZO oxide G Glass substrate D

Normalized Drain Current (A) 10-6 Dark initial Light initial 10-7 Light 60s Light 1000s 10-8 10-9 10-10 10-11 10-12 10-13 With SiO 2 passivation layer S SiO 2 PV IGZO oxide G Glass substrate D -15-10 -5 0 5 10 15 Gate Voltage (V)

NID 1e-4 1e-5 1e-6 1e-7 1e-8 S 1e-9 1e-10 1e-11 1e-12 1e-13 1e-14 Passivation (SiO2) Subthreshold leakage current IGZO oxide Hole Gtrapping Glass substrate initial Light 0s Light 60s Light 180s Light 300s Light 600s Light 1000s D Vg (-10 V) 1e-15-15 -10-5 0 5 10 15 VG e - e - e - e - e - e - e - e - h+ h+ h+ h+ Vs (common) e- e- e- e- e- e- e- h+ h+ h+ h+ h+ h+ h+ e- h+ h+ Vg (-10~0 V) h+ Vd (5V)

2. 未具有保護層之元件在照光環境下之不穩定性分析 Normalized Drain Current (A) Normalized Drain Current (A) 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 Vac. -15-10 -5 0 5 10 15 O 2 Gate Voltage (V) Gate Voltage (A) initial 60sec 180sec 300sec 600sec 1000sec initial 60s 180s 300s 600s 1000s 未具保護層之 IGZO TFT 在照光下之不穩定性, 可以發現跟外界環境有很大之相關若在真空環境下照光可以發現其 Vt 向左之飄移量會大於氧環境下照光由此可知對於未蓋保護層之元件其光敏感度可能跟氧氣之吸附與脫附有關元件在照光後會在主動層產生電子電洞對, 而產生之電洞會與吸附在 IGZO 上之氧離子 (O 2- ) 作用形成 O 2 然後脫附造成 Vt 往左偏移 -15-10 -5 0 5 Light-induced 10 instability 15 of an InGaZnO thin film transistor with and without SiOx passivation layer formed by plasma-enhanced-chemical-vapor-deposition. Appl. Phys. Lett. 97, 192103 (2010)

機制驗證 Normalized Drain Current (A) Normalized Drain Current (A) 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 Vacuum recovery initial Light 1000s vac. recover 100s vac. recover 200s vac. recover 500s vac. recover 1000s vac. recover 1500s vac. recover 2000s vac. recover 3600s vac. recover 7200s vac. recover 10800s -15-10 -5 0 5 10 15 Gate Voltage (V) O 2 recovery initial Light 1000s O 2 recover 100s O 2 recover 200s O 2 recover 500s O 2 recover 1000s O 2 recover 1500s O 2 recover 2000s O 2 recover 3600s O 2 recover 7200s O 2 recover 10800s 真空下 recovery 實驗流程真空下照光 1000s 氧氣下 recovery 由不同環境的 recovery 實驗可以驗證對於未具有保護層之元件其照光下之不穩定性在於氧氣之託負所造成之 Vt 向左飄移 -15-10 -5 0 5 10 15 Gate Voltage (V)

Improvement of ambient gas induced instability under gate bias operation by different PV layer No PV Sputter SiOx Sputter Al 2 O 3 SiOx Al 2 O 3 Gate Gate

儀器名稱 : 中文名稱 : 多靶磁控濺鍍系統英文名稱 :Multi-Target Sputter 儀器廠牌型號 : 廠牌及型號 : 聚昌, Psur- 100HB

儀器功能 : 薄膜沉積 : 可鍍各種金屬合金半導體絕緣體透明導電體 (ITO ZnO...) 本實驗室提供靶材 :Al Ti Cu ITO Al 2 O 3 SiO 2 其他靶材請自備可通入氣體 :Ar O 2 N 2 NH 3 H 2 製程最高溫度 :400 1 組 DC 電源供應器 (1000W 輸出 ) 及 2 組 RF 電源供應器 (1200W 輸出 ) 可共鍍真空度 (base pressure) 約為 5E-6 torr, 濺渡時最低操作壓力可達 2 mtorr

Comparison of PBTS stored in atmosphere ambiance (Vg=50, 85 ) Normalized Drain Current (A) 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 -30-20 -10 0 10 20 30 Gate Voltage (V) Initial 100s 500s 1000s 2000s Normalized Drain Current (A) 10-3 10-4 1 Day 10 Day 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 -30-20 -10 0 10 20 30 Gate Voltage (V) initial 100s 500s 1000s 2000s

PBTS (Vg=50, 85 ) Atmosphere for 10 days After baking device in H 2 O ambiance

Improvement of the ambiance induced instability by sputter SiOx Al 2 O 3 實驗內容 : 10 天追蹤特性探討 (1 5 10 Day) 實驗方式 : N/PBTS (85 ) No PV Sputter SiOx Sputter Al 2 O 3 SiOx Al 2 O 3 Gate Gate

Normalized Drain Current (A) 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 Comparison of PBTS in no PV, sputter SiOx, sputter Al 2 O 3 (Vg=50, 85 ) No PV -30-20 -10 0 10 20 30 Gate Voltage (V) Initial 100s 500s 1000s 2000s Normalized Drain Current (A) 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 SiOx 10-3 10-4 10-5 10-6 0 s 10 1 Day -7 10-8 10-9 10-10 2000 s initial 1 Day 100s 10-11 200s 10-12 500s 10-13 1000s 10-14 10-15 -30-20 -10 0 10 20 30-30 -20-10 0 10 20 30 1 Day 1 Day Gate Voltage (V) NI D (A) Al 2 O 3 V G (V) Normalized Drain Current (A) 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 -30-20 -10 0 10 20 30 Gate Voltage (V) initial 100s 500s 1000s 2000s Normalized Drain Current (A) 10 Day 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 Gate Voltage (V) initial 100s 500s 1000s 2000s NI D (A) -30-20 -10 0 10 20 30 10-3 10-4 10-5 10-6 10 Day 10 Day 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 -30-20 -10 0 10 20 30 V G (V) 0 s 100 s 500 s 1000 s 2000 s

Comparison of NBTS in no PV, sputter SiOx, sputter Al 2 O 3 (Vg= -50, 85 ) NID(Amp.) 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 No PV Gate Voltage (V) initial 100s 500s 1000s 2000s Normalized Drain Current (A) -30-20 -10 0 10 20 30 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 SiOx initial 100s 500s 1000s 2000s -30-20 -10 0 10 20 30 Gate Voltage (V) Normalized Drain Current (A) 10-3 10-4 10-5 10-6 10-10 10-11 10-12 10-13 10-14 10-15 Al 2 O 3 10 1 Day 1 Day 1 Day 10-7 -8 10-9 -30-20 -10 0 10 20 30 Gate Voltage (V) initial 100s 500s 1000s 2000s Normalized Drain Current (A) 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 -30-20 -10 0 10 20 30 Gate Voltage (V) initial 100s 500s 1000s 2000s Normalized Drain Current (A) 10-3 10-4 10-5 10-6 10-7 10 Day 10 Day 10 Day 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 -30-20 -10 0 10 20 30 Gate Voltage (V) initial 100s 500s 1000s 2000s Normalized Drain Current (A) 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 -30-20 -10 0 10 20 30 Gate Voltage (V) initial 100s 500s 1000s 2000s

Al 2 O 3 Gate PBTS (V G = 50 V, 85 ) NBTS (V G = - 50 V 85 ) V T (V) 4 2 0 Air Vacuum N 2 O 2 H 2 O V T (V) 4 2 0 O2 N2 Air H2O Vacuum -2-2 -4-4 0 500 1000 1500 2000 Stress time (s) 0 500 1000 1500 2000 Stress time (S)

Atmosphere for 10 days PBTS (V G = 50 V) (85 ) No PV Al 2 O 3 Normalized Drain Current (A) 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 -30-20 -10 0 10 20 30 Gate Voltage (V) initial 100 s 500 s 1000 s 2000 s

Summary 1. The degradation behavior under PBS has been attributed to the electron trapping mechanism and the PBIS is less than the PBS stress since the light-induced electron detrapping occurs simultaneously. 2. The light-induced instability for unpassivation device is due to the oxygen desorption induced negative Vt shift. 3. The unusually hump effect under positive bias stress is caused by water molecule adsorption induced parasitical transistor and Al 2 O 3 passivation layer can effectively prevent the water molecule adsorption and suppress the hump effect.

東芝 (Toshiba Corp.) 開發出以氧化物半導體 TFT 驅動的軟性有機 EL 面板, 在第 49 屆 SID International Symposium, Seminar & Exhibition (SID 2011) 發表

A 2.2 inch mono-qqvga (128 160 pixels) AMOLED driven by spin-coated IZO TFTs. (a) An optical microscope image of the pixel array. (b) A displayed image. Reprinted by permission from Society of Information Display

本實驗室 2011 TFT paper list 1. Environment-Dependent Thermal Instability of Sol-gel derived Amorphous Indium-Gallium-Zinc-Oxide Thin Film Transistors. Appl. Phys. Lett. 98, 152109 (2011) 2. Investigating the degradation behavior caused by charge trapping effect under DC and AC gate-bias stress for InGaZnO thin film transistor. Appl. Phys. Lett. 99, 022104 (2011) 3. Anomalous On-Current and Subthreshold Swing Improvement in Low- Temperature Polycrystalline-Silicon Thin-Film Transistors under Gate Bias Stress. Appl. Phys. Lett. 98, 122101 (2011) 4. Charge Trapping Induced Parasitic Capacitance and Resistance in SONOS TFTs under Gate Bias Stress. IEEE Electron Device Lett. 32(3), 321-323 (2011) 5. NBTI Degradation in LTPS TFTs under Mechanical Tensile Strain IEEE Electron Device Lett. 32(7), 907-909 (2011) 6. On-Current Decrease after Erasing Operation in the Nonvolatile Memory Device with LDD Structure. IEEE Electron Device Lett. 32(8), 1038-1040 (2011) 7. Effect of Lateral Body Terminal on Silicon-Oxide-Nitride-Oxide-Silicon Thin Film Transistors. accepted by IEEE Electron Device Lett. (2011).