p5e_vm_do_1[1].02g_ - PDF 免费下载

P-VM O P TITL R.0 00_0_ 00.0. 0 LOK IRM VR.0 Intel Pentium processor / 0 POWR FLOW HRT on oard Prescott,mithField 0 POWR QUN endar Mill,Presler 0 POWR ITRIUTION.V & TNY L 0 LOK ITRIUTION 0 RT MP RULTOR 0~0 Main clock 09~ INTL PROOR L 00//MHz INTL RLK R HNNL HOT U R HNNL R POWR Onboard V(L) LN & U onnector PIX_ PIX 00/MHz INTRT V HR 00MHz PI lot INTL 9 L Intel LN 0 on board TPM RLK ~ INTL IH9 PI xpress X LOT PI _ U MH Q ~ gerefw 00MHz 9 T onnector 0 JM 00MHz udio L_ MI LINK UIO ONNTOR Lanes ~ U_Power circuit 00MHz High-peed U PI U 9 0 TPM_ONNTOR PI ports 0Mb/s ~ WH POWR ONNTOR RLTK ZLI LINK INTL UIO T U O IH9 O.KHz VOR RIVR MHz V_UL& V&V_UL LI 00MHz L Intel MHz.V igabit thernet.mhz LI/PIX.V_UL& VTT_R 9 0 PNL & Hottart VOR ONTROLLOR L MHz.VUL &.0V &VTTPU.V NO(Intel) 00MHz crew Hole PI xpress X PIX U PI U 9 MI version List hange P 00MHz Jmb PIX U LINK R NTL T U T hannel hannel Note: N/ = Installed Part. = Not Installed Part. PROTO = PROTO Phase Only. ~0 9 MHz I MHz 9LPR9LF R NTL T efault component footprint is M 00 type. ifference footprint show on schematics. LOK MMORY R /00/0 R /00/0 PI Mb WXVI TII TII TII PI LOT PI LOT 00 MHz 00/ MHz MHz. MHz TII TII TII MHz MHz.MHz MHz.KHz Winbond UPR I LP U Thermal ensor UTek omputer Inc. P-VM O lock iagram hienhih_hung ate: Tuesday, November, 00 heet of.00

PU V P9 for PWM controller P0000RZ for MOFT driver fficiency is about % @ full loading in 0/ VOR () V V o_vw# (OT) (PK) P0N(P-MO)PT0H(N-MO) in 0/// V_UL PWK_TRL in 0// LO MP in 0//.V_UL (.) VTT_R () LO L0 in 0/ V_UL (0.) LO L0 in LL V () OPPT0H* in 0/.V (0.) PT0H in 0/ VTT_PU ().V PT0H in 0/.0V (.) OPPT0H* in 0/.V (.) P-VM O UTek omputer Inc. P-VM O Power Flow arry_ue ate: Friday, March, 00 heet of.00

->0 V 0-> V V_UX V_P0_UL V_P0_UL V_P0_UL& V_UX.V_UX.V_UX &.V.VTY.V_UX&.V.V_UX PUOR.VTY.V_UX.V_UX &.V PUOR.V.V_UX &.V.V_UX.V.V 0 0.V 0 0 -ms VRM_PWROO VRM_PWROO VRM_OUTN VRM_OUTN P-ON P-OFF 0 0 0 0.PUOR must rise after the voltage across 90% of.v,andthe interval is within -ms.vrm_outn rises after the voltage across 90% of its specified value ->0 V 0-> V_UX V_P0_UL V V_P0_UL V_P0_UL.V_UX.VTY.V_UX &.V.VTY.V_UX &.V.V_UX PUOR.VTY PUOR.V_UX.V.V 0 &.V.VTY.V_UX 0.V_UX 0 0 -ms.v &.V.V.V 0 VRM_PWROO VRM_OUTN P-ON 0 VRM_PWROO VRM_OUTN P-OFF.PUOR must rise after the voltage across 90% of.v,andthe interval is within -ms.vrm_outn rises after the voltage across 90% of its specified value 0 0 0: : : Windows RunningV,V_P0_UL,.V,.V_UX,.VTY,PUOR,.V,.V_UX,.V,.V existed Windows tandbyv_p0_ul,.v_ux,.v_ux,.vty existed Power On Only V_UX,.V_UX,.V_UX existed UTek omputer Inc. P-VM O Power equence Tyler_Yuan ate: Friday, March, 00 heet of.0

Prescott,mithdield, Presler & onroe VOR 0W.V_F_VTT..W.V V 0m 0m._UL. earlake K0._UL 0m (&MLK).V_F_VTT..V. (0,) K/M U 0..W U PORT UV (0,) UV m mw () FUV (0,) FUV 0m 0mW (). (MI&PI) V.9 (L) m ().m (MO) PI V 0m 99mW IH9.V_F_VTT m.v. m (PI) (U&T&PLL) m 0.0W(L internal) FN V 0. W.V.0V V V VRT m 0.W(LN) m (MI).(ore) m (L internal) m 0.W(0/00 LN internal) 9m (L) m (H,&) m(b-ln) 9m (0/00 LN) m (H 0&) 0m (V_) u L O V 00m W R IMM._UL. (0,)._UL T() VTT_R 0. (0) T () V 0m mw theros L V.m.mW(I&L).V.m.W(nalog) PI XPRx V. W V 0..W (wake) V 0m mw (no wake) V.0 9.9W.V.m.mW (ore) PIX V. W V 0..W (wake) V 0m mw (no wake) V.0 9.9W PI LOT V 0..W (wake) V 0m mw (no wake) V..0W V W V 0. W -V 0..W UTek omputer Inc. P-VM O Power istribution Tyler_Yuan ate: Friday, March, 00 heet of.0

PIx lot MHHLK/# K_00M_MH/# K_9M_RF/# 00/ MHz 00 MHz 9 MHz Intel earlake MH M_H_LK[0..]/# R, K_00M_P/# K_00M_P/# K_00M_P/# 00 MHz 00 MHz 00 MHz PIx lot PIx lot PIx lot M_H_LK[0..]/# R, K_00M_IH/# 00 MHz Intel Processor onroe L PUHLK/# 00// MHz LOK HIP RTMN-0 K_00M_T/# 00 MHz K_M_IH MHz K_M_U MHz K_M_IH. MHz Intel IH9 ITLK MHz Intel H udio odec K_M_L MHz PI lot PI lot PI lot ITP K_ITP/# 00/ MHz K_00M_LN/# 00 MHz ttansic L VI0 TPM K_M_IO MHz K_M_IO MHz WHF UTek omputer Inc. locks istribution Tyler_Yuan.0 P-VM O ate: Friday, March, 00 heet of

0-to- tate xplain: a. VU dirves high when PWR ONN plugd in. b. RMRT# drives high from IO to IH9. c. ULK sent out LK from IH9. Power uttom W PWRTN# LN_RT# PIRT# 0/00/000 theros L LP_# invert PON# POWR UPPLY P PWR_P P_IN# Winbond HF UPR I Included Power equence Logic Function npirt_out npirt_out npirt_out ni_rtrv npirt_out PI_RT# PI_RT# RT RT PI-xpress x PI-xpress x PWROK PWR_V LP_# LP_# RMRT# PI_RT# PLTRT# 0 Prescott Pentium Processor L earlaker MH NORTH RI PWROO PWROK PUPWR PWROK PUPWR PWRTN# PWRTN# _TT# LP_# LP_# LP_# IH9 OUTH RI RMRT# IHPIRT# PLTRT# PILOTRT# PLTRT# RT PI LOT RT PI LOT RT PI LOT RTIN# PLTRT# UTek omputer Inc. Reset Map Tyler_Yuan P-VM O ate: Friday, March, 00 heet of.0

{,} {} IO _M R J_OVT J_OVT _PI_L_R _LP_IO_R _PI R _PILK_TPM_R _PI_L_R _PI_9_R _M_U_R _M_IO_R K_9M_RF K_9M_RF# K T K T# _K_PWROK _PIX PIX#_ K_00M_IH K_00M_IH# _PI_R _PI_R# H_L0_R H_L_R H_L_R _V_LK From PO's Output (NO) RN RN RN RN R MOhm /LPR9.Mhz X _X 0PF/0V /LPR9 /LPR9 _X 9 0 9 0 9 0 9 U 0PF/0V /LPR9 *RF0/L **O_0 **O_ PILK0_X **L_TOP/PILK_X PILK_X FL/PILK_X FL/PILK_X VPI PILK_X PILK_X V FL/U_ *L_#/_Mhz OT9T_LR/PIeT_LR OT9_LR/PIe_LR TLKT_LR TLK_LR VT Vtt_Pwrd/P#/WOL_TOP# PIeT_LR0 PIe_LR0 V PIeT_LR PIe_LR PIeT_LR PIe_LR I9LPR9LF-T _RT# N ; _RT# RT# (Output) for Jumperfree. When PWROK is negated, the IH will asserts PLTRT#. WT RT# 9 X X VRF 0 V 9 T LK PUT_L0*** PU_L0*** VPU PUT_LF*** PU_LF*** RT_IN#/RT# 0 RLTH** 9.Mhz V Mhz V PIeT_LR/PU_TOP#* PIe_LR/PI_TOP#* 0 V 9 PIeT_LR PIe_LR PIeT_LR PIe_LR PIeT_LR PIe_LR N_L0_R {} N_L_R {} N_L_R {} R R _V_LK _PIX PIX# PI_N _PI_N# O_RTON# {,,9} O_RTON#_IO {} R /MultiJumper/PO_Trap O_PWROK {,,} _X _X _MT_MIN _MLK_MIN _F_PU_R _F_PU#_R _F_N_R _F_N#_R _RT# _RLTH R R0 K K {} O_RRX H_L0 H_L H_L 9 0PF/0V _PU_TOP# {} _PI_TOP# {} HL 0 0 0 0 0PF/0V RN0 KOHM HL 0 0 0 V 0.UF/0V V PU From PU's L LK Trapped by PU's L RN RN.KOHM PU_Trap RN PU_Trap.KOHM RN PU_Trap.KOHM Q PM90 /MultiJumper.KOHM PU_Trap HL0 F MHz (MHz) 0 00MHz(00MHz) 0 MHz(0MHz) 0 MHz(MHz) VTTPU RN KOHM /LPR9 Q P0N /MT UF/V/00 /MT Q N0 RN KOHM /LPR9 R 0K /MT Q N0 /nonmt R RN KOHM /LPR9 V _LP_M {,,,} Q9 L N0 /00Mhz H_L0_R H_L_R H_L_R K T {} K T# {} K_00M_IH {} K_00M_IH# {} _PI_N {} _PI_N# {} _PIX_ {} _PIX#_ {} 9 0.UF/V {} {} O_IO_P9 O_IO_P90 0UF/0V 0.UF/V RN0 KOHM RN KOHM /LPR9 _F_PU_R {} _F_PU#_R {} _F_N_R {} _F_N#_R {} _M_IO_R {} _M_U_R {} _M R {} _PI_L_R {} 0.UF/V RN0 KOHM RN0 KOHM {} O_N_ 0.UF/V Q Q N0 N0 0.UF/V H_L_R H_L0_R 0.UF/V R KOhm N/ 0.UF/V V R.KOhm Q N0 _V_LK 0.UF/V 0.UF/V H_L_R Q N0 VTTPU _PI_R {0} _PI_R# {0} _PI_L_R {} _M_IO_R _PI_9_R _M R 0 select output clock=mhz select pin/ to be PIX output OT Freq.=00Mhz select output clock=mhz select pin/ to be PI_TOP#/PU_TOP# OT Freq.=9Mhz _M_IO_R _M R _PI_9_R _V_LK RN.KOhm RN.KOhm N/ N/ RN.KOhm RN.KOhm N/ N/ F F F H_L0 RN H_L KOhm RN /00 H_L KOhm RN /00 KOhm RN /00 KOhm /00 _M_U_R RN _PILK_TPM_R.KOhm H_L0 {} RN.KOhm H_L {} _PI R RN.KOhm H_L {} RN /00.KOhm /00 /00 _PIX_ {} _PIX#_ {} K_9M_RF {} K_9M_RF# {} _K_PWROK {} _MLK_MIN {,,,0,} _MT_MIN {,,,0,} _PI R {} _PILK_TPM_R {} _LP_IO_R {} _PI_9_R {} R9 O_RMRT# {9,,} For support F PU H_L0_R _RLTH R9 _LP# {,} V R.KOhm /upport_f R VTTPU KOhm R9 Q /L_F PM90 KOhm /upport_f /upport_f H_L0 H_L_R VTTPU Q PM90 /upport_f R90 0 /upport_f R.KOhm /upport_f Q0 PM90 /upport_f H_L_R UTek omputer Inc. 0.Main lock- dany_hao P-VM O.00 Friday, March, 00 ate: heet of

{} _F_PU_R R Ohm _F_PU {0,} {} _F_PU#_R {} _F_N_R R Ohm R Ohm _F_PU# {0,} K_F_N {} {} _PI_L_R OHM RN _PI_ {} {} _PI_L_R OHM RN9 0PF/0V _PI_ {} 0PF/0V {} _F_N#_R K_F_N# {} {} _LP_IO_R OHM RN R Ohm _LP_IO {} 9 0PF/0V {} _M_IO_R R OHM _M_IO {} 0PF/0V OHM RN OHM RN9 {} {} _M_U_R _M R R0 OHM R OHM K_M_U {} 0 0PF/0V K_M_ {} 0PF/0V {} {} _PI_9_R _PI R OHM RN OHM RN9 _PI_9 {} 0PF/0V _PI_ {} 0PF/0V {} _PILK_TPM_R OHM RN9 _PILK_TPM {0,9,9} 0PF/0V UTek omputer Inc. P-VM O 0.Main lock- lbert hang ate: Friday, March, 00 heet of.00

{} H_RQ0# {} H_#[:] {} H_RQ#[0:] {} H_T#0 {} H_R#[0:] {} H_# {} H_NR# {} H_HIT# {} H_PRI# {} H_Y# {} H_RY# {} H_HITM# {} H_INIT# {} H_LOK# {} H_TRY# {} H_FR# Output, Not tuff lose to PU Len = 0~.". H_VTT_OUT_R H_# H_# H_# H_# H_# H_# H_#9 H_#0 H_# H_# H_# H_# H_# H_# H_R#0 H_R# H_R# HR Ohm / mb_r00 H_IRR# H_VTT_OUT_L Test Pin can remove for layout space H_RQ#0 K H_RQ# J H_RQ# M H_RQ# K H_RQ# J HR Ohm mb_r00 L 0# P 0# M 0# L 0# M 0# R 0# T 09# U 0# T # U # U # V # V # W # R N P RQ0# RQ# RQ# RQ# RQ# T0# R0# F R# R# # NR# HIT# PRI# Y# RY# HITM# P INIT# LOK# TRY# FR# F H U U J H H J L IRR# R0# RP# INIT# MRR# P0# P# P0# P# P# P# RV RV RV RV OKT # # W 9# Y 0# Y # # # # # # # F # F 9# 0# # # H # H # J # J T# TLRF TLRF0 H F is TLRF H_# H_# H_#9 H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_#9 H_#0 H_# H_# H_# H_# H_# H_TLRF_L TLRF_L H9 TLRF F/TLRF RV/TLRF H 0 F H_PU_TLRF0 HR mb_r00 / H 0PF/0V / XR H_PU_TLRF H_PU_TLRF H_PU_TLRF H_#[:] {} support lose to PU H_#[:] {} H_T# {} lose to PU H 0PF/0V / XR HR mb_r00 / HT / H0 0PF/0V / XR H9 0PF/0V / XR lose to PU H_PU_MH_TLRF {} HR lose to PU PU_TLRF0/// Voltage ivider for Nvidia * PU_TLRF = 0. * VTT = 0.V HR HR HR HR 改改. HR HR HR9 HR0 改改 00 0V000 PU_TLRF0/// Voltage ivider for intel 9~ 9,9 * PU_TLRF = 0. * VTT = 0.V HR HR HR HR 改改 0V0 HR HR HR9 HR0 改改 0 0V00 PU_TLRF0/// Voltage ivider for X 9(for presler) * PU_TLRF = 0. * VTT = 0.V HR HR HR HR 改改 00 0V000 HR HR HR9 HR0 改改 00 0V00 PU_TLRF0/// Voltage ivider for Q, Q,, P, * PU_TLRF = 0. * VTT = 0.V HRHR HR 改改 0000 HR 改改. HR HR9 HR0 改改 00 0V00 HR 改改 00 H_PU_TLRF0_R HR H_PU_TLRF_R mb_r00 HR H 0 UF/0V % HR HR mb_r00 H UF/0V H_PU_TLRF_R mb_r00 H UF/0V H_PU_TLRF_R mb_r00 H UF/0V H_VTT_OUT_R H_VTT_OUT_R H_VTT_OUT_L HR0 0 % HR Ohm % HR Ohm % HR 0 % HR.OHM % HR Ohm % H_VTT_OUT_L HR9 0 % {} H_#[0:] H_PU_TLRF0_R {} {} H_I#0 H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_#9 H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_#9 H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_#9 H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_#9 H_#0 H_# H_# H_# H_# H_# H_# H_# {} H_TN#0 TN0# TN# 0 H_TN# {} {} H_TP#0 9 TP0# TP# 9 H_TP# {} H_PU_TLRF_R {} {} H_#[:] {} H_I# H_PU_TLRF_R {} {} H_TN# {} H_TP# H_PU_TLRF_R {} 00# 0# 0# 0# 0# 0# 0# 0# 0 0# 09# 0 0# # # # # # I0# 9 # F # F9 # 9 9# 0# 0 # 0 # F # F # # # # F # 9# F 0# # L I# TN# TP# OKT U TeK omputer IN H_# H_#9 H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_#9 H_#0 H_# H_# H_# H_#[:] {} H_I# {} H_#[:] {} H_I# {} H_TN# {} H_TP# {} L- (Host us) # # # # # # F # F 9# 0# 9 # F0 # # F # # # # I# 9 # 0 9# 0# # # # # # # # # 9# 0# 9 # 9 # # I# 0 TN# TP# P-VM O 0. eta Makishin Huang ate: Friday, March, 00 heet 9 of 0.

PU VI Termination (PU ide) H_VTT_OUT_R mb_rp00 HRN KOhm HRN KOhm HRN KOhm HRN KOhm HRN9 KOhm HRN9 KOhm HRN9 KOhm HRN9 KOhm mb_rp00 INTL and other : H_FRR# need pull-high at side {} {} NV9..:H_FRR# {} ohm and H_NMI, {} HR H_INTR 0ohm need {} KOhm pull-high at side {} % {} mb_r00 H_MI# H_0M# H_FRR# H_INTR H_NMI H_INN# H_TPLK# L P MI# K 0M# R FRR#/P# K LINT0/INTR L LINT/NMI N INN# M TPLK# TTHI_ TTHI_ TTHI_ TTHI_ TTHI_ TTHI_ TTHI_0 F F F H_TTHI_ H_TTHI_ H_TTHI_ H_TTHI_ H_TTHI_ H_TTHI_ H_TTHI_0 HRN HR9 VTTPU Ohm Ohm mb_r00 H_VTT_OUT_L 0. eta {,0} H_VI_LT {,0} H_VI0 {,0} H_VI {,0} H_VI {,0} H_VI {,0} H_VI {,0} H_VI HRN HRN HRN HRN HRN HRN HRN {,0} H_VI.KOhm HRN {,0} H_VI mb_rp00.kohm y IO : 改 H_VI_T,H_VI_T 改 H_VII,H_VII. For winbond and other IT IO, 改 H_VI,H_VI PU Thermal iode P THRM : ed. M. / Presler PI : onroe PI onreo / llendale PU upport H_THRMTRIP# is O/ and need pull-high at side If power didn't use,can be removed H_V_PLL from or other.v in power page and need to care about the sequency. H_V_PLL New Feature for onroe.kohm.kohm.kohm.kohm.kohm mb_rp00.kohm VTTPU VTTPU {,} H_THRM_PU- H_VPLL H_VTT_OUT_R {,} _F_PU {,} _F_PU# {} H_KTO# {,} H_THRM_PU HR HR / {} H_PI {} H_THRMTRIP# IN 00 0UH m 0% HL 0UH / IN 00 0UH m 0% HL 0UH PL OMPONNT LO POIL TO PU OKT. TH TR WITH TO P MUT NO MLLR THN MIL. IN 00 0UH m 0% HL 0UH HL /00Mhz mb_l00..:h/h/h/h change from 0uF/0V 0 XR to 0uF/0V 00 YV by rule. H_THRM_PU-_R VOR H_V HJP HORTPIN / H_VIOPLL (PU F PLLs Power) H_VI_LT H_VI0_R H_VI_R H_VI_R H_VI_R H_VI_R H_VI_R H_VI_R H_VI_R HR0~HR OM should be by PU support. on't support old PU,then OM should change H 0UF/0V H_V H 0UF/0V H 00PF/0V K H_V_PLL H 0UF/0V / H 0.UF/V N M L M L K L M M F L M N N N N L L VI_T VI0 VI VI VI VI VI VI VI LK0 LK KTO# THRM THRM PI THRMTRIP# V_N V_N V_M_RULTION V_M_RULTION V N V N V V VIOPLL V_PLL TTHI0 TTHI09 TTHI0 TTHI_ TTHI_ TTHI_ TTHI_ RV RV RV RV RV OOTLT RV9 RV LL_I0 LL_I N RT# PWROO PROHOT# H W P W L U 9 H Y F9 V L N L.lose to PU Len = 0 ~ in.. V is Ohm H_TTHI_ H_TTHI_9 H_TTHI_0 H_TTHI_ H_TTHI_ H_TTHI_ H_TTHI_ H_TP_PU_ H_TP_KLPH_ % mb_r00 H_TP_FRN_9 HT/ H_TP_PU_H H_PUOOT H_TP_R_9 H_TP_LWTRL_ H_TP_LL_I0_V H_TP_LL_I_ H_TP_VRL H_PURT# H_PUPWR H_PROHOT# H_TTHI_ HRN Ohm HRN Ohm HRN Ohm HRN Ohm onnected to Pin "TTHI_" HR0 HT / HT0 / HR HR Ohm mb_r00 HR KOhm / HT / HT9 / HT / HT / HR HRN Ohm Ohm / mb_r00 Ohm mb_r00 0 / HR % HRN Ohm H_VTT_OUT_L H_VTT_OUT_L HRN Ohm H_VTT_OUT_R H_VTT_OUT_L H_VTT_OUT_R H_VTT_OUT_R H_TTHI_ {} H_TTHI_9 {} epend on chipset support : onnected to PULP# IH: can disconnect H_TP_PU_ {} H_PUOOT {} L support OOTLT Y: Weak Internal PU 00P MI MI0 H_PURT# {,} HR : lose to PU Len = 0 ~ in. H_PUPWR {,} HR : Intel R Remove it 00V N 0(W) N H_PROHOT# {0,} H_PROHOT#:If use the input and output function,need to PU H_OMP :.9ohm for P 0ohm 0.ohm for P 0ohm H 0.UF/V / H_VTT_OUT_L H 0.UF/V / HR0 HR HR HR HR HR HR HR HR 9.9Ohm 9.9Ohm 9.9Ohm 9.9Ohm 9.9Ohm 9.9Ohm 9.9Ohm 9.9Ohm.9Ohm H_OMP H_OMP H_OMP H_OMP H_OMP0 H_OMP H_OMP H_OMP H_OMP Y OMP OMP J OMP T OMP OMP0 T OMP OMP R OMP OMP J RV H RV OKT FORPR# IMPL MI MI0 K F V W H_FORPR# H_IMPL H_MI H_MI0 HR HR HR Ohm Ohm mb_r00 mb_r00 HR % Ohm mb_r00 HR HR bom by design. efault 0P HR: ohm for 00, N for H_MI0 {} U TeK omputer IN H_FORPR# {0,} H_FORPR#,H_PROHOT# : Use for ual-ore PU VR Thermal ontrol ircuit(t) P-VM O L- (PU, VI, Misc.) Makishin Huang ate: Friday, March, 00 heet 0 of 0.

H_L[0:] need pull-high ~ K to VTTPU at LKN page. ~ K depend on supporting retraping H_VTT_LT should be pull high at POWR P VOR controllor had pu 0ohm to H_VTT_OUT_R {} {} {} H_L0 H_L H_L {} H_VTT_LT {0} P_VTT_PWR Test Pin can remove for layout space H_VTT_OUT_L H_VTT_OUT_R VTT_OUT_R H9 0.UF/V / H 0.UF/V / L 9 L0 H0 L 0 L F VTT_L H_VTT_OUT_R H 0.UF/V H0 0.UF/V HR9 KOhm / % mb_r00 M VTTPWR J VTT_OUT_L RV9 RV0 RV 0 RV RV OKT VTT VTT VTT VTT VTT VTT VTT VTT VTT9 VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT9 VTT0 VTT VTT VTT VTT RV PM0# PM# PM# PM# PM# PM# TK TI TO TM TRT# ITPLKOUT0 ITPLKOUT R# RV 9 9 0 9 0 0 9 0 9 J J F F K J N VTTPU H_TT Test Pin can remove for layout space H_PM#0 H_PM# H_PM# H_PM# H_PM# H_PM# H_TK onnected to ITP H_TI H_TO H_TM H_TRT# HR KOhm / H_ITP_LK HR KOhm / H_ITP_LK# % mb_r00 % mb_r00 HR KOhm H_TP_N % / mb_r00 H_LKPH_ H_LKPH_J LF F V0 F V9 F V F V F V F V F0 V F V F V F V F0 V0 V9 V 0 V 9 V V V V V V 0 V0 V9 V V V 0 V V V V RV RV RV0 F RV RV9 J RV OKT 0. eta V V V V V V V 9 V9 V0 V V V V V 9 V V 0 V V9 V0 V V V V V V V 9 V 0 V9 V0 V post_nc post_nc post_nc post_nc L L L0 PU Frequency 0 0 0 0 0 0 0 0 0 MHz MHz 00MHz MHz {0} H_TTHI_ {0} H_TTHI_9 {0,} H_PUPWR {,,,0,} _MLK_MIN {,,,0,} _MT_MIN onnected to PU onnected to PU H_VTT_OUT_R H_PM# H_PM# H_TK TK/TI/TM : near PU, <." lose to PU HRN P Ohm HRN P Ohm HR /OT/NomaskP HR /OT/NomaskP H_VTT_OUT_R mb_r00 HR KOhm % P HR P H_VTT_OUT_R mb_r00 HR Ohm P mb_rp00 HRN Ohm HRN Ohm *ITP,HR,HR,HR,HR place on bottom. ** The HRN of H_TK, H_TRT#, and H_PM# must be mounted. efault 不不 XP 請 function 要不 XP 請 ONNTOR 請 OM 如如請請 RWORK 方方 XP HRN HRN HR HR HR H_PM# H_PM# H_ITP_PWR H_ITP_TTIN# H_VTT_OUT_R XP PM# PM# PM# PM# PM# 0 PWROO PM0# 9 RRV VTT LK0 LKp KL LKn 0 RT# 9 L R# TO TRT# N 0 TK TI 9 TM TO_ON_P /OT/NomaskP H_PM# H_PM# H_PM# H_PM#0 H_ITP_LK_R H_ITP_LK#_R H_ITP_PURT# O_RTON# H_TO H_TRT# H_TI H_TM lose to PU HRN Ohm HRN P Ohm HRN P Ohm HRN P Ohm mb_rp00 H_PM# H_PM# H_PM# H_PM#0 mb_rp00 HRN Ohm HRN Ohm HRN Ohm HRN Ohm TO: lose to ITP connector TK/TI/TM : near PU, <." H_VTT_OUT_R HR /OT/NomaskP HR /OT/NomaskP onnected to PU P P P H_TO H_TRT# H_TI H_TM H_VTT_OUT_R H_VTT_OUT_L H_TT HR P/Nomask HR P/Nomask HR KOhm P % mb_r00 onnected to PU HR Ohm mb_r00 P HR9 P/Nomask HR0 P/Nomask onnected to PU U TeK omputer IN H_TP_PU_ {0} H_ITP_LK H_ITP_LK# _F_PU {,0} _F_PU# {,0} H_PURT# {0,} O_RTON# {,,9} P-VM O HR HR HR9 HR0 請請請請請請請請 L- (FL, ITP I/F) Makishin Huang ate: Friday, March, 00 heet of 0.

VOR VOR ate: heet of Friday, March, 00 U TeK omputer IN L-(POWR) 0. P-VM O Makishin Huang ate: heet of Friday, March, 00 U TeK omputer IN L-(POWR) 0. P-VM O Makishin Huang ate: heet of Friday, March, 00 U TeK omputer IN L-(POWR) 0. P-VM O Makishin Huang 0. eta V F9 V F V F0 V F V F V 0 V V V9 V 0 V V V V H V H0 V H V H V H V9 H0 V0 H V H V H V H V J0 V J V J V J V9 J0 V90 J V9 J V9 J V9 J V9 J9 V9 J0 V9 J V9 K0 V99 K V00 K V0 K V0 K V0 K0 V0 K V0 K V0 K V0 K V0 K9 V09 K0 V0 K V K V L0 V L V L V L V L0 V L V L V9 L V0 L V M V M0 V M V M V M V M0 V9 M V0 M V M V M V M V N V N0 V N V N V9 N V0 N V N0 V N V N V N V N V V V9 V0 V 0 V V V V 0 V V V 9 V9 V0 V V V V V V V V V9 V V 9 V V V V V 0 V V V9 V0 V V F0 V F V F V F9 V F V F V9 F V9 H0 V9 H V9 H V9 H V9 H V9 H V9 H V9 H9 V99 H0 V00 H V0 H V0 H V0 H V0 H V0 H V0 H V0 H V09 H V0 H V H V H V H9 V J V J V K V K V K V9 L V0 L V L V L V L V L V L9 V L V L0 V L V9 L V0 M V M V N V N V N V P V P V P V P V9 P V0 P V P9 V P0 V P V P V R V R V R V R V9 R V0 R V R V R9 V R0 V R V R V T V T V T V0 U V V V V V V V V V V V V V V9 V V V9 V0 V V V V V W V W V Y V Y V Y L OKT L OKT ocket tandard ircuit PU RV. OKT H_0. eta ocket tandard ircuit PU RV. OKT H_0. eta V V V V V V V V V9 9 V0 0 V V V V V V V V 9 V9 0 V0 V V V V V V 9 V V V9 V0 9 V F V F V F V F V F V F9 V F V F V9 F V0 F9 V V V V V V 9 V V V9 V0 V V V 9 V 0 V V 9 V H V H V9 H V0 H V H V H9 V H V H V H V H V H V H V9 H9 V H0 V H V H9 V J V J V J V J V J V J9 V9 J V0 J V J V J V J V J9 V K V K V K V K V9 K V90 K9 V9 K V9 K V9 K V9 K V9 K V9 K9 V9 L V9 L V99 L V00 L V0 L V0 L9 V0 L V0 L V0 L V0 L V0 L9 V0 L0 V0 L9 V M V M V M V M V M V M9 V M V M V9 M V0 M V M9 V M0 V M V M9 V N V N V N V N V9 N V0 N9 V N V N V N V N V N9 V N0 V N V N9 V9 J0 V0 J V J V J V J V J V J V J9 V J0 V J V9 J V0 J V J V J V J V J V J V J9 V J0 V J V9 J9 V0 K V K V K V K V K V K V K9 V K0 V K V L V M V M V M V M V M V0 M V9 M9 V M0 V M V N V N V N V N V N V N V0 N9 V09 N0 V0 N V0 P V0 R V0 T V0 T V0 T V0 T V0 T V00 T V99 T9 V9 T0 V9 T V9 U V9 U V9 U V9 U V9 U V9 U V90 U9 V9 U0 V U V V V W V W V W V W V W V W V0 W9 V9 W0 V W V Y V Y V Y V Y V Y V Y V Y9 V Y0 V9 Y L OKT L OKT

V V NW PU WITH (onroe,wolfdale) 0. eta HR / HR9 HRN.KOhm mb_rp00 H_W_P HRN.KOhm VR0. VR H_VI_LT HIH HRN.KOhm mb_rp00 HRN.KOhm mb_rp00 mb_rp00 H_PUOOT H_PUOOT {0} H_PUOOT FLOTIN H_MI0 FLOTIN HR.KOhm {0,0} H_VI_LT H_VI_LT H_VI_LT_ mb_r00 HQ PM90 H 0.UF/V / mb_c00 H_PUOOT_ HQ HN0 HN0 HR Ohm H_PUOOT_ mb_r00 H_MI0 H_MI0 {0} H 0.UF/V / mb_c00 V TLRF over Voltage circuit (Yorkfield,Wolfdale) H_MI0_ V HQ HN0 / H_MI0_ HR Ohm / mb_r00 HQ HRN.KOhm mb_rp00 HQ9 This table only for Q, Q,, P, Other is T PIO-.efault Input PIN with standby power.efault output high PIN with standby power {} H_TLRF_OV# HRN.KOhm mb_rp00 HRN.KOhm mb_rp00 HRN.KOhm mb_rp00 HRN.KOhm mb_rp00 H_TLRF_OV#_ V HQ0 PM90 H_TLRF_OV#_ V H_TLRF_OV#_ HRN0.KOhm mb_rp00 HN0 HR Ohm 0.0 H_TLRF_OV_ HQ mb_r00 HR / mb_r00 HR H_PU_TLRF0_R {9} H_PU_TLRF_R {9} OV OV OV 0 0 0 0 0 0 0 0 0 Ratio et 0. 0. 0.9 0. 0. 0. 0. 0. PIO-.efault Input PIN with standby power.efault output high PIN with standby power {} H_TLRF_OV# PIO-.efault Input PIN with standby power.efault output high PIN with standby power {} H_TLRF_OV# HRN H_TLRF_OV#_ HN0.KOhm mb_rp00 H_TLRF_OV#_ HQ HRN0 H_TLRF_OV#_ HR PM90.KOhm.KOhm mb_rp00 V % V HRN.KOhm mb_rp00 HRN0.KOhm mb_rp00 HRN0.KOhm mb_rp00 H_TLRF_OV#_ HQ H_TLRF_OV#_ PM90 HRN.KOhm mb_rp00 H_TLRF_OV#_ mb_r00 HR9 / mb_r00 HR0 / HQ HN0 P-VM O H_PU_TLRF_R {9} H_PU_TLRF_R {9} HR Ohm % U TeK omputer IN L-(WITH) Makishin Huang ate: Friday, March, 00 heet of 0.

H_RQ#0 H_RQ# H_RQ# H_RQ# H_RQ# H_R#0 H_R# H_R# H_WIN_IV H_WIN H_WIN H_OMP# H_OMP H_OMP MH_TLRF0 H_ROMP MH_TLRF0 H_OMP# H_# H_# H_#0 H_#9 H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_#9 H_# H_# H_# H_# H_# H_# H_# H_#9 H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_#0 H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#9 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_#9 H_# H_# H_#0 H_#9 H_#0 H_#9 H_# H_# H_# H_#9 H_# H_#9 H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_#0 H_# H_# H_# H_# VTTPU VTTPU VTTPU H_RQ#[0:] {9} H_T# {9} H_T#0 {9} H_TP# {9} H_TN# {9} H_TN#0 {9} H_TP#0 {9} H_I# {9} H_I#0 {9} H_I# {9} H_TN# {9} H_TP# {9} H_I# {9} H_TP# {9} H_TN# {9} H_# {9} H_TRY# {9} H_RY# {9} H_NR# {9} H_HIT# {9} H_PRI# {9} H_Y# {9} H_HITM# {9} H_LOK# {9} H_FR# {9} H_RQ0# {9} H_R#[0:] {9} H_PURT# {0,} K_F_N# {} K_F_N {} H_PU_MH_TLRF {9} H_PURT# {0,} H_#[:] {9} H_#[:] {9} H_#[:] {9} H_#[:] {9} H_#[0:] {9} H_#[:] {9} H_#[:] {9} ate: heet of Friday, March, 00 UTek omputer Inc. RLK-.0 P-VM O Tyler_Yuan ate: heet of Friday, March, 00 UTek omputer Inc. RLK-.0 P-VM O Tyler_Yuan ate: heet of Friday, March, 00 UTek omputer Inc. RLK-.0 P-VM O Tyler_Yuan 0/0 0/ 0/ 0/ 此須須須 N N.PF/0V N.PF/0V H# J H# L9 H# J0 H# L H# L H# K H9# N H0# N H# M H# N H# M H# R H# N H# N H# U H# N9 H9# R H0# P H# R9 H# V H# R H# U H# U H# R H# V H# V H9# Y H0# V H# V H# Y H# Y H# Y9 H# HRQ0# F0 HRQ# L HRQ# L HRQ# HRQ# J HT0# M HT# U HTP0# M HTN0# M HTP# HTN# H HTP# HTN# H HTP# HTN# HINV#0 M0 H# W0 HTRY# Y0 HRY# W HFR# T HITM# Y HIT# U HLOK# V HRQ0# HINV# J HINV# 9 HINV# HNR# W HPRI# 9 HY# U0 HR0# U HR# HR# U9 HPURT# H0 R0 H P H R H N0 H R H M9 H N H N H L H9 J9 H0 L H J H K H 0 H F H F H H H F H9 H0 H 9 H H 9 H 9 H H H F H H9 K H0 H H H J H F H M H H K H H K9 H9 F H0 J9 H F9 H L H K H H H L H J H M H H9 H0 H H H 0 H H 0 H H H H9 H0 H H H HWIN HROMP HOMP HOMP# HVRF HVRF HLKP R HLKN U F NU RLK F NU RLK NR 9.9Ohm NR 9.9Ohm NR9 9.9Ohm NR9 9.9Ohm N 0.UF/V N 0.UF/V NR 9.9Ohm NR 9.9Ohm NR NR N UF/0V N UF/0V N.PF/0V N.PF/0V N 0.UF/V N 0.UF/V NR.Ohm NR.Ohm NR0 0 NR0 0 NR KOhm NR KOhm NR NR N 0.UF/V N 0.UF/V NR KOHM NR KOHM NR Ohm NR Ohm

V NU {} _PI_N {} _PI_N# {} X_VO_T {} X_VO_LK VO TRL T : VO R PRNT, P IL 0: VO IL (FULT) XP_LKINP XP_LKINN VO_TRLT VO_TRLLK VO PI XP_OMPO XP_OMPI N_XP_OMP0 NR.9Ohm.V X_VO_LK X_VO_T NR 0KOhm NR 0KOhm NR 0KOhm NR 0KOhm {} X_X_RXP0 {} X_X_RXN0 {} X_X_RXP {} X_X_RXN {} X_X_RXP {} X_X_RXN {} X_X_RXP {} X_X_RXN {} X_X_RXP {} X_X_RXN {} X_X_RXP {} X_X_RXN {} X_X_RXP {} X_X_RXN {} X_X_RXP {} X_X_RXN {} X_X_RXP {} X_X_RXN {} X_X_RXP9 {} X_X_RXN9 {} X_X_RXP0 {} X_X_RXN0 {} X_X_RXP {} X_X_RXN {} X_X_RXP {} X_X_RXN {} X_X_RXP {} X_X_RXN {} X_X_RXP {} X_X_RXN {} X_X_RXP {} X_X_RXN F K J F J H J H F F L9 L M M9 M L M M R9 R0 T R R R P_RXP_0 P_RXN_0 P_RXP_ P_RXN_ P_RXP_ P_RXN_ P_RXP_ P_RXN_ P_RXP_ P_RXN_ P_RXP_ P_RXN_ P_RXP_ P_RXN_ P_RXP_ P_RXN_ P_RXP_ P_RXN_ P_RXP_9 P_RXN_9 P_RXP_0 P_RXN_0 P_RXP_ P_RXN_ P_RXP_ P_RXN_ P_RXP_ P_RXN_ P_RXP_ P_RXN_ P_RXP_ P_RXN_ XP_TXP0 XP_TXN0 XP_TXP XP_TXN XP_TXP XP_TXN XP_TXP XP_TXN XP_TXP XP_TXN XP_TXP XP_TXN XP_TXP XP_TXN XP_TXP XP_TXN XP_TXP XP_TXN XP_TXP9 XP_TXN9 XP_TXP0 XP_TXN0 XP_TXP XP_TXN XP_TXP XP_TXN XP_TXP XP_TXN XP_TXP XP_TXN XP_TXP XP_TXN 0 0 9 9 F F J K L K N M P N R P U T V U X_X_TXP0 {} X_X_TXN0 {} X_X_TXP {} X_X_TXN {} X_X_TXP {} X_X_TXN {} X_X_TXP {} X_X_TXN {} X_X_TXP {} X_X_TXN {} X_X_TXP {} X_X_TXN {} X_X_TXP {} X_X_TXN {} X_X_TXP {} X_X_TXN {} X_X_TXP {} X_X_TXN {} X_X_TXP9 {} X_X_TXN9 {} X_X_TXP0 {} X_X_TXN0 {} X_X_TXP {} X_X_TXN {} X_X_TXP {} X_X_TXN {} X_X_TXP {} X_X_TXN {} X_X_TXP {} X_X_TXN {} X_X_TXP {} X_X_TXN {} VO TRP VO TRL T : VO R PRNT, P IL 0: VO IL (FULT) {} N_MI_RX0 {} N_MI_RX#0 {} N_MI_RX {} N_MI_RX# {} N_MI_RX {} N_MI_RX# {} N_MI_RX {} N_MI_RX# N_MI_RX0 N_MI_RX#0 N_MI_RX N_MI_RX# N_MI_RX N_MI_RX# N_MI_RX N_MI_RX# W V Y Y9 MI_RXP0 MI_RXN0 MI_RXP MI_RXN MI_RXP MI_RXN MI_RXP MI_RXN MI MI_TXP0 MI_TXN0 MI_TXP MI_TXN MI_TXP MI_TXN MI_TXP MI_TXN V V W Y 9 Y N_MI_TX0 N_MI_TX#0 N_MI_TX N_MI_TX# N_MI_TX N_MI_TX# N_MI_TX N_MI_TX# N_MI_TX0 {} N_MI_TX#0 {} N_MI_TX {} N_MI_TX# {} N_MI_TX {} N_MI_TX# {} N_MI_TX {} N_MI_TX# {} RLK UTek omputer Inc. P-VM O RLK- Tyler_Yuan ate: Friday, March, 00 heet of.0

_M _M _M _M _M _M _M _M _M9 _M0 _M _M _M _M _0 #0 # # _K_0 _K K K OT OT OT Q_0 _Q_#0 _M_0 _Q_0 _Q Q Q Q Q Q Q Q Q_# _M Q Q_9 _Q_0 _Q Q Q Q Q Q Q_# _M Q Q Q Q_9 _Q_0 _Q Q Q Q Q_# _M Q Q Q Q Q Q_9 _Q_0 _Q Q Q_# _Q Q Q Q Q Q Q Q_9 _Q Q_# _M Q_0 _Q Q Q Q Q Q Q Q Q_# _M Q Q_9 _Q_0 _Q Q Q Q Q Q Q_# _M Q Q Q Q_9 _Q_0 _Q Q Q M0 _M _M _M _M _M _M _M _M _M9 _M0 _M _M _M _M _0 #0 # # # _K_0 _K K K OT_0 _OT OT_ N_R_VRF N_R_OMPY_PU N_R_ROMPVOH N_R_ROMPVOL _Q_0 _Q_#0 _M_0 _Q_0 _Q Q Q Q Q Q Q Q Q_# _M Q Q_9 _Q_0 _Q Q Q Q Q Q Q_# _M Q Q Q Q_9 _Q_0 _Q Q Q Q Q_# _M Q Q Q Q Q Q_9 _Q_0 _Q Q Q_# _M Q Q Q Q Q Q Q Q_9 _Q Q_# _M Q_0 _Q Q Q Q Q Q Q Q Q_# _M Q Q_9 _Q_0 _Q Q Q Q Q Q Q_# _M Q Q Q Q_9 _Q_0 _Q Q Q_ N_R_VRF N_R_OMPX_P N_R_OMPY_P N_R_OMPX_PU RV_N _OT_0 _M0 # _M OT_.VUL.VUL.VUL.VUL _# {} _R# {} _M_LK0 {} _M_LK#0 {} _M_LK {} _M_LK# {} _M_LK {} _M_LK# {} _M_LK {} _M_LK# {} _Q_0 {} _Q_#0 {} _M_0 {} _Q_ {} _Q_# {} _M_ {} _Q_ {} _Q_# {} _M_ {} _Q_ {} _Q_# {} _M_ {} _Q_ {} _Q_# {} _Q_ {} _Q_# {} _M_ {} _Q_ {} _Q_# {} _M_ {} _Q_ {} _Q_# {} _M_ {} _Q_[0..] {} _M[0..] {} #0 {} # {} # {} _M[0..] {} _R# {} _# {} _W# {} _0 {} _OT_0 {} _M_LK0 {} _M_LK# {} _M_LK# {} _M_LK {} _M_LK#0 {} _M_LK {} _Q_0 {} _Q_#0 {} _M_0 {} _Q_ {} _Q_# {} _M_ {} _Q_ {} _Q_# {} _M_ {} _Q_ {} _Q_# {} _M_ {} _Q_ {} _Q_# {} _M_ {} _Q_ {} _Q_# {} _M_ {} _Q_ {} _Q_# {} _M_ {} _Q_ {} _Q_# {} _M_ {} _0 {} _K_0 {} _Q_[0..] {} #0 {} # {} # {} # {} _K_ {} _K_ {} _K_ {} _K_0 {} _K_ {} _K_ {} _K_ {} _OT_0 {} _OT_ {} _OT_ {} _OT_ {} _OT_ {} _OT_ {} _ {} _ {} _ {} _ {} _M_LK# {} _M_LK {} _W# {} # {} _M_LK# {} _M_LK {} _M_LK {} _M_LK# {} _M_ {} _OT_ {} _M_LK# {} _M_LK {} _M_LK# {} _M_LK {} _M[0..] {} _Q_[0..] {} _M[0..] {} _Q_[0..] {} ate: heet of Friday, March, 00 UTek omputer Inc. RLK-.0 P-VM O Tyler_Yuan ate: heet of Friday, March, 00 UTek omputer Inc. RLK-.0 P-VM O Tyler_Yuan ate: heet of Friday, March, 00 UTek omputer Inc. RLK-.0 P-VM O Tyler_Yuan FOR R FOR R FOR R FOR R FOR R FOR R FOR R FOR R VOH: 0.* VM VOL: 0.* VM FOR R NR0 9.Ohm NR0 9.Ohm NR.0KOhm NR.0KOhm NR KOhm NR KOhm N 0.UF/V N 0.UF/V TP TP NR 9.Ohm NR 9.Ohm NR 9.Ohm NR 9.Ohm N0 0.UF/V N0 0.UF/V NR KOhm NR KOhm N 0.UF/V N 0.UF/V N 0.0UF/0V N 0.0UF/0V N 0.UF/V N 0.UF/V N 0.UF/V N 0.UF/V NR 9.Ohm NR 9.Ohm NR9 KOhm NR9 KOhm TP TP M_0 0 M_ Y M_ M_ M_ Y M_ M_ M_ M_ W M_9 M_0 M_ Y M_ 0 M_ Y M_ 9 Q_0 P Q_0# P M_0 N Q_0 M Q_ N Q_ R Q_ R Q_ L Q_ M Q_ R Q_ R Q_ W Q_# W M_ W Q_ V Q_9 V Q_0 Q_ Q_ U Q_ U Q_ Y Q_ Y Q_ Y Q_# M_ Q_ Q_ Y Q_ 9 Q_9 9 Q_0 Q_ Q_ Q_ Y9 Q_ T0 Q_# U M_ N Q_ T Q_ R Q_ U Q_ T Q_ P Q_9 N Q_0 P0 Q_ V0 Q_ R Q_# R0 M_ U Q_ V Q_ U0 Q_ P Q_ N9 Q_ V0 Q_ V Q_ R Q_9 P Q_ L Q_# L0 M_ M Q_0 N Q_ M9 Q_ K Q_ K Q_ N0 Q_ N Q_ L Q_ L9 Q_ Q_# M_ 0 Q_ J0 Q_9 H Q_0 F9 Q_ 0 Q_ J Q_ J Q_ F Q_ F Q_ Q_# M_ 0 Q_ 0 Q_ Q_ Q_9 0 Q_0 Q_ Q_ 9 Q_ W_# _# W R_# Y _0 _ Y _ Y0 _0# _# Y _# _# K_0 Y9 K_ W K_ 9 K_ OT_0 OT_ OT_ OT_ 9 LK_0 R LK_ P LK_ V LK_ P9 LK_ M LK_ T LK_0# U LK_# N LK_# W LK_# P LK_# M LK_# U MROMPVOH M0 MROMPVOL M MRMRT RV N R_ NU RLK R_ NU RLK N9 0.0UF/0V N9 0.0UF/0V M_0 W M_ M_ M_ Y M_ M_ M_ W M_ M_ M_9 Y M_0 M_ Y M_ M_ Y M_ W_# _# W R_# Y _0 _ Y _ Y _0# _# 9 _# _# 0 K_0 W K_ K_ 0 K_ 0 OT_0 OT_ W9 OT_ OT_ Y9 LK_0 W LK_0# V LK_ U LK_# T LK_ V LK_# T LK_ R9 LK_# U9 LK_ V9 LK_# W LK_ N LK_# P RRV9 M Q_0 V Q_0# U M_0 R Q_0 N Q_ N Q_ W Q_ W Q_ N Q_ N Q_ N9 Q_ U Q_ R Q_# P M_ W9 Q_ T Q_9 U Q_0 P Q_ R Q_ R Q_ U9 Q_ V Q_ U Q_ P Q_# R M_ W Q_ U Q_ V Q_ U Q_9 T Q_0 U Q_ M Q_ V Q_ W Q_ T Q_# U M_ P Q_ V Q_ T Q_ T Q_ P Q_ U Q_9 W Q_0 R Q_ N Q_ W9 Q_# U9 M_ U Q_ W Q_ V Q_ N Q_ N Q_ U Q_ R Q_ N Q_9 R Q_ L Q_# L M_ M Q_0 M Q_ M Q_ J Q_ L Q_ R9 Q_ M Q_ L Q_ L Q_ Q_# M_ 9 Q_ Q_9 J Q_0 F Q_ F Q_ J Q_ J Q_ Q_ F Q_ Q_# M_ Q_ Q_ Q_ Q_9 Q_0 Q_ F Q_ Q_ ROMPXP ROMPYP W RRV N RRV M RRV RRV F LWX P LWY 9 ROMPXP L ROMPYPU 0 ROMPYP 0 VRF M ROMPXPU L R_ NU RLK R_ NU RLK NR KOhm NR KOhm

NU.V {} N_L0_R {} N_L_R {} N_L_R 0 J0 J L0 L L RT_HYN RT_VYN V_HYN {} V_VYN {} NR.KOhm {} N_TPV_MH_XP_N N_XP_LR N_RFU_ N_N K0 F0 J 0 LLZTT XORTT MTYP XP_M XP_LR RFU_0 N RT_R RT_RN RT_LU RT_R# RT_RN# RT_LU# 9 0 9 0 V_R {} V_RN {} V_LU {} NR KOhm NR KOhm PULL OWN FOR IL MT NR KOhm V RT T RT LK L M V T {} V LK {} Pin MTYP XP_LR XP_N TN K RRV9 H RRV0 L RRV N RRV N RRV N RRV L RRV L RRV M RRV U0 RRV9 U RRV0 R9 RRV R0.V_L RRV U RRV U RRV ONTROL LINK RFRN R RRV R RRV 0 RRV 9 RRV NR0 RRV9 Y K RRV0 F % RRV RRV.V N_LINK_VRF L NR RRV M 9 N RRV % 0.UF/V M N_LINK_T L_VRF {} N_LINK_T N_LINK_LK L_T {} N_LINK_LK N_LINK_RT# L_LK {} N_LINK_RT# {,,} O_PWROK L_RT# M NR /nonmt L_PWROK TUFF FOR NON MT N_L_PWROK NR /MT H L R R NORM RVR ONURRNT NON-ONURRNT NL IL TUFF FOR MT N_L_PWROK_R {} Y R # 9 R M0 R W# W R OT RIPTION MMORY TYP PI-XPR LN RVRL PI- / VO O-XITN RLK TL ONFINTILITY MI RT_IRF RFLKINP RFLKINN N N N N N N N N N9 N0 RTIN# PWROK IH_YN# F_O RV RV RV 0 N0 M M J R0 N_RT_IRF _PLTRT# N_IH9_YN# NR.KOhm.V When non-raphics, install it. Place near MH. N_IH9_YN# {} NR 0KOhm r00_h /nonrph NR9 0KOhm r00_h /nonrph.v_l _PLTRT# {0,,0,9,} O_PWROK {,,} K_9M_RF {} K_9M_RF# {} V NR KOhm /MT N UF/V/00 /MT NR 0KOhm /MT NR LINK PWROK NRTION.9KOhm /MT NR0 0KOhm /MT NR.KOhm PU /MT VOUT V VIN- VOUT VIN VIN- VIN LMVIR {,,,} V UTek omputer Inc. _LP_M N_L_PWROK NR Ohm /MT P-VM O RLK- Tyler_Yuan ate: Friday, March, 00 heet of NR NR KOhm /MT KOhm /MT NQ PM90 /MT.0

PV_MPLL PV_PLL VQ_RT PV_PLL PV_PLL_R TP_MH_V_HPLL PV_MPLL_R PV_HPLL PV_PLL V_V_RT.V_L.V.V.V P_V_.V_L.V.V.V_L.V V V ate: heet of Friday, March, 00 UTek omputer Inc. RLK-.0 P-VM O Tyler_Yuan ate: heet of Friday, March, 00 UTek omputer Inc. RLK-.0 P-VM O Tyler_Yuan ate: heet of Friday, March, 00 UTek omputer Inc. RLK-.0 P-VM O Tyler_Yuan NR Ohm NR Ohm NL 0.UH NL 0.UH NL 0 NL 0 N.UF/.V c00 N.UF/.V c00 N 0.0UF/0V N 0.0UF/0V N 0.UF/V N 0.UF/V N 0UF/.V N 0UF/.V N UF/0V N UF/0V NR r00 NR r00 N 0.UF/V N 0.UF/V N UF/0V c00 N UF/0V c00 N.UF/.V N.UF/.V NR Ohm NR Ohm N UF/V N UF/V N 0.UF/V N 0.UF/V NR9 r00 NR9 r00 N UF/0V N UF/0V NR Ohm NR Ohm N9.UF/.V N9.UF/.V N9 UF/V N9 UF/V NL UH NL UH N0 0.UF/V N0 0.UF/V V_90 F V_9 F V_ F V_ V_ V_ V_ 9 V_0 V_99 V_9 V_9 V_9 V_9 F V_9 F V_9 F V_9 F V_9 F0 V_0 V_0 V_00 V_0 V_0 V_0 V_0 V_ V_ V_0 V_09 V_0 V_0 V_ Y V_ Y V_ V_ V_ V_ W V_0 Y V_9 Y V_ Y V_ V V_ V V_ W V_ W V_ W V_ V0 V_ V V_ V V_0 V V_9 V V_ V V_0 U V_9 U V_ U V_ V V_ U V_ V9 V_ V V_ V V_ P V_ P V_ R V_0 R V_9 R V_ R V_ U V_ U V_ U V_ U9 V_ U0 V_ U V_ U V_ F V_ V_ J V_ J V_ J V_0 L V_9 N V_ N V_ N V_ N9 V_ N V_ N V_9 9 V_ V_ V_ F9 V_ P0 V_L_PLL Y V_XPPLL V_HPLL V_MPLL V_PLL V_PLL V_IO V_ J V_ J V_ J0 V_ J9 V_ J V_ J V_ J V_ J V_9 H V_0 H V_ H V_ V_ V_ V_ 0 V_ 9 V_ V_9 V_0 V_ V_ V_ V_ V_ F V_ F V_ F V_ F V_9 F V_0 F V_ F V_ V_ V_ V_ 9 V_ V_ V_ 0 V_9 V_0 V_ V_ V_ 9 V_ V_ V_ V_ V_ V_9 0 V_0 V_ V_ V_ 9 V_ V_ V_ V_ Y V_ Y V_9 Y0 V_0 Y V_ Y V_ Y V_ W V_ W V_ W V_ W9 V_ V V_ V V_9 V V_ V0 V_ V9 V_ U V_ U V_ U0 V_ U9 V_ U V_ U V_9 V_RT V_RT V_XP V_RT VQ_RT V V_ V_ V_ 0 V_ V_HPLL V V_XPLL Y POWR NUF RLK POWR NUF RLK N.UF/.V c00 N.UF/.V c00 N.UF/.V N.UF/.V N0 UF/V N0 UF/V N.UF/.V c00 N.UF/.V c00 NL 0 NL 0 NL UH NL UH NR Ohm NR Ohm N UF/.V c00 N UF/.V c00 N 0UF/0V N 0UF/0V N UF/0V c00 N UF/0V c00 NR NR N 0UF/0V N 0UF/0V N9 UF/0V c00 N9 UF/0V c00 N 0UF/.V N 0UF/.V NL 0UH NL 0UH N0 UF/0V c00 N0 UF/0V c00 T T N UF/V N UF/V N 0.UF/V N 0.UF/V NR r00 NR r00 N.UF/.V c00 N.UF/.V c00 NL 0UH NL 0UH

.0 N.UF/.V N.UF/.V N.UF/.V N.UF/.V.VUL.V N N UF/0V UF/0V N 0.UF/V N9.UF/.V N 0.UF/V N.UF/.V N 0UF/.V N UF/0V N9 0.UF/V N.UF/.V N 0UF/.V VTTPU NU P9 VTT P VTT P VTT P VTT P VTT N9 VTT N VTT N VTT N VTT9 M9 VTT0 M VTT M VTT L VTT L VTT K VTT K VTT J VTT J VTT H VTT9 H VTT0 VTT VTT VTT F VTT F VTT F VTT 9 VTT VTT VTT9 VTT0 9 VTT VTT VTT 0 VTT 9 VTT VTT 0 VTT 9 VTT VTT9 VTT0 0 VTT VTT R VTT R VTT R VTT R VTT 9 VM VM 0 VM VM VM VM VM 9 VM VM9 VM0 VM VM VM 0 VM VM VM VM Y VM W VM9 W0 VM0 V VM V VM V_XP 0 V_XP 9 V_XP V_XP V_XP V_XP V_XP V_XP V_XP9 V_XP0 V_XP V_XP V_XP V_MLK V_MLK V_MLK V_MLK V_MLK V_L V_L V_L V_L V_L V_L V_L V_L V_L9 V_L0 V_L V_L V_L V_L V_L V_L V_L V_L V_L9 V_L0 V_L V_L V_L V_L V_L V_L V_L V_L V_L9 V_L0 V_L V_L V_L V_L V_L V_L V_L V_L V_L9 V_L0 V_L V_L V_L V_L V_L V_L9 V_L0 V_L V_L V_L V_L V_L V_L V_L V_L V_L9 V_L0 V_L V_L V_L V_L V_L V_L V_L V_L V_L9 V_L V_L V_L V_L V_L V_L V_L V_L V_L0 V_L V_L9 V9 V9 Y L L L0 L9 L L L L J J J K K K K K0 K K K K K K J Y J J J J J0 J J J J 0 9 Y0 Y9 V0 L K L9 L L L L L L0 L L L K K0 K9 J F J0 J9 J 0 9 F0 F9 F 0 9 0 9 L J.V_L V_KR N 0.UF/V N0 0.UF/V c00 Please use 0900 NR0 NR N 0UF/.V NL UH N 0UF/.V V_KR_R N 0UF/.V.VUL N 0.UF/V N UF/.V RLK UTek omputer Inc. P-VM O RLK- Tyler_Yuan ate: Friday, March, 00 heet 9 of.0

ate: heet of 0 Friday, March, 00 UTek omputer Inc. RLK-.0 P-VM O Tyler_Yuan ate: heet of 0 Friday, March, 00 UTek omputer Inc. RLK-.0 P-VM O Tyler_Yuan ate: heet of 0 Friday, March, 00 UTek omputer Inc. RLK-.0 P-VM O Tyler_Yuan V9 L V9 L V9 K V9 J9 V9 J V9 J V99 H V00 V0 V0 F V0 F V0 F V0 F0 V0 F9 V0 F V0 F V09 F V0 F V V V 0 V V V V V 9 V9 V0 V V V V V 9 V V V V9 V0 0 V 0 V V V V V V V 9 V9 V0 V V V V V 0 V V V Y V9 Y V V V V Y0 V F V F V F9 V V9 V0 V V9 V U9 V U V R V V V V V9 V0 V V V V V 0 V V V Y V9 Y V0 W V W V V V V V0 M0 V0 M V0 M V0 M0 V09 M V0 M V L0 V L V L V L V L9 V L V L0 V L V9 L V0 L V L V K V K V K V K V K V K V K V9 J V0 J V J V J V J V J9 V J V J V H V H9 V9 H V0 H0 V H V H V H V V V V V V9 V0 V 9 V V V F V F V F V F V F V9 F V0 F V V V V V V 9 V P V P V9 V 0 V V V V V V V V V9 V0 V V V V V V V 9 V V9 0 V90 9 V9 V9 V9 V0 Y V V V V V V V V V V V9 V9 V0 V V V V U V U V U V U V U0 V U V U V9 T V0 T9 V T V T V T V R V R V R V R V R V9 R V0 R V R0 V R V R9 V R V P V P V P V P V9 N V N V N9 V N V N V N0 V N V N V N V N V9 N V0 M V M0 V M V M V M9 V M V M V M0 V M V9 M9 V90 V9 M V9 M V0 M V0 M V0 M V0 M V R V R V R V0 R V9 T V T V U V U V U V U V00 M V99 N V9 N V9 N0 V9 N V9 N V9 N V9 N V9 N V9 N V90 P V9 P V P0 V P V R V R V R V Y V Y V Y V Y V Y9 V Y0 V Y V Y V9 Y V0 W V W V W0 V W V V V V9 V V V V V V V9 V V V V V V V V U V9 NUH RLK NUH RLK LIP NL_ LIP NL_ N_H HTINK N_H HTINK LIP NL_ LIP NL_ LIP NL_ LIP NL_ LIP NL_ LIP NL_

{} _Q_[0:] {} _M[0:] OLOR: YLLOW TYP: old Flash IMM_ {} _Q_[0:] {} _M[0:] OLOR: LK TYP : old Flash IMM_ For one channel use. elete this block If you want to design one channel. 0.F eta _M0 _Q M 0 Q _Q M Q _Q M Q 0 _Q_0 _M Q0 9 _Q_9 _M Q9 0 _Q M Q 0 _Q M Q _Q M Q 0 9 _Q M9 Q _Q_ y chipset support, _M0 9 Q _Q M 0/P Q Plz ref chipset _Q M Q spec _Q_ y chipset support _M Q 0 9 _Q_0 _M Q0 0 _Q_9 {} _M Q9 99 {} _M _Q_ Q 9 _Q_ Q _Q_ {} _M_LK 0 KP Q {} _M_LK _Q_ {} _M_LK# KN Q 09 {} _M_LK# _Q_ {} _M_LK KP Q 0 {} _M_LK _Q_ {} _M_LK# KN Q 9 {} _M_LK# _Q_ {} _M_LK0 K0P Q 9 {} _M_LK _Q_ {} _M_LK#0 K0N Q 90 {} _M_LK# _Q_0 Q0 9 _Q_9 Q9 0 _Q_ {} # # Q 0 {} # _Q_ {} #0 9 0# Q 00 {} # _Q_ Q 99 _Q_ Q _Q_ {} _OT_ OT Q {} _OT Q_ {} _OT_0 9 OT0 Q {} _OT Q_ Q 0 _Q_ Q 9 _Q_0 Q0 _Q_9 Q9 _Q_ {} _W# W# Q {} _W# _Q_ {} _R# 9 R# Q 0 {} _R# _Q_ {} _# # Q 9 {} _# _Q_ Q _Q_ Q _Q_ Q 0 _Q_ {} _ / Q 9 {} Q_ {} _ 90 Q {} Q_0 {} _0 0 Q0 {} _0 _Q_9 Q9 _Q_ Q 0 _Q_ {} _K_ K Q {} _K Q_ {} _K_0 K0 Q {} _K Q_ Q _Q_ Q 0 ddress 0 _Q_ Q _Q_ Q 0 _Q_ Q 0 _Q_0 Q0 9 _Q_9 0 Q9 _Q_ Q _Q_ Q 9 _Q_ Q _Q_ Q _Q_ {} _Q_ QP Q {} _Q Q_ {} _Q_# QN Q 0 {} _Q_# _Q_ {} _Q_ 0 QP Q 9 {} _Q Q_ {} _Q_# 0 QN Q {} _Q_# _Q_0 {} _Q_ 9 QP Q0 {} _Q_ {} _Q_# 9 QN {} _Q_# {} _Q_ QP {} _Q_ {} _Q_# QN {} _Q_# {} _Q_ QP N/ {} _Q_ {} _Q_# QN N/ {} _Q_# {} _Q_ QP N/ {} _Q_ {} _Q_# QN N/ {} _Q_# {} _Q_ QP N/ 9 {} _Q_ {} _Q_# QN N/ {} _Q_# {} _Q_0 Q0P N/ {} _Q_0 {} _Q_#0 Q0N N/0 {} _Q_#0 {} _M_ {} _M_ {} _M_ {} _M_ {} _M_ {} _M_ {} _M_ {} _M_0,,,0,} _MLK_MIN,,,0,} _MT_MIN M/QP N/QP M/QP N/QN M/QP 0 M/QP M/QP M/QP M/QP M/Q0P M0/Q9P 0 L 9 {} _M_ {} _M_ {} _M_ {} _M_ {} _M_ {} _M_ {} _M_ {} _M_0 {,,,0,} _MLK_MIN {,,,0,} _MT_MIN _M0 _M _M _M _M _M 0 _M 0 _M _M 9 _M9 _M0 _M _M _M 9 _M 0 9 9 9 90 ddress.v_l 0 0 9 0 0 9 9 0 0 9 0 9 0/P KP KN KP KN K0P K0N # 0# OT OT0 W# R# # / 0 K K0 0 QP QN QP QN QP QN QP QN QP QN QP QN QP QN Q0P Q0N L Q Q Q 0 Q0 9 Q9 Q Q Q 0 Q Q Q Q Q 0 Q0 0 Q9 99 Q 9 Q Q Q 09 Q 0 Q 9 Q 9 Q 90 Q0 9 Q9 0 Q 0 Q 00 Q 99 Q Q Q Q 0 Q 9 Q0 Q9 Q Q 0 Q 9 Q Q Q 0 Q 9 Q Q0 Q9 Q 0 Q Q Q Q 0 Q Q Q Q0 Q9 Q Q 9 Q Q Q Q 0 Q 9 Q Q0 N/ N/ N/ N/ N/ 9 N/ N/ N/0 M/QP N/QP M/QP N/QN M/QP M/QP M/QP M/QP M/QP M/Q0P M0/Q9P _Q Q Q Q_0 _Q_9 _Q Q Q Q Q Q Q Q Q_0 _Q_9 _Q Q Q Q Q Q Q Q Q_0 _Q_9 _Q Q Q Q Q Q Q Q Q_0 _Q_9 _Q Q Q Q Q Q Q Q Q_0 _Q_9 _Q Q Q Q Q Q Q Q Q_0 _Q_9 _Q Q Q Q Q Q Q Q Q_0 V {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} _M0 _M _M _M _M _M _M _M _M _M9 _M0 _M _M _M {} y chipset support, Plz ref chipset spec _R# _# _W# _0 {} # {} # {} _K_ {} _K_ {} _OT_ {} _OT_ {} # {} #0 {} _K_ {} _K_0 {} _OT_ {} _OT_0 _M _MLK_MIN 00 RN Ohm RN Ohm RN Ohm RN Ohm RN Ohm RN Ohm Ohm RN RN Ohm RN Ohm RN Ohm RN Ohm RN Ohm 00 RN Ohm RN Ohm 00 RN Ohm RN Ohm RN Ohm 00 RN Ohm RN Ohm RN Ohm RN Ohm 00 RN Ohm RN Ohm For one channel use. You can delete these blocks and reseve "RN" If you want to design one channel of IMM. V99W R _MT_MIN PF/0V V99W /R Ohm r00 RN Ohm RN Ohm RN Ohm 00 RN Ohm RN Ohm RN Ohm RN Ohm RN Ohm RN Ohm Mus Ps Placed close to IMM PF/0V /R VTTR 0 N/QN N/QN N/QN N/QN N/QN N/QN N/QN N/Q0N N/Q9N R_IMM_0P RT# R0 NP_N NP_N NP_N N0 N N 9 0 0 N/QN N/QN N/QN N/QN N/QN N/QN N/QN N/Q0N N/Q9N R_IMM_0P RT# R0 NP_N NP_N NP_N N0 N N 9 0 U TeK omputer IN P-VM O RII hannel Makishin Huang ate: Friday, March, 00 heet of 0.F

{} _Q_[0:] {} _M[0:] OLOR: YLLOW TYP : old Flash IMM_ {} _Q_[0:] {} _M[0:] OLOR: LK TYP : OL FLH IMM_ For one channel use. elete this block If you want to design one channel. 0.F eta _M0 _Q M0 _Q M 0 Q _Q M 0 Q _Q M Q _Q M Q _Q M Q 0 _Q_0 _M Q 0 _Q_0 _M Q0 9 _Q_9 _M Q0 9 _Q_9 _M Q9 _Q M Q9 0 _Q M Q 0 _Q M Q 0 _Q M Q 0 _Q M Q _Q M Q 0 _Q M Q 0 {} _M0 9 _Q M9 Q 9 _Q M9 Q {} _M _Q M0 9 Q _Q M0 9 Q {} _M _Q M 0/P Q _Q M 0/P Q {} _M _Q M Q _Q M Q y chipset support _Q M Q 0 _Q_0 _M Q 0 {} _M 9 _Q_0 _M Q0 0 9 _Q_9 _M Q0 0 {} _M _Q_9 {} _M Q9 99 {} _M {} _M _Q_ Q9 99 _Q_ Q 9 _Q_ Q 9 {} _M _Q_ Q _Q_ Q _Q_ {} _M_LK 0 KP Q {} _M_LK 0 _Q_ KP Q {} _M _Q_ {} _M_LK# KN Q 09 {} _M_LK# {} _M9 _Q_ KN Q 09 _Q_ {} _M_LK KP Q 0 {} _M_LK {} _M0 _Q_ KP Q 0 _Q_ {} _M_LK# KN Q 9 {} _M_LK# _Q_ KN Q 9 {} _M _Q_ {} _M_LK0 K0P Q 9 {} _M_LK _Q_ K0P Q 9 _Q_ {} _M_LK#0 K0N Q 90 {} _M_LK# {} _M _Q_0 K0N Q 90 _Q_0 Q0 9 _Q_9 Q0 9 _Q_9 Q9 0 _Q_ Q9 0 _Q_ {} # # Q 0 {} # _Q_ # Q 0 {} _M _Q_ {} #0 9 0# Q 00 {} # 9 _Q_ 0# Q 00 _Q_ Q 99 _Q_ Q 99 _Q_ Q _Q_ Q _Q_ {} _OT_ OT Q {} _OT Q_ OT Q _Q_ {} _OT_0 9 y chipset support, OT0 Q {} _OT_ 9 _Q_ OT0 Q _Q_ Q 0 _Q_ Q 0 Plz ref chipset _Q_ Q 9 _Q_0 Q 9 spec _Q_0 Plz keep RN0 if you Q0 _Q_9 Q0 _Q_9 Q9 delete R & net _Q_ Q9 _Q_ {} _W# W# Q {} _W# "_M / " _Q_ W# Q _Q_ {} _R# 9 R# Q 0 {} _R# 9 _Q_ R# Q 0 _Q_ {} _# # Q 9 {} _# _Q_ # Q 9 _Q_ Q _Q_ Q _Q_ Q {} _0 _Q_ Q _Q_ Q 0 {} Q_ Q 0 _Q_ {} _ / Q 9 {} _ {} Q_ / Q 9 _Q_ {} _ 90 Q {} _ 90 _Q_0 Q _Q_0 {} _0 0 Q0 {} _0 _Q_9 0 Q0 _Q_9 Q9 _Q_ Q9 _Q_ Q 0 _Q_ Q 0 _Q_ {} _K_ K Q {} _K_ {} # _Q_ K Q _Q_ {} _K_0 K0 Q {} _K_ {} # _Q_ K0 Q _Q_ Q {} _K_ ddress _Q_ Q ddress _Q_ Q 0 {} _K Q_ Q 0 _Q_.V_L Q _Q_.V_L Q _Q_ Q _Q_ Q 0 0 _Q_ Q {} _OT Q_0 Q 0 0 _Q_0 Q0 {} _OT Q_9 Q0 9 9 _Q_9 0 Q9 _Q_ 0 Q9 _Q_ Q _Q_ Q _Q_ Q 9 _Q_ Q 9 _Q_ Q _Q_ Q _Q_ Q _Q_ Q _Q_ {} _Q_ QP Q {} _Q Q_ QP Q _Q_ {} _Q_# QN Q 0 {} _Q_# _Q_ QN Q 0 _Q_ {} _Q_ 0 QP Q 9 {} _Q_ 0 _Q_ QP Q 9 _Q_ {} _Q_# 0 QN Q {} _Q_# 0 _Q_0 QN Q _Q_0 {} _Q_ 9 QP Q0 {} _Q_ 9 QP Q0 {} _Q_# 9 QN {} _Q_# 9 QN {} _Q_ QP {} _Q_ QP {} _K_ {} _Q_# QN {} _Q_# QN {} _K_0 {} _Q_ QP N/ {} _Q_ QP N/ {} _OT_ {} _Q_# QN N/ {} _Q_# QN N/ {} _OT_0 {} _Q_ QP N/ {} _Q_ QP N/ {} # {} _Q_# QN N/ {} _Q_# QN N/ {} #0 {} _Q_ QP N/ 9 {} _Q_ QP N/ 9 {} _Q_# QN N/ {} _Q_# QN N/ {} _Q_0 Q0P N/ {} _Q_0 Q0P N/ {} _M {} _Q_#0 Q0N N/0 {} _Q_#0 Q0N N/0 {} _# {} _W# {} _R# {} _M_ M/QP N/QP {} _M_ M/QP N/QP {} _M_ M/QP N/QN {} _M_ M/QP N/QN {} _M_ M/QP {} _M_ M/QP {} _M_ 0 M/QP {} _M_ 0 M/QP {} _M_ M/QP M/QP {} _M_ M/QP M/QP {} _M_ M/QP {} _M_ M/QP {} _M_ M/Q0P {} _M_ M/Q0P {} _M_0 M0/Q9P {} _M_0 M0/Q9P y chipset support, Plz ref chipset spec {,,,0,} _MLK_MIN {,,,0,} _MT_MIN 0 L 9 {,,,0,} _MLK_MIN {,,,0,} _MT_MIN 0 L 9 00 RN Ohm RN9 Ohm RN9 Ohm RN9 Ohm RN9 Ohm RN Ohm RN Ohm RN Ohm RN Ohm RN0 Ohm RN Ohm RN0 Ohm RN0 Ohm 00 Ohm RN0 00 RN Ohm RN Ohm R Ohm r00 00 RN Ohm RN Ohm RN Ohm RN Ohm RN Ohm RN Ohm For one channel use. You can delete these blocks and reseve "RN" If you want to design one channel of IMM. 00 RN Ohm RN Ohm RN Ohm RN Ohm RN Ohm RN Ohm RN Ohm RN Ohm RN Ohm RN Ohm VTTR 0 N/QN N/QN N/QN N/QN N/QN N/QN N/QN N/Q0N N/Q9N R_IMM_0P RT# R0 NP_N NP_N NP_N N0 N N 9 0 0 N/QN N/QN N/QN N/QN N/QN N/QN N/QN N/Q0N N/Q9N R_IMM_0P RT# R0 NP_N NP_N NP_N N0 N N 9 0 U TeK omputer IN P-VM O RII hannel Makishin Huang ate: Friday, March, 00 heet of 0.F

If you don't use MM_WRN, please connect PIN to. 0.UF/V /R 0.UF/V _VRF_IMM.VUL _VRF_IMM IMM_ 9 V0 VQ9 9 9 V9 VQ V VQ V VQ V VQ V VQ 9 V VQ V VQ V VQ 9 V VQ0 V0 VQ0 9 0 09 9 0 0 0 9 00 9 9 9 9 0 0 0 0 9 9 0 0 9 9 9 0 0 0 9 9 0 9 9 0 0 0 VRF R_IMM_0P VP.VUL IMM_ 9 V0 VQ9 9 9 V9 VQ V VQ V VQ V VQ V VQ 9 V VQ V VQ V VQ 9 V VQ0 V0 VQ0 9 0 09 9 0 0 0 9 00 9 9 9 9 0 0 0 0 9 9 0 0 9 9 9 0 0 If you don't use MM_WRN, 0 please 9 9 connect 0 PIN to 9 9 0. 0 0 VRF R_IMM_0P VP W/ = 0/0.VUL If you don't use MM_WRN,please connect PIN to. 0.UF/V.VUL IMM_: LOT TO PU OLOR: YLLOW TYP : OL FLH.V_L R KOhm.V_L /R.VUL W/ = 0/0 _VRF_IMM IMM_ OLOR: YLLOW TYP : OL FLH If you don't use MM_WRN, please connect PIN to. IMM_ OLOR: LK TYP : OL FLH IMM_ FURTHT FROM PU OLOR: LK TYP : OL FLH If you don't use MM_WRN,please connect PIN to. 0.UF/V R KOhm 0.UF/V 0.UF/V /R If you don't use MM_WRN, please connect PIN to. 9 0.UF/V /R 0 UF/0V c00.vul 0 :R.0:Regin _VRF_IMM IMM_ 9 V0 VQ9 9 9 V9 VQ V VQ V VQ V VQ V VQ 9 V VQ V VQ V VQ 9 V VQ0 V0 VQ0 9 0 09 9 0 0 0 9 00 9 9 9 9 0 0 0 0 9 9 0 0 9 9 9 0 0 0 9 9 0 9 9 0 0 0.VUL VTTR If you don't use MM_WRN,please connect PIN to..v_l.v_l 0.UF/V /R.VUL.VUL.VUL IMM_ 9 V0 VQ9 9 9 V9 VQ V VQ V VQ V VQ V VQ 9 V VQ V VQ V VQ 9 V VQ0 V0 VQ0 9 0 09 9 0 0 0 9 00 9 9 9 9 0 0 0 0 9 9 0 0 9 9 9 0 0 0 9 9 If you don't use 0 9 9 MM_WRN,please 0 connect PIN to. 0 0 VRF R_IMM_0P VRF VP VP R_IMM_0P 0.UF/V 0.UF/V mb_c00 0.UF/V mb_c00 0.UF/V mb_c00 0.UF/V mb_c00 0.UF/V mb_c00 0.UF/V mb_c00.vul 0.UF/V mb_c00 0.UF/V mb_c00 0.UF/V mb_c00 0 0.UF/V mb_c00 hannel 0.UF/V mb_c00 0.UF/V mb_c00 hannel For one channel use. elete this block If you want to design one channel..:ll of "" must be confirm 0.UF/V mb_c00 0.UF/V mb_c00 0.UF/V mb_c00 0.UF/V mb_c00 0.UF/V /R mb_c00 0.UF/V /R mb_c00 0.UF/V /R mb_c00 0.UF/V /R mb_c00 0.UF/V mb_c00 0.UF/V mb_c00 0.UF/V /R mb_c00 9 0.UF/V /R mb_c00 0.UF/V /R mb_c00 0.UF/V /R mb_c00 0.UF/V mb_c00 0.UF/V mb_c00 U TeK omputer IN VTTR 0.UF/V mb_c00 0 0.UF/V mb_c00 9 0.UF/V /R mb_c00 0.UF/V /R mb_c00 0.UF/V mb_c00 0.UF/V mb_c00 0.UF/V /R mb_c00 hannel 9 0.UF/V mb_c00 0.UF/V mb_c00 0 0.UF/V /R mb_c00 hannel 9 0.UF/V mb_c00 0.UF/V mb_c00 P-VM O 0.F eta hannel hannel hannel hannel RII (Power) Makishin Huang ate: Friday, March, 00 heet of 0 0.UF/V /R mb_c00 0.UF/V /R mb_c00 tandard ircuit RII lottermination RV. RII 9 0UF/0V /R mb_c00 0UF/0V /R mb_c00 0.UF/V /R mb_c00 0.UF/V /R mb_c00 _0.F eta 0 0UF/0V /R mb_c00 0UF/0V /R mb_c00 0.F

For Intel earlake hipset V 0. eta tandard ircuit V RLK RV. V_0. T V_RLK /V {} V_R {} V_RN {} V_LU V0 0PF/0V /V Place near connector side Place near N side V 0PF/0V /V V 0PF/0V /V VR mb_r00 % VR mb_r00 % VR mb_r00 % VR mb_r00 % VR mb_r00 % V V99W /V V V99W /V V V99W /V V 0PF/0V V 0PF/0V VLX VLX VLX V 0PF/0V 0.0uH V 0.UF/V mb_c00 /V V_R_L V_RN_L V_LU_L V PF/0V VL /00Mhz mb_l00 V_R_L V_LU_L V_HYN_R V_V_L V_V_F V_RN_L V T_R V_VYN_R V LK_R V_V Right ngle (efault) V V V_V V V99W /V V_V VR.KOhm V {} V T V T_Q VR V T_R VQ V HN0 0 V 00PF/0V /V {} V LK VR mb_r00 % 0.0uH 0.0uH V9 V0 PF/0V PF/0V V_V_L V 0.UF/V mb_c00 VF./V V R N RN T LU HYN 9 V N VYN 0 LK I_ I_ PR V VR.KOhm VR.KOhm VR0.KOhm V V99W /V V LK_Q VR9 V LK_R VQ HN0 0 V 00PF/0V /V V mb_r00 VR {} {} V_HYN V_VYN V 0.UF/V mb_c00 V V VU NHTR /V VU NHTR /V mb_r00 VR V_HYN_U V_VYN_U VRX Ohm VRX Ohm V_VYN_R V_HYN_R V 00PF/0V /V V 00PF/0V /V V V VU NHTR /V V 0 V 9 VU NHTR /V UTek omputer Inc. Onboard V(L).W. Huang P-VM O ate: Friday, March, 00 heet of 0.

.For single I LN U_U0_V_L 0 Left L:. ORN : ctivity LN U U Right L:. RN : 000Mbps. ORN : 00Mbps. No Light : 0Mbps L_TLP {9} L_TLN {9} V0 L LP0- L- LP0 L P_ V P_ LP- P_ LP P_ P_ 9 9 V P_ 0 0 P_ L- P_ LN_ V T- L_MI_- {9} V T L_MI_ {9} {,} U_U-_R P- T- L_MI_- {9} {,} U_U0-_R P- T L_MI_ {9} {,} U_U_R P T- L_MI_- {9} {,} U_U0_R P T L_MI_ {9} T- L_MI_0- {9} T 0 L_MI_0 {9} TR 9 L_TR {9} U LN_U LN0 LN LN U U 9 LN9 U TLP TLN LILN 0 LILP 9 LN_ON_U L_LINK000# {9} L_LINK00# {9} P L:. RN : 000Mbps. ORN : 00Mbps. No Light : 0Mbps {,} U_U-_R {,} U_U_R {,} U_U-_R {,} U_U_R {} U_U_V_L Z_9P0_V F_U Z_TP0- UX_9_ON_P 9 U U 0. eta Z_TP0 {} Z_TP0- {} Z_TP0 {} tandard ircuit xternal 9/LNU/ onnecter T/U RV. onnecter 0. eta XTRNL_ONNTR UTK omputer IN P-VM O onnector Makishin_Huang ate: Friday, March, 00 heet of 0.

PIX_ 0.F eta 若若若請 LOT_WRN 請線, 請請 X_X_T_ 接接. X_WK# 是需端 Pull-high {,,,} _MLK_PI {,,,} _MT_PI {,} X_WK# efault :lue,/f,latch 往不 V V V V V 若要若請 U 請 LOT, 請 R 自自自自 V_ PRNT# 料料 :V0UU V_ V_ RV V_ MLK JT MT JT JT X.V_ JT X 9 PF/0V JT.V_ 9 PF/0V 0 /PI.Vaux.V_ 0 /PI O_PIRT#_PIX {} WK# PWR V V NP_N NP_N V () 如有若請, 是需端以.K OhmPull high 接 V. () 若不若請, 請 R 請將接接, 不不 floating, 並請並並是是是要 Pull high or pull down. () 若 hipset 有 support VO, 請 R 自自自改 Netname. 沒有若請請 Net 請接接, 不不 floating. {} X_VO_LK {} X_VO_T {} N_TPV_MH_XP_N 若若若請 LOT_WRN 請線, 請請 X_X_T_[:] 接接. {} X_X_TXP0 {} X_X_TXN0 {} X_X_TXP {} X_X_TXN {} X_X_TXP {} X_X_TXN {} X_X_TXP {} X_X_TXN {} X_X_TXP {} X_X_TXN {} X_X_TXP {} X_X_TXN {} X_X_TXP {} X_X_TXN {} X_X_TXP {} X_X_TXN {} X_X_TXP {} X_X_TXN {} X_X_TXP9 {} X_X_TXN9 {} X_X_TXP0 {} X_X_TXN0 {} X_X_TXP {} X_X_TXN {} X_X_TXP {} X_X_TXN {} X_X_TXP {} X_X_TXN {} X_X_TXP {} X_X_TXN {} X_X_TXP {} X_X_TXN XX XX XX XX XX9 XX XX XX XX XX9 XX XX XX XX XX9 XX 0.UF/V mb_c00 0.UF/V mb_c00 0.UF/V mb_c00 0.UF/V mb_c00 0.UF/V mb_c00 0.UF/V mb_c00 0.UF/V mb_c00 0.UF/V mb_c00 0.UF/V mb_c00 0.UF/V mb_c00 0.UF/V mb_c00 0.UF/V mb_c00 0.UF/V mb_c00 0.UF/V mb_c00 0.UF/V mb_c00 0.UF/V mb_c00 mb_c00 XX 0.UF/V mb_c00 XX 0.UF/V mb_c00 XX 0.UF/V mb_c00 XX 0.UF/V mb_c00 XX0 0.UF/V mb_c00 XX 0.UF/V mb_c00 XX 0.UF/V mb_c00 XX 0.UF/V mb_c00 XX 0.UF/V mb_c00 XX0 0.UF/V mb_c00 XX 0.UF/V mb_c00 XX 0.UF/V mb_c00 XX 0.UF/V mb_c00 XX 0.UF/V mb_c00 XX0 0.UF/V mb_c00 XX 0.UF/V X_X_TXP0_ X_X_TXN0_ X_X_TXP_ X_X_TXN_ X_X_TXP_ X_X_TXN_ X_X_TXP_ X_X_TXN_ X_X_TXP_ X_X_TXN_ X_X_TXP_ X_X_TXN_ X_X_TXP_ X_X_TXN_ X_X_TXP_ X_X_TXN_ X_X_TXP_ X_X_TXN_ X_X_TXP9_ X_X_TXN9_ X_X_TXP0_ X_X_TXN0_ X_X_TXP_ X_X_TXN_ X_X_TXP_ X_X_TXN_ X_X_TXP_ X_X_TXN_ X_X_TXP_ X_X_TXN_ X_X_TXP_ X_X_TXN_ 9 0 9 0 9 0 9 0 9 0 9 9 0 RV HOP0 HON0 PRNT_# HOP HON HOP HON 9 HOP HON 0 RV PRNT_# HOP HON HOP HON HOP HON HOP HON PRNT_# 9 HOP HON 0 HOP9 HON9 HOP0 HON0 HOP HON HOP HON 9 HOP HON 0 HOP HON HOP HON PRNT_# RV PI_XPR_X RFLK RFLK- HIP0 HIN0 RV 9 HIP HIN 0 HIP HIN HIP HIN RV RV HIP HIN HIP HIN 9 HIP HIN 0 HIP HIN RV9 HIP HIN HIP9 HIN9 HIP0 HIN0 9 HIP HIN 0 HIP HIN HIP HIN HIP HIN HIP HIN 9 0 9 0 9 0 9 0 9 0 9 9 0 _PIX_ {} _PIX#_ {} X_X_RXP0 {} X_X_RXN0 {} X_X_RXP {} X_X_RXN {} X_X_RXP {} X_X_RXN {} X_X_RXP {} X_X_RXN {} X_X_RXP {} X_X_RXN {} X_X_RXP {} X_X_RXN {} X_X_RXP {} X_X_RXN {} X_X_RXP {} X_X_RXN {} X_X_RXP {} X_X_RXN {} X_X_RXP9 {} X_X_RXN9 {} X_X_RXP0 {} X_X_RXN0 {} X_X_RXP {} X_X_RXN {} X_X_RXP {} X_X_RXN {} X_X_RXP {} X_X_RXN {} X_X_RXP {} X_X_RXN {} X_X_RXP {} X_X_RXN {} X 0.UF/V /PI X uf/v UTek omputer Inc. PIX_ ddie hiu tandard ircuit PIX RV. PIX_LOT X 0.UF/V mb_c00 /PI PIX_LOT X_0.F eta /PI P-VM O X 0.UF/V mb_c00 /PI 0.F ate: Friday, March, 00 heet of

0. eta V V V PIX_ White,/F V V _MLK_PI _MT_PI X_WK# X9 PF/0V /PI X0 PF/0V /PI 9 0 V_ V_ RV MLK MT.V_ JT.Vaux WK# PRNT# V_ V_ JT JT JT JT.V_.V_ PWR 9 0 O_PIRT#_PIX {} {} {} X_X_TXP0 X_X_TXN0 XX PRNT# PIN 0.UF/V mb_c00 XX () 如有若請, 是需端以.K OhmPull high 接 V. X_X_TXP0_ X_X_TXN0_ mb_c00 0.UF/V () 若不若請, 請 R 請將接接, 不不 floating, 並請並並是是是要 Pull high or pull down. RV HOP0 HON0 PRNT_# RFLK RFLK- HIP0 HIN0 9 NP_N NP_N _PIX_ {} _PIX#_ {} X_X_RXP0 {} X_X_RXN0 {} LOT_P V V V X_X_T_[:] 若若若請 LOT_WRN, 請請接接. X 0.UF/V /PI X 0.UF/V /PI mb_c00 X 0.UF/V /PI mb_c00 _MLK_PI & _MT_PI 是接接 Mus( 吃 standby power) {,,,} {,,,} _MLK_PI _MT_PI {,} X_WK# X_WK# 是需端 Pull-high UTek omputer Inc. PIX_ ddie hiu P-VM O 0. ate: Friday, March, 00 heet of

0. eta V V V V V V K 0.UF/V /PI mb_c00 K 0.UF/V /PI mb_c00 顏顏 :White /F K 0.UF/V /PI mb_c00 K 0.UF/V /PI mb_c00 K 0.UF/V /PI mb_c00 顏顏 :White /F K 0.UF/V /PI mb_c00 -V PI V V V -V PI V V V {} K_INT# {} K_INT# {} _PI_ {} K_RQ#0 K_ K_9 K_ K_ K_/# K_ K_ K_9 K_ K_/# K_IRY# K_VL# K_LOK# K_PRR# K_RR# K_/# K_ K_ K_0 9 0 9 0 9 0 9 0 9 -V TK TO V V INT INT PRNT RRV PRNT RRV LK RQ V 9.V / 9.V / IRY.V9 VL 9 LOK PRR.V0 RR.V / 0 0 TRT V TM TI V INT INT V RRV 9 V 0 RRV RRV RT V NT RRV 9 0 0.V IL.V 0 9 0.V FRM TRY TOP.V 9 ON 0 O PR.V 9 9 9 K_PM# K_0 K_ K_ K_ K_ K_0 K_ K_ K_FRM# K_TRY# K_TOP# _MLK_PI _MT_PI K_INT# {} K_INT# {} O_PIRT#_LOT {,} K_NT#0 {} K_PR K_ K_ K_ K_9 K_ {,} -V TRT TK V TM TO TI V V V INT K_INT# {} {} K_INT# INT INT K_INT# {} {} K_INT# INT V 9 PRNT RRV 9 O_PIRT#_LOT {,} 0 RRV V 0 {} _PI_ PRNT RRV K_NT# {} {} K_RQ# RRV RRV RT K_ {,} LK V NT RQ 9 K_PM# K_ V RRV 9 0 K_0 K_9 0 0 9.V K_ K_ K_ K_ K_ K_/#.V K_ / IL.V K_ K_ 9 K_0 K_9 0 9 0 9 0 K_ K_.V K_ K_/# /.V K_FRM# K_IRY# FRM IRY K_TRY# K_VL#.V9 TRY VL K_TOP# K_LOK# 9 TOP 9 K_PRR# LOK.V 9 0 _MLK_PI PRR ON 0 _MT_PI K_RR#.V0 O RR K_PR K_/#.V PR K_ K_ /.V K_ K_ 0 K_ K_0 0 9 9 K_9 9 9 K_ K_ K_ K_ K_ 9 0.V V9 K V0 V hold_n hold_n /0.V 0 0 V RQ V V 9 0 K_/#0 K_ K_ K_ K_0 K_RQ# K_ K_ K_ K_ K_ 9 0.V V9 K V0 V hold_n hold_n /0.V 0 0 V RQ V V 9 0 K_/#0 K_ K_ K_ K_0 K_RQ# 若若若請 LOT_WRN 請線, 請請 K_PI_T_ & K_PI_T_ 接接. LOT_0P 若若若請 LOT_WRN 請線, 請請 K_PI_T_ & K_PI_T_ 接接. LOT_0P V K 0UF/.V K 0UF/0V mb_c00 {,} K_[0..] V K 0UF/.V K {,} K_/#[0..] 0UF/0V mb_c00 {,} K_PR {,,,} _MLK_PI {,,,} _MT_PI {} {} {} {} 這這 Net 是要 Pull high, 請並並 hipset 所是 Pull high 電電電電電電 K_INT# K_INT# K_INT# K_INT# {} K_RQ#0 {} K_RQ# {,} K_RQ# {} K_RQ# {,} K_PM# {,} K_TOP# {,} K_VL# {} K_LOK# {,} K_PRR# {,} K_RR# {,} K_FRM# {,} K_TRY# {,} K_IRY# K_RQ# 改 PI slot useonly, 是要.K Pull high to V, 電電電電將電 net 合合若請 {} K_RQ# PI RV. tandard ircuit PI_LOT K_0. T PI LOT 有有有料料, 分分分分分分電分分請請 P 所是所 PI LOT 種種種種種.(efault 改分分 ) 料料電料分分請 Footprint : V00W00( 分 ) -->mb_slot_pci_0p_long_lf V00W0( 分 ) -->mb_slot_pci_0p_short_lf UTek omputer Inc. PI_LOT- P-VM O ddie hiu 0. PI_LOT /PI ate: Friday, March, 00 heet of

0. eta LR 9.9Ohm IH side PRp/LN_RXP PRn/LN_RXN PTp/LN_TXP PTn/LN_TXN {} L_LI_TXP_PHY {} L_LI_TXN_PHY {} L_LI_RXP_PHY {} L_LI_RXN_PHY Place near PHY side mb_c00 LX 0.UF/V mb_c00 LX 0.UF/V mb_c00 LX 0.UF/V mb_c00 LX 0.UF/V Place near IH side L_LI_TXP_ L_LI_TXN_ L_LI_RXP_ L_LI_RXN_ LU H LN_TXP I LN_TXN I LN_RXP H LN_RXN LR LR LR LR LR LR LR 9.9Ohm 9.9Ohm 9.9Ohm 9.9Ohm 9.9Ohm 9.9Ohm 9.9Ohm L_TRMINTION0 L_TRMINTION L_TRMINTION L_TRMINTION L L L L 0.UF/V 0.UF/V 0.UF/V 0.UF/V LN_RX0 LN_RX LN_RX LN_TX0 LN_TX LN_TX LN_LK LN_RTYN LN_RT# {} L_LI_JRX {} L_LI_JRX {} L_LI_JRX0 {} L_LI_JTX {} L_LI_JTX {} L_LI_JTX0 {} L_LI_JKLK {} L_LI_JRTYN {} L_LN_RT#.V_L LR KOhm /- % LR0 %.KOhm O_RMRT# {,,} LR9 /- L.UF/.V /- c00 LR /- FOR NON MT LR9 Ohm LR %.KOhm L_LI_JKLK_R L_KI_P L_KI_N L_RI_P F F H JRX JRX JRX0 JTX JTX JTX0 JKLK JRTYN KI_P KI_N RI_P RI_N MI_MINU[] MI_PLU[] MI_MINU[] MI_PLU[] MI_MINU[] MI_PLU[] MI_MINU[0] MI_PLU[0] XTL XTL L0 L L H9 H F F9 9 9 H H L_XIN L_XOUT LR Ohm L_LINK000#_R L_XOUT_R LRN L PF/0V LX Mhz 0 LRN LRN L PF/0V.V_L 0 0 LRN 0 L_MI_- {} L_MI_ {} L_MI_- {} L_MI_ {} L_MI_- {} L_MI_ {} L_MI_0- {} L_MI_0 {} L_TLP {} L_TLN {} L_LINK000# {} L_LINK00# {} LR.Ohm mb_r0 oc "_dc" LQ P9-.V_L LR.Ohm mb_r0 Place near transistor L_.V_TRL_ L 0UF/0V mb_c00 Parameters are critical. Use P9 000 000 L 0.UF/V mb_c00 L_.0V_INT L0 0.0UF/0V L_.V L 0UF/0V mb_c00 L 0.UF/V mb_c00 L 0.UF/V mb_c00 Intel pec Update: rrata # solve xcess Noise on.v upply L 0UF/0V mb_c00 L UF/.V mb_c00 /- L 0.UF/V mb_c00.v_l L 0.UF/V mb_c00 L_.V_TRL L 0.UF/V mb_c00 L 0UF/0V mb_c00 /- L 0.UF/V mb_c00 /- L 0.UF/V mb_c00 TRL_0 VP0_OUT VP0_ V V VP0_ VFP0 VP0 F VP0_ H VFP0 TRL_ VP_ VP_ F VP_ VP_ F VP_ VP_ NINVH TT_N RRV RRV RRV RRV RRV I_TT_N I_TT_P THRM N THRM P JT_TM JT_TO JT_TI JT_TK V V V V V V V V V V V V V9 V0 V V V V V V V I I H F I9 I I I I 9 F 9 9 9 L_TT_N L_I_TT_N L_I_TT_P LR 0 LR /- Test MHz clock jitter /- 000PF/0V L /- 000PF/0V L_.V L L9 0.UF/V mb_c00 /- UTek omputer Inc. L_TR {} /- 000PF/0V L9 LL /- 000PF/0V L0 L 0.UF/V mb_c00 P-VM O tandard ircuit Intel PHY RV. INTL_M /- M L_0. T L Intel Nick Kao 0. ate: Friday, March, 00 heet 9 of

V V V,,},,} _MT_MIN _MLK_MIN _MT_MIN _MLK_MIN V R Infineon R Infineon R Infineon R.KOhm Infineon R 0.UF/V inosun/00ohm 0.UF/V 9 0 U N LPP# PIO RIRQ N L0 V V PIO L PP LFRM# TTI LLK TTI/ L 0 V V 9 N L XTLI/k_IN LRT# XTLO LKRUN# L9TT R.KOhm _PWRWN# F_RIRQ# F_L0 F_L F_FRM# _PILK_TPM F_L F_L _PLTRT# F_LKRUN# _PWRWN# {,9} F_RIRQ# {,9,} F_L0 {,9,} F_L {,9,} F_FRM# {,9,} _PILK_TPM {,9,9} F_L {,9,} F_L {,9,} _PLTRT# {,,0,9,} F_LKRUN# {9} V R0 T remove R T remove 0.UF/V R9.KOhm X /Infineon.KHZ PF/0V Infineon PF/0V Infineon X_ XTL_HOLR_P UTek omputer Inc. on board TPM hienhih_hung P-VM O ate: Tuesday, November, 00 heet 0 of.00

U K_/#[0..] {,} V R9 K K_NT# K_NT# R9 K {,} O_PIRT#_LOT {,} K_PM# {,} K_PR {,} K_VL# {} _PI_ {,} K_IRY# {,} K_RR# {,} K_TOP# {} K_LOK# {,} K_TRY# {,} K_PRR# {,} K_FRM# {} K_NT# {} K_NT# {} K_NT#0 K_RQ# {} K_RQ# {} K_RQ# {} K_RQ#0 {} K_INT# {} K_INT# {} K_INT# {} K_INT# {} K_INT# {9} L_LI_JKLK {9} L_LI_JRTYN {9} L_LI_JRX0 {9} L_LI_JRX {9} L_LI_JRX {9} L_LI_JTX0 {9} L_LI_JTX {9} L_LI_JTX {9} L_LN_RT# K_NT# K_NT# K_NT#0 K_RQ# K_RQ# K_RQ# K_RQ#0 K_INT# K_INTF# K_INT# K_INTH# R R J K F0 H F F H F K J F K L F F H F F PIRT# PM# PR VL# PILK IRY# RR# TOP# PLOK# TRY# PRR# FRM# NT#/PIO NT#/PIO NT#/PIO NT0# PI RQ#/PIO RQ#/PIO RQ#/PIO0 RQ0# PIRQ# PIRQ# PIRQ# PIRQ# PIRQ#/PIO PIRQF#/PIO PIRQ#/PIO PIRQH#/PIO LN_LK LN_RTYN LN_RX0 LN_RX LN_RX LN_TX0 LN_TX LN_TX LN_RT# LN /0# /# /# /# 0 9 0 9 0 9 0 LN_OMPO LN_OMPI F 9 0 9 9 0 H F 0 H J F H 9 9 K_/#0 K_/# K_/# K_/# K_0 K_ K_ K_ K_ K_ K_ K_ K_ K_9 K_0 K_ K_ K_ K_ K_ K_ K_ K_ K_9 K_0 K_ K_ K_ K_ K_ K_ K_ K_ K_9 K_0 K_ P_.V_PI LN_I R.9 % K_[0..] {,} {} K_RQ#0 {} K_RQ# {} K_RQ# {} {} {} {} K_INT# K_INT# K_INT# K_INT# K_RQ# {} K_RQ# K_INT# K_INTF# K_INT# K_INTH# K_TOP# K_VL# K_LOK# K_PRR# K_RR# K_FRM# K_TRY# K_IRY# KR.KOhm KP.KOHM 0 KP.KOHM 0 KP.KOHM KP 0.KOHM 0 KP.KOHM 0 KPF.KOHM 0 KPH 9.KOHM 0 KP.KOHM 0 KRN.KOHM KRN.KOHM KRN.KOHM KRN.KOHM KP.KOHM 0 KP.KOHM 0 KP.KOHM 0 KP.KOHM 0 KP.KOHM 0 KPH 9.KOHM 0 KPF.KOHM 0 KP.KOHM 0 V V V _RTRT# R 0KOhm UF/0V T_V R.0: hange R0 & c & ize from 00 to 00 PF/0V c00 R0 0MOhm r00_h Y.KHZ PF/0V M_00 Y_ XTL_HOLR_P _RTRT# PIO/PI_#/LPIO RTRT# PI_0# _RTRT# PI_MOI H0 RTRT# PI_MIO _IH_RTX PI_LK RTX _IH_RTX RTX IH9 RT PI F _PI_#_R _PI_0#_R _PI_MOI_R _PI_MIO_R _PI_LK_R R R R _PI_#_R K_NT#0 R KOhm R K F_PI_# {0} F_PI_MOI {0} F_PI_MIO {0} F_PI_LK {0} OOT VTOR LT NT0# PI_# PI 0 PI LP 0 _PI_#_R R K V TTRY attery ocket JLMO: V R9 KOhm % T T_R MINI_JUMPR TT_P LRT UTek omputer Inc. T_V _RTRT# HR_XP R.KOhm TW P-VM O T_ R 0KOhm KT LITHIUM TT IH9- Tyler_Yuan ate: Friday, March, 00 heet of R0 V/0mh UF/0V.0

U P_.V_PI R.9Ohm % {} K_00M_IH# {} K_00M_IH MI_OMP F F0 U U MI MI_IROMP MI_ZOMP MI_LKN MI_LKP U UP0N UP0P UPN UPP UPN UPP U_U- {} U_U {} U_U- {} U_U {} U_U- {} U_U {} {} N_MI_TX#0 {} N_MI_TX0 {} N_MI_RX#0 {} N_MI_RX0 {} N_MI_TX# {} N_MI_TX {} N_MI_RX# {} N_MI_RX {} N_MI_TX# {} N_MI_TX {} N_MI_RX# {} N_MI_RX {} N_MI_TX# {} N_MI_TX {} N_MI_RX# {} N_MI_RX W W V0 V9 Y0 Y9 0 9 F 9 0 MI0RXN MI0RXP MI0TXN MI0TXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP Y Y Y Y U_U9- {} U_U9 {} U_U0- {} U_U0 {} U_U- {} U_U {} U_U0- {} U_U0 {} U_U- {} U_U {} U_U- {} U_U {} PI_ UP9N UP9P UP0N UP0P V V W W U_U- {} U_U {} U_U- {} U_U {} {} X_X_RXN0 {} X_X_RXP0 {} X_X_TXN0 {} X_X_TXP0 P0 P9 R R PRn PRp PTn PTp UPN UPP V V U_U- {} U_U {} M0 M9 N N K0 K9 L L PRn PRp PTn PTp PRn PRp PTn PTp O0#/PIO9 O#/PIO0 O#/PIO O#/PIO O#/PIO O#/PIO9 O#/PIO0 O#/PIO O#/PIO O9#/PIO O0#/PIO O#/PIO P N P R N N N M P R T P U_O# U_O# U_O# U_O# U_O9# U_O# U_UO#0 {} U_UO# {} U_UO# {} U_UO# {} U_UO#9 {} U_UO#0 {} H0 H9 J J PRn PRp PTn PTp {0} X_TX_RXN {0} X_TX_RXP {0} X_TX_TXN {0} X_TX_TXP {9} L_LI_TXN_PHY {9} L_LI_TXP_PHY {9} L_LI_RXN_PHY {9} L_LI_RXP_PHY F0 F9 9 0 PRn PRp PTn PTp PRn/LN_RXN PRp/LN_RXP PTn/LN_TXN PTp/LN_TXP URI# URI _URI R % R.0 LK K_M_U {} IH9 UTek omputer Inc. P-VM O IH9- Tyler_Yuan ate: Friday, March, 00 heet of.00

VTTPU V O_VTTPU_OV# {} {} O_0 {0} H_0M# TP {0} H_INN# {9} H_INIT# {0} H_INTR {0} H_FRR# {0} H_NMI {} O_K_RT# {0,9,} F_RIRQ# _TP_INIT_V# U P 0T J 0M# INN# M INIT_V# INIT# H INTR J FRR# F NMI L RIN# N RIRQ T0RXN T0RXP T0TXN T0TXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP K J K9 J9 J K H F J K H F T_T_RXN0 {9} T_T_RXP0 {9} T_T_TXN0 {9} T_T_TXP0 {9} T_T_RXN {9} T_T_RXP {9} T_T_TXN {9} T_T_TXP {9} T_T_RXN {9} T_T_RXP {9} T_T_TXN {9} T_T_TXP {9} H_FRR# {0} H_THRMTRIP# R Ohm VTTPU R Ohm VTTPU_OV# RN.KOHM RN.KOHM Q0 PM90 Q9 N0 {0} R H_MI# H H_TPLK#_R {0} H_TPLK# J9 {0} H_THRMTRIP#.V_L {} N_LINK_LK {} N_LINK_T H R 9.KOhm {} N_LINK_RT# 0 % {} N_L_PWROK_R T _IH_L_RF R Ohm 0.UF/V % V 0 0PF/0V MI# TPLK# THRMTRIP# TRXN TRXP TTXN TTXP TRXN HOT TRXP TTXP TTXN TRXN TRXP TTXN TTXP T_LKN T_LKP TL# L_LK0 TRI# TP TRI L_T0 TP L_RT0# TP LPWROK L_VRF0 TP LINK T T0P/PIO TP/PIO9 TP/PIO TP/PIO TP TP TLKRQ#/PIO J K F H J9 K9 H9 F0 J K F H F F9 K J K 0 F L _TRI VOR_OV# _TP _.V_OV_Q# _.V_OV_Q# _TP _TP T_T_RXN {9} T_T_RXP {9} T_T_TXP {9} T_T_TXN {9} T_T_RXN {9} T_T_RXP {9} T_T_TXN {9} T_T_TXP {9} T_T_RXN {9} T_T_RXP {9} T_T_TXN {9} T_T_TXP {9} K T# {} K T {} R.9Ohm % r00_h V R 0KOhm O_IO_WP# {0} V R 0KOhm R 0KOhm T_TL# {9} R R9 0KOhm 0KOhm R0 0KOhm R 0KOhm R9 R 0KOhm 0KOhm.V_OV# R 0KOhm _.V_OV_Q# V RN.KOHM RN.KOHM V RN.KOHM Q PM90 RN.KOHM Q Q N0 PM90 O_.V_OV# {} O_.V_OV# {} Q N0 LOK/PIO LO/PIO TOUT0/PIO9 TOUT/PIO J K H 0 VTTPU_OV#.V_OV# J_NO_T {} J_PUTM# {} V O_.V_OV# {} R 0KOhm R 0KOhm R 0KOhm {} _PUFN_PWM R 0KOhm TH0 {} _IH_PIO _IH_PIO _IH_PIO _N_PUFN TH0 R0 TP _IH_PWM TP _IH_PWM H K H K J J K TH0/PIO TH/PIO TH/PIO TH/PIO PWM0 PWM PWM IH9 FN_P {0} T 9 H_PI O_T O_T {} H_PI_ PI For the ONRO processor (I-direction) IO_PI {} R R R VOR_OV# H_PI_ 有電電是個須須需個個以個個請請 H_PI_IO {} V RN9.KOHM Q RN9.KOHM PM90 RN9.KOHM RN9.KOHM O_VOR_OV# {0} RN _.V_OV_Q#.KOHM Q N0 UTek omputer Inc. RN.KOHM Q P-VM O IH9- Tyler_Yuan ate: Friday, March, 00 heet of Q N0 PM90.0

NW PU {0} H_KTO# {} T_V O_RI# traping Pin: : X 0: X {} _Z_OUT {} _Z_YN R MOhm /NWPU O9 0.UF/V /NWPU V R99 KOhm R MOhm /NWPU R.KOhm Q R00 KOhm NW_PU N0 /NWPU Q PM90 R0 R0 RIN# RIN# {} LRQ0# V V RMOV FOR TO MO _MLK_PI Regin 自自自自 R 0KOhm 0KOHM RN 0KOHM RN 0KOHM RN 0KOHM RN R R _MT_PI V R 0KOhm O_TN MLINKLRT# MLINK0 MLINK MLINK0 MLINK {} _Z_IN0 {} _Z_OUT {} _Z_YN {} K_M_ {0,9,} F_L0 {0,9,} F_L {0,9,} F_L {0,9,} F_L {,9} _Z_ITLK {0,9,} F_FRM# {} _Z_RT# _LRQ# {9} O_TN {,,,} _MLK_PI {,,,} _MT_PI MLINKLRT# MLINK0 MLINK J LRQ#/PIO K FWH0/L0 H FWH/L M FWH/L J FWH/L L L K H_IN0 H H_IN H H_IN J H_IN J K M H J U LRQ0# FWH/LFRM# H_OUT H_YN LK LP H_IT_LK H_RT# UIO MLRT#/PIO H MLK MT PIO0 N J_ILNT# {} PIO 0 _FP_PR# {} _WOL_ONLY WOL_N/PIO9 _WOL_ONLY {} PIO0 LRT#/PIO0 PIO PIO 9 O_PM# {} LPIO/PIO 9 O_PWRTN# {} PIO0 PIO PIO M PIO K PIO0 F LPIO0/PIO PIO _TT#/PIO QRT_TT0/PIO QRT_TT/PIO PIO K PIO F PIO9 J INTRUR# LN00_LP THRM# K MH_YN# H U_TT#/LPP R ULK R PIO H PIO F LPIO/PIO F LINKLRT#/PIO0/LPIO WK# 0 MLINK0 PWRTN# T MLINK RI# 9 PUPWR VRMPWR PWROK MU PLTRT# Y_RT# F9 RMRT# F TT# PL MF_MO_N _PIO9 R0.KOhm MI TRMINTION TRP NW_PU nablelnpower IH_THRM# _PWRWN# _ULK V _PIO R KOhm RIN# IH_VRMP _PI_TOP# {} _PU_TOP# {} TT# {} _FP_PR# {} T_V R 90KOhm TO NL INTRNL VRM V V N_IH9_YN# {} _PWRWN# {0,9} R.0 R.K R 0KOhm R 0KOhm 0KOhm R V X_WK# {,} O_PWRTN# {} H_PUPWR {0,} P_VRM_ {0,} O_PWROK {,,} _PLTRT# {,0,0,9,} O_RTON# {,,9} O_RMRT# {,9,} {} _FP_PR# R.K V R9 0KOhm Regin 預預,ost own IH_VRMP V T V V R.K R.K R 0KOhm L ONTROL IRUIT Q R _IH9_LP_M# 0KOhm /MT KOhm PM90 /MT UF/V/00 /MT KOhm V R9 /MT _LP_M O_TN 00PF/0V _LP_M {,,,} V {,} _LP# {,} _LP# R.K {} _K_PWROK T T _LP# _LP# _IH9_LP_M# IH_TP0 IH_TP IH_TP LP_# LP_# LP_# F LP_M# T K_PWR TP0 K TP TP F0 TP IH9 Power L MI R Q PL.KOhm PM90 INTVRMN PKR N _PL- {9} INTVRMN T_V TO NL INTRNL VRM R 90KOhm V Trap for TO timer reboot feature R KOhm _PKR {9} RVI_MO R MF_MO_N.KOhm HR_XP ate: Friday, March, 00 heet of V UTek omputer Inc. P-VM O R9.KOhm IH9- Tyler_Yuan.0

P_.0V_INT_ VRF PV_VMI P_.V_INT PV_MIPLL VRF_U P_.0V_INT_ VT_PLL PV_LN_PLL.V P_.V_PI.V.V P_P0V_LN V T_V P_.VL_INT.0V P_.0V_L_INT.V V V V V VTTPU.V_L ate: heet of Friday, March, 00 UTek omputer Inc. IH9-.0 P-VM O Tyler_Yuan ate: heet of Friday, March, 00 UTek omputer Inc. IH9-.0 P-VM O Tyler_Yuan ate: heet of Friday, March, 00 UTek omputer Inc. IH9-.0 P-VM O Tyler_Yuan R.0.0V LN OUTPUT 0uF/.V 0uF/.V 0.UF/V 0.UF/V 0 0.UF/V 0 0.UF/V 0.UF/V 0.UF/V 9 0.UF/V 9 0.UF/V L 0UH L 0UH 9 0.UF/V 9 0.UF/V 0.UF/V 0.UF/V UF/0V c00 UF/0V c00 0.UF/V 0.UF/V L UH L UH 0 0.UF/V 0 0.UF/V 0.UF/V 0.UF/V L UH L UH 0.UF/V 0.UF/V TW TW L UH L UH 0.UF/V 0.UF/V 0.UF/V 0.UF/V UF/.V c00 UF/.V c00 0.UF/V 0.UF/V 0.UF/V 0.UF/V UF/0V UF/0V 0.UF/V 0.UF/V 0 0.UF/V 0 0.UF/V.UF/.V c00.uf/.v c00 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V UF/0V UF/0V 0.UF/V 0.UF/V UF/0V UF/0V 9 UF/0V 9 UF/0V 0.UF/V 0.UF/V 9 0.UF/V 9 0.UF/V 9 UF/0V 9 UF/0V 9 UF/0V 9 UF/0V 0.0UF/0V 0.0UF/0V UF/.V c00 UF/.V c00 UF/0V c00 UF/0V c00 R R R R 0.0UF/V 0.0UF/V VRF VRF_us F Vcc H0 Vcc H Vcc Vcc Vcc VccL_ VccusH 9 VccH 0 Vcc 0 Vcc 9 Vcc Vcc F VccUPLL K VccTPLL K0 VccMIPLL T0 VccLNPLL Vccus F VccL VccL VccLN 0 VccLN 9 VccLN VccLN 0 Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc 9 Vcc 0 Vcc 9 Vcc 0 Vcc J Vcc J Vcc K Vcc K Vcc K Vcc L Vcc 9 L Vcc 0 M Vcc M Vcc M Vcc N Vcc N VccMI_ 9 VccMI_ 0 Vcc P Vcc P Vcc P Vcc R Vcc 9 R Vcc 0 T Vcc T Vcc T Vcc T Vcc T Vcc U Vcc U Vcc U9 Vcc U0 Vcc 9 V Vcc 0 Vcc Vcc Vcc 9 Vcc 0 Vcc Vcc F Vcc H0 Vcc H Vcc J0 Vcc Vcc Vcc F Vcc 9 H Vcc 0 H Vcc J Vcc K Vcc K0 Vcc Vcc VccLN_0_ 0 VccLN_0_ 0 Vcc Vcc Vcc Vcc 9 T Vcc 0 Vcc Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_ Vcc_0_ F Vcc_0_ Vcc_0_ H Vcc_0_ H Vcc_0_0 M Vcc_0_ M Vcc_0_ M Vcc_0_ M Vcc_0_ M Vcc_0_ M9 Vcc_0_ N Vcc_0_ N9 Vcc_0_ R Vcc_0_9 R9 Vcc_0_0 U Vcc_0_ U9 Vcc_0_ V Vcc_0_ V9 Vcc_0_ W Vcc_0_ W Vcc_0_ W Vcc_0_ W Vcc_0_ W Vcc_0_9 W9 V_PU_IO H V_PU_IO J0 Vcc H Vcc VccLN_ Vcc Vcc 9 Vcc 9 Vcc 0 Vcc H Vcc J Vcc K Vcc L VccLN VccLN Vccus U Vccus U Vccus U Vccus U Vccus U Vccus U Vccus U Vccus 9 V Vccus 0 W Vccus W Vccus Y Vccus Vccus 0 Vccus Vccus H VccRT Vccus_0_ Vccus_0_ H VccL_0 Vccus H Vccus Vcc Vcc H0 Vcc K Vcc 0 V Vcc V Vcc W Vcc W Vcc Y Vcc Y Vcc Y Vcc_0_9 J Vccus 0 U IH9 U IH9.UF/.V.UF/.V 0.UF/V 0.UF/V 90.UF/.V 90.UF/.V UF/0V UF/0V 0UF/.V 0UF/.V UF/.V c00 UF/.V c00 R R UF/0V c00 UF/0V c00 UF/0V UF/0V 0 0UF/.V 0 0UF/.V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0 0.UF/V 0 0.UF/V UF/0V c00 UF/0V c00 0UF/.V 0UF/.V

UF F9 V V V 9 V 0 V H V H9 V H V H V9 H V0 H V H V H9 V J9 V J0 V J V K V K V L V9 L V0 L9 V L0 V M V M V M V M V M V M V N V9 N V0 N V N V N V N V N V N9 V N0 V P V P V9 P V0 P V P V P V P V P9 V P V P V P V P V9 R V0 R V R V R V R V R V R V R9 V R0 V R V9 T V0 T V T V T V T V T V T V T9 V T V T9 V9 T V U V U V U V U V U V U V U V V V V V9 V V0 V V V V V V V V V V V V V V W V W V9 W V90 W V9 W9 V9 W0 V9 W V9 K V9 H9 V9 J V9 F V9 V99 Y V00 IH9 V0 V0 V0 V0 V0 V0 V0 V0 V09 V0 V V V V V V V V V9 V0 V V V V V V V V V9 V0 V V V V V V V V V9 V0 V V V V V V V V V9 V0 V V V V V V V V V9 V0 V V V V V V V V V9 V V V V V V V V V V9 V0 V V V V V V V V V9 V90 V9 V9 V9 V9 V9 V9 V9 V9 F F F F F 0 9 9 K K0 K9 K K K K J J J J J0 J J J H H H0 H9 H H H F9 F F9 F F F0 F F 9 9 0 9 9 0 9 0 9 0 W Y Y Y HTINK HT INK Mus witch _MLK_PI R9 _MLK_MIN _MT_PI R90 _MT_MIN V R9 KOhm R9 0KOhm Q N0 {,,,} _MLK_PI _MLK_MIN {,,,,0} {,,,} _MLK_PI _MT_PI.00 Mus connect to two kind of devices, one use Main power, another use tandby power, so use this switch circuit to isolate those two device. M_LK and M_T for tandby device. M_LK_MIN and M_T_MIN for Main power device. _MT_PI V Q N0 _MT_MIN {,,,,0} RN _MLK_MIN.KOHM RN.KOHM RN _MT_MIN.KOHM.KOHM RN UTek omputer Inc. P-VM O ate: Friday, March, 00 heet of V IH9- Tyler_Yuan.0

If the PI chipset can support.v and v signaling, then connect the PI_VIO pin on the FW to the PI_VIO pin (9) V V ZL /00Mhz Z_V Z 0.UF/V mb_c00 Z 0.UF/V mb_c00 ZR for crystal oscillator stability V 0. eta {,} K_[0..] {,} K_/#[0..] {,} K_PR {,} K_FRM# {,} K_IRY# {,} K_TRY# {,} K_VL# {,} K_TOP# {,} K_ {} K_RQ# {} K_NT# {,} K_PRR# {,} K_RR# {} _PI_9 {,} O_PIRT#_LOT {} K_INT# {,} K_PM# Z 0.UF/V mb_c00 K_0 K_ K_ K_ K_ K_ K_ K_ K_ K_9 K_0 K_ K_ K_ K_ K_ K_ K_ K_ K_9 K_0 K_ K_ K_ K_ K_ K_ K_ K_ K_9 K_0 K_ K_/#0 K_/# K_/# K_/# K_PM#_R ZR9 / ZU PI_VIO 9 PI_0 PI_ PI_ PI_ PI_ PI_ 0 PI_ 9 PI_ PI_ PI_9 PI_0 PI_ PI_ 0 PI_ 9 PI_ PI_ PI_ PI_ PI_ 0 PI_9 9 PI_0 PI_ PI_ PI_ PI_ 0 PI_ 9 PI_ PI_ PI_ PI_9 PI_0 PI_ PI_0# PI_# PI_# PI_# PI_PR PI_FRM# 9 PI_IRY# 0 PI_TRY# PI_VL# PI_TOP# PI_IL 9 PI_RQ# PI_NT# PI_PRR# PI_RR# PI_PLK PI_PRT# PI_INT# 0 PI_PM# 99 V0 V V V V V V V V0 V V V V V V V 9 V0 V V V0 V V V XI RT# R R0 Z_TP- TPI0 TP0 TP0- TP0 TP0- TPI TP 0 TP- 9 TP TP- ROM_ ROM_LK 9 XO 9 9 90 9 P P TT0 TT TT PTT 9 9 M 9 Z_XIN Z_XOUT Z_URRT Z_URRT0 Z_TPI Z_TP_R Z_TP-_R Z_TP_R Z_TP-_R Z_TPI0 Z_TP0_R Z_TP0-_R Z_TP0_R Z_TP0-_R Z_ Z_L ZR 90OHM ZX % Z_XOUT_R Z_XRT ZR.9KOhm %.: ZR9 0K 改改 9K Z_XP Z PF/0V ZR9 Z Z_9P0_V 9KOhm % Power class 0 -> P pull down V 0.UF/V mb_c00 an be change to Z_9P0_V for some function.mhz ZR 0KOhm ZRN.KOhm mb_rp00 V {} {} {} {} {} {} {} {} hange ZR for 0ohm to short Z PF/0V ZRN.KOhm mb_rp00 Z 0.UF/V mb_c00 Z_TP Z_TP- Z_TP Z_TP0- Z_TP0 Z_TP0- Z_TP0 ZRN.KOhm mb_rp00 ZRN.KOhm mb_rp00 Z 0.UF/V mb_c00 ZRNX ZRNX ZRNX ZRNX ZL /00MHz /VT0 ZL /00MHz /VT0 ZRNX ZRNX ZRNX ZRNX ZL /00MHz /VT0 ZL /00MHz /VT0 Z_TP_R Z_TP-_R Z_TP_R Z_TP-_R Z_TP_ ZR.99KOhm % Z_TP0_R Z_TP0-_R Z_TP0_R Z_TP0-_R Z 0.UF/V mb_c00 ZR.Ohm % ZR.Ohm % Z_TP0_ ZR.99KOhm % Z 0PF/0V ZR.Ohm % Z 0PF/0V Z0 0.UF/V mb_c00 ZR ZR.Ohm.Ohm % % Z UF/0V / ZR.Ohm % Z9 UF/0V / ZR.Ohm % Z_TPI Z 0.UF/0V XR ZR.Ohm % Z_TPI0 Z0 0.UF/0V XR FW_0 00 9.V-00K V tandard ircuit ZU 0 V WP L T0N 9 RV. FW / FW Z_0._beta UTek omputer Inc. FW- Makishin Huang P-VM O 0. ate: Friday, March, 00 heet of

0. eta 9_ * 若無無請 Header * olor = Red Z_9P_V Z_9P_V {} {} Z_TP Z_TP I9_ 0 Z_TP- {} Z_TP- {} HR_XP_K9 V Z Z_9P0_V ZF ZL Z_V_F Z_V_ V Z ZF./V /00Mhz Z Z_V_F 0.UF/V./V / Z_V_ Z_9P_V ZL /00Mhz Z 0.UF/V / UTek omputer Inc. FW- Makishin Huang P-VM O 0. ate: Friday, March, 00 heet of

0. eta 顏顏 :lack 顏顏 :R {} T_T_TXP0 {} T_T_TXN0 {} T_T_RXN0 {} T_T_RXP0 TX9 TX TX TX 0.0UF/0V mb_c00 0.0UF/0V mb_c00 0.0UF/0V mb_c00 0.0UF/0V mb_c00 T_T_TXP0_ T_T_TXN0_ T_T_RXN0_ T_T_RXP0_ T N - - N 9 () 假如 hipset 沒有分 Master & lave, onnector 顏顏請種種顏顏. () 假如 hipset 有分 Master & lave, Masterr 顏顏請種種顏顏 onnector lave 顏顏請種種顏顏 onnector T_ON_P {} T_T_TXP {} T_T_TXN {} T_T_RXN {} T_T_RXP TX0 TX TX TX 0.0UF/0V mb_c00 0.0UF/0V mb_c00 0.0UF/0V mb_c00 0.0UF/0V mb_c00 T_T_TXP_ T_T_TXN_ T_T_RXN_ T_T_RXP_ T N - - N 9 T_ON_P {} T_T_TXP {} T_T_TXN {} T_T_RXN {} T_T_RXP TX TX TX TX 0.0UF/0V mb_c00 0.0UF/0V mb_c00 0.0UF/0V mb_c00 0.0UF/0V mb_c00 T_T_TXP_ T_T_TXN_ T_T_RXN_ T_T_RXP_ T N - - N 9 T_ON_P {} T_T_TXP {} T_T_TXN {} T_T_RXN {} T_T_RXP TX TX TX TX 0.0UF/0V mb_c00 0.0UF/0V mb_c00 0.0UF/0V mb_c00 0.0UF/0V mb_c00 T_T_TXP_ T_T_TXN_ T_T_RXN_ T_T_RXP_ T N - - N 9 T_ON_P {} T_T_TXP {} T_T_TXN {} T_T_RXN {} T_T_RXP TX TX TX TX9 0.0UF/0V mb_c00 0.0UF/0V mb_c00 0.0UF/0V mb_c00 0.0UF/0V mb_c00 T_T_TXP_ T_T_TXN_ T_T_RXN_ T_T_RXP_ T N - - N 9 T_ON_P {} T_T_TXP {} T_T_TXN {} T_T_RXN {} T_T_RXP TX TX TX TX0 0.0UF/0V mb_c00 0.0UF/0V mb_c00 0.0UF/0V mb_c00 0.0UF/0V mb_c00 T_T_TXP_ T_T_TXN_ T_T_RXN_ T_T_RXP_ T N - - N 9 T_ON_P UTek omputer Inc. P-VM O tandard ircuit T T_onnector RV. T_0. T T_ONNTOR T_onnector avid Yao 0. ate: Friday, March, 00 heet 9 of

V T_.V T_.V I I I I I I9 I0 0.UF/V /IU 0.UF/V /IU 0UF/.V /IU 0.UF/V /IU 0.UF/V /IU 0.UF/V /IU 000PF/0V /IU LO TO PIN,9 LO TO PIN LO TO PIN 9 LO TO PIN R.0: 拿拿 I & I {,0,,9,} _PLTRT# V T_.V I_P I_P I_P9 I_P IRN OHM IRN OHM IRN OHM IRN OHM I_P_R I_P_R I_P9_R I_P_R {} X_TX_TXP {} X_TX_TXN {} X_TX_RXN {} X_TX_RXP {} _PI_R# {} _PI_R Near hipset I_RXT TX 0.UF/V X_TX_TXP_ mb_c00 TX 0.UF/V X_TX_TXN_ mb_c00 TX 0.UF/V X_TX_RXN_ mb_c00 TX 0.UF/V X_TX_RXP_ mb_c00 I_RXT IR.KOhm /IU TIU PLKN PLKP PV_ P_ PRXT PRXP PRXN 9 PV_ 0 P_ PTXN PTXP I_P I_P I_P I_P I_P I_P0 ZI ZI ZI ZI ZI ZI0 XRTn 0 9 V_ I_P I_P I_P I_P9 I_P I_P0 I_P I_P I_PRQ ZI XIMRQ N ZI ZI ZI ZI9 ZI ZI0 ZI V_ ZI ZI 9 0 I_P I_P YIMKn XIIORY YIIORn YIIOWn V XINTRQ XILI 0 YI 9 YI0 YI YI0n YIn JM-LZ0 /IU V I_PK# I_PIORY I_PIOR# I_PIOW# I_IRQ PTT I_P I_P0 I_P I_P0# I_P# I_P0 I_P I_P I_P I_P I_P I_P I_P I_P I_P I_P I_P0 I_P I_P I_P0 I_P# I_PIORY I_PIORY I_PRQ I_PRQ I_IRQ IRN OHM IRN OHM IRN OHM IRN OHM IRN OHM IRN OHM IRN OHM IRN OHM IRN OHM IRN OHM IRN OHM IRN OHM IRN OHM IRN OHM IRN OHM IRN OHM IR.KOhm /IU I_P0_R I_P_R I_P_R I_P_R I_P_R I_P_R I_P_R I_P_R I_P_R I_P_R I_P_R I_P0_R V IR Ohm /IU I_PIORY_R IR.KOhm % /IU I_P_R I_P_R I_P0_R I_P#_R IR Ohm /IU I_PRQ_R IR 0KOhm % /IU {} {9} I_IT# PRI_I ( 垂垂 ) RT#_I RT#_I I_P_R I_P_R I_P_R I_P_R I_P_R I_P_R I_P_R I_P0_R I_PRQ_R I_PIOW#_R I_PIOR#_R I_PIORY_R I_PK#_R I_IRQ_R I_P_R I_P0_R I_P0#_R I_PTL# olor : R I PRI_I 9 0 9 9 0 9 0 HR_X0P I_P_R I_P9_R I_P0_R I_P_R I_P_R I_P_R I_P_R I_P_R I_L PTT I_P_R I_P#_R I_IRQ IR Ohm /IU I_IRQ_R T_.V Io=0. I_PIOW# I_PIOR# IR9 OHM /IU I_PIOW#_R IR0 OHM /IU I_PIOR#_R T connector PN:000K (lue) R/ connector PN:000K (lue) R/ connector PN:000N (Red) V TP 0.UF/V mb_c00 TP 0.UF/V mb_c00 /JM TPQ J/ OUT Vout IN XF P_.VT_J_0 TPR TPR.Ohm T_.V TP 0uF/.V L P I_PK# I_P0# I_P IR OHM /IU I_PK#_R IR Ohm /IU I_P0#_R IR 0KOhm % /IU I_L IR /IU Vout=Vref*(TPR/TPR)=.*(./0)=.V UTeK OMPUTR IN <Title> Regin_hiang P-VM O ate: Friday, March, 00 heet 0 of.00

{} _Z_IN0 {} _Z_OUT {} _Z_YN {} _Z_RT# {,9} _Z_ITLK {9} _PP RN Ohm RN Ohm RN Ohm R OHM 0 PF/0V 須須擺個 c00 R KOhm {} _PIFO V R OHM _PP_R _ R.KOhm UF/0V _Z_IN0_R _Z_OUT_R _Z_YN_R _Z_RT#_R _Z_ITLK_R RN Ohm _PP_ U T_IN T_OUT 0 YN RT# LK PP PIFO H Link ack Panel LIN_L LIN_R LIN_VRFO 9 FRONT_L FRONT_R MI_L MI_R MI_VRFO_L MI_VRFO_R _LIN_L LIN_R LOUT_L LOUT_R MI_L MI_R I_MI_L _I_MI_R.UF/.V XR.UF/.V XR 0uF/.V 0uF/.V.KOHM RN.KOHM RN.UF/.V XR.UF/.V XR 9.KOHM RN.KOHM RN _LIN_L_L _LIN_R_L _LOUT_L_L _LOUT_R_L _MI_L_L _MI_R_L L L L L L L /00Mhz /00Mhz /00Mhz /00Mhz /00Mhz /00Mhz 00PF/0V /L 00PF/0V 0 00PF/0V /L _ 00PF/0V /L 00PF/0V 00PF/0V /L 0. eta _LIN_L {} _LIN_R {} _LOUT_L {} _LOUT_R {} _MI_L {} _MI_R {} 0.UF/V 0.UF/V 0.UF/V 0.UF/V 9 V V_IO 9 0.UF/V 0.UF/V _ For -hannel 若請, 如改 -hannel 請請此請請. tandard ircuit UIO RV. L L _0. eta /L {} L {} {} R {} _J_LOUT {} _J_LIN {} _J_MI {} _J_UR {} _J_UR {} _J_NL {} _J_FRONT V _ V 0.UF/V _ R.KOhm R0 0.UF/V _ R 0KOhm 0.UF/V R.KOhm R9 0KOhm 0UF/0V 0KOhm _JRF _N R 9.KOhm /H/L R.KOhm /H/L R 0KOhm /H/L _VUX _VRF V V _L 9 _ 0 _R N VRF 0 JRF ense ense PIO0/MI_LK PIO/MI_T PIFI/P L_R IN V V V V _ PIN_VRFO Front Panel I_L I_R NTR LF URR_L 9 URR_R LIN_L LIN_R LIN_VRFO MI_L MI_R MI_VRFO 0 _UR_L UR_R N LF UR_L UR_R_ 9 0uF/.V _LIN_L_ 0 0uF/.V _LIN_R I_LIN 0uF/.V _MI_L_ 0uF/.V _MI_R I_MI 0UF/V /H/L 0UF/V /H/L 0UF/V /H/L 0UF/V /H/L For -hannel 若請, 如改 -hannel 請請此請無請請. 0UF/V /H/L 0UF/V /H/L WW _UR_L_L _UR_R_L _N_L _LF_L _UR_L_L _UR_R_L _LIN_L_R _LIN_R_R _I_MI_L _I_MI_R L /00Mhz /H/L /00Mhz /H/L L L9 /00Mhz /H/L /00Mhz /H/L L0 L /00Mhz /H/L /00Mhz /H/L L R Ohm _MI_L_L _MI_R_L _LIN_L_L.KOHM RN _LIN_R_L R Ohm WW _I_LIN_L.KOHM RN _I_LIN_R.KOHM RN.KOHM RN PK UTek omputer Inc. _ L _ /00Mhz UR_L {} _UR_R {} _N {} _LF {} _UR_L {} _UR_R {} _LIN_L {} _LIN_R {} _MI_L {} _MI_R {} 00PF/0V /H/L 0 00PF/0V /H/L 00PF/0V /H/L L L 00PF/0V /H/L 00PF/0V /H/L 00PF/0V /H/L /00Mhz 00PF/0V /00Mhz L /00Mhz 9 00PF/0V P-VM O 00PF/0V 0 00PF/0V RealTek L Oldy hu ate: Friday, March, 00 heet of 0.

ack Panel hannel onnector 請顏灰 {} {} {} {} _UR_L {} _J_UR {} {} _LF _UR_R {} _UR_L {} _J_UR _UR_R _N _J_NL 藍綠粉顏 9 0 PORT PORT PORT 9 0 UIO PORT PORT PORT _ 0 9 PHON_JK_P /H/L LIN_L {} _J_LIN {} _LIN_R {} _LOUT_L {} _J_LOUT {} _LOUT_R {} _MI_L {} _J_MI {} _MI_R {} 0. eta PIF OUT (Header) V PIF_OUT {} _PIFO R9.KOhm /L 9 00PF/0V mb_c00 HR_XP_K lack udio odec New olution for Vista!! ate : //00 PR 0 P_V_J_0 Front Panel {} _MI_L {} _MI_R {} _LIN_R {} _J_FRONT {} _LIN_L FP 9 0 HR_XP_K 顏顏 : reen _J_MI _J_LIN R 9.KOhm R 0KOhm _FP_PR# {} 連接連 IO 請 PI Pin 種 FP 偵偵請, 是需 IO 端 Pull-high.K OHM 連 V. V P TW V PU P_V_VOUT_ J/ Vout OUT PQ IN P0N P XF 0uF/.V P PR 0.UF/V Ohm _ P_V_T_0 PR P MOhm 0.UF/V XR _ Vout=Vref*(PR/PR)=.*(/00)=.V V P 0.UF/V lose to Pin IN {} 0.UF/V _ 0.UF/V /L 0.UF/V WFR_H_P 顏顏 : lack L R_ PK _ UTek omputer Inc. L {} R {} udio onnector Oldy hu 0.UF/V 0.UF/V P-VM O ate: Friday, March, 00 heet of 0.

0. eta V_UL_UK ULX 9/00MHz /U UF ULX 9/00MHz /U./V U_U0_V_L UL /00Mhz U_U0_V_F Regin 自自預預 {} U_U0 {} U_U0- {} U_U {} U_U- {} U_UO#0 URNX URNX URNX URNX U_U0_R {,} U_U0-_R {,} U_U_R {,} U_U-_R {,} URN.KOHM mb_rp00 mb_rp00 URN.KOhm U 0UF/.V onnect to hipset onnect to ack I hort directly if X-series ULX 9/00MHz /U V_UL_UK U_U_V_L ULX 9/00MHz /U UF./V UL /00Mhz U_U_V_F Regin 自自預預 {} U_U {} U_U- {} U_U {} U_U- {} U_UO# URNX URNX URNX URNX U_U_R {,} U_U-_R {,} U_U_R {,} U_U-_R {,} URN.KOHM mb_rp00 mb_rp00 URN.KOhm U 0UF/.V ULX 9/00MHz /U V_UL_UK U_U_V_L ULX 9/00MHz /U UF./V UL /00Mhz U_U_V_F Regin 自自預預 {} U_U {} U_U- {} U_U {} U_U- {} U_UO# URNX URNX URNX URNX U_U_R {,} U_U-_R {,} U_U_R {,} U_U-_R {,} URN.KOHM mb_rp00 mb_rp00 URN.KOhm U 0UF/.V U_U_V_L Regin 自自預預 ULX 9/00MHz /U ULX 9/00MHz /U V_UL_UK UF./V UL /00Mhz U_U_V_F U 0UF/.V {} U_U {} U_U- {} U_U {} U_U- {} U_UO# URNX URNX URNX URNX U_U_R {,} U_U-_R {,} U_U_R {,} U_U-_R {,} URN.KOHM mb_rp00 mb_rp00 URN.KOhm UTeK OMPUTR IN P-VM O U_UL,Port~(O) Nick Kao ate: Friday, March, 00 heet of 0.

0. eta If there are unused U ports,you need check with the chipset vendor.it may need to have a pull down resistor on the unused U port. nd pull up UO# to V. U_U9_V_L Regin 自自預預 U ULX9 9/00MHz /U V_UL_UK 0UF/.V ULX0 9/00MHz /U UF./V U_U9_V_F UL /00Mhz {} U_U {} U_U- {} U_U9 {} U_U9- {} U_UO#9 URNX URNX URNX URNX U_U_R {,} U_U-_R {,} U_U9_R {,} U_U9-_R {,} URN.KOHM mb_rp00 mb_rp00 URN.KOhm. URN.KOHM URN.KOHM mb_rp00 mb_rp00 If there are unused U ports,you need check with the chipset vendor.it may need to have a pull down resistor on the unused U port. nd pull up UO# to V. U_U0_V_L URN.KOhm URN.KOhm mb_rp00 mb_rp00 Regin 自自預預 U ULX 9/00MHz /U V_UL_UK 0UF/.V ULX 9/00MHz /U UF./V U_U0_V_F UL /00Mhz {} U_U0 {} U_U0- {} U_U {} U_U- {} U_UO#0 URNX URNX URNX URNX U_U0_R {,} U_U0-_R {,} U_U_R {,} U_U-_R {,} URN.KOHM mb_rp00 mb_rp00 URN.KOhm UTeK OMPUTR IN P-VM O U_UL,Port9~(O) Nick Kao ate: Friday, March, 00 heet of 0.

0. eta ack I U Protection (IP0Z or V99) Port ~ 個一若請 V99, 若請 IP0Z 是需需 Review 同請 U {,} U_U0_R U_U0-_R {,} U_U0_V_L {,} U_U_R IP0Z /U U_U-_R {,} U {,} U_U_R U_U-_R {,} U_U_V_L {,} U_U_R U_U-_R {,}. IP0Z /U ack I U Protection (IP0Z or V99) Port ~ 個一若請 V99, 若請 IP0Z 是需需 Review 同請 U9 {,} U_U_R U_U-_R {,} U_U0_V_L {,} U_U_R IP0Z /U U_U-_R {,} U0 {,} U_U_R U_U-_R {,} U_U_V_L {,} U_U_R. IP0Z /U U_U-_R {,} UTeK OMPUTR IN U_UL,Port ~ () Nick Kao P-VM O ate: Friday, March, 00 heet of 0.

0. eta ack I U Protection (IP0Z or V99) Port ~ 個一若請 V99, 若請 IP0Z 是需需 Review 同請 U {,} U_U_R U_U-_R {,} U_U0_V_L {,} U_U9_R U_U9-_R {,} IP0Z /U U {,} U_U0_R U_U0-_R {,} U_U_V_L {,} U_U_R. IP0Z /U U_U-_R {,} UTeK OMPUTR IN U_UL,Port 9~ () Nick Kao P-VM O ate: Friday, March, 00 heet of 0.

0. eta onnect to ack I U_U0_V_L U hoose a proper connector in page "ack I onnector" U_U-_R U_U_R U_U0-_R U_U0_R U 0.UF/V mb_c00 U 0UF/0V mb_c00 U U_U_V_L U hoose a proper connector in page "ack I onnector" U_U-_R U_U_R U_U-_R U_U_R U 0.UF/V mb_c00 U9 0UF/0V mb_c00 U UTeK OMPUTR IN P-VM O Nick Kao U,Port~(xt.) ate: Friday, March, 00 heet of 0.

U Internal onnector Tow choice: ox Header or Pin Header U Internal onnector Tow choice: ox Header or Pin Header U90 Internal onnector Tow choice: ox Header or Pin Header U Internal onnector Tow choice: ox Header or Pin Header 0. eta Pin Header Pin Header Pin Header Pin Header U_U_V_L U_U_V_L U_U9_V_L U_U0_V_L U U U90 U {,} U_U-_R U_U-_R {,} {,} U_U-_R U_U-_R {,} {,} U_U-_R U_U9-_R {,} {,} U_U0-_R U_U-_R {,} {,} U_U_R U_U_R {,} {,} U_U_R U_U_R {,} {,} U_U_R U_U9_R {,} {,} U_U0_R U_U_R {,} 0 0 0 0 HR_XP_K9 HR_XP_K9 HR_XP_K9 HR_XP_K9 U_U0_V_L U 0.UF/V mb_c00 U_U_V_L U0 0UF/0V mb_c00 U 0.UF/V mb_c00 U_U_V_L U 0UF/0V mb_c00 U 0.UF/V mb_c00 U_U9_V_L U 0UF/0V mb_c00 U 0.UF/V mb_c00 U 0UF/0V mb_c00 P 和 WIFI Module 頁頁頁保預保電保, 如如此 Port 不不 ox Header(Pin Header) 而不 P 或 WIFI Module, 電以連電保個個請拿 tandard ircuit UWiFi U() WiFi(onnecter) RV. U 0. T UWiFiP /U P 和 WIFI Module 頁頁頁保預保電保, 如如此 Port 不不 ox Header(Pin Header) 而不 P 或 WIFI Module, 電以連電保個個請拿 P 和 WIFI Module 頁頁頁保預保電保, 如如此 Port 不不 ox Header(Pin Header) 而不 P 或 WIFI Module, 電以連電保個個請拿 UTeK OMPUTR IN P-VM O Nick Kao U,Port~(Int.) ate: Friday, March, 00 heet of 0.

0. eta hannel efined TPM onnector follow up Intel Pin definition {,0,,0,} _PLTRT# V V F_L {0,,} 0 F_L {0,,} {,0,9} _PILK_TPM {0,,} F_FRM# {0,,} F_L F_RIRQ# {0,,} F_LKRUN# {0,,} F_L0 F_LKRUN# {0} {0,} _PWRWN# 9 0 9 TPM HR_X0P_K /TPM FR0.KOhm tandard ircuit TPM TPM_onnector RV. F_0. T TPM_ONNTOR /TPM UTek omputer Inc. TPM_onnector Oldy hu P-VM O 0. ate: Friday, March, 00 heet 9 of

F_PI_LK F_PI_MOI F_PI_# 等 net 須需端預 series termination resistor V F 0.UF/V mb_c00 /M/PI F 擺須須 FQ,FQ,FQ 附須, 個個 V 請 noise couple 連 F_PI_LK, F_PI_MOI,F_PI_MIO 等等料種種 OM 要不請 Flash, 將其請請請. 0. eta PI M M Flash P/N Priority T : 00000H0 {} F_PI_LK {} F_PI_MIO V FQ HN0 /M/PI FR KOhm % /M/PI mb_r00 FQ HN0 /M/PI F_PI_MIO_Q FRN KOhm /M/PI mb_rp00 FR mb_r00 F_PI_LK_Q F_PI_MIO_R K V O F_V F F /M/PI 0.UF/V mb_c00 /PI FR /IP/PI TW.V_L Priority PM : 0000 Priority TML : 00000L00 Priority Winbond : 00000F0 PI M M Flash P/N Priority T : 00000 Priority T : 000000 Priority MXI : 000 Priority Winbond : 00000 Priority TML : 000000 {} F_PI_MOI V FQ HN0 /M/PI FRN KOhm /M/PI mb_rp00 F_V F_PI_MOI_Q I IO RV. PI tandard ircuit PI F_0. eta /PI PI M M Flash P/N Priority T : 000000 Priority MXI : 000000 Priority T : 00000 Priority TML : 0000900 Priority PNION: 0000 {} O_IO_WP# FRN mb_rp00.kohm FRN mb_rp00.kohm V FQ HN0 /M/PI FRN KOhm /M/PI mb_rp00 FRN mb_rp00.kohm FRN mb_rp00.kohm F_PI_HOL# O_IO_WP#_Q HOL# WP# F_PI_#_Q F_PI_MIO_Q F_PI_HOL# F_V PI HR_XP_K /M/PI F_PI_LK_Q F_PI_MOI_Q M M Flash F_PI_#_Q F_PI_MIO_R O_IO_WP#_Q FU9 # V O HOL# WP# LK IO WXVI /M/PI F_V F_PI_HOL# F_PI_LK_Q F_PI_MOI_Q PI M M Flash P/N Priority Winbond : 00000 V {} F_PI_# FQ HN0 /M/PI F_PI_#_Q # V FRN KOhm /M/PI mb_rp00 IP & M PI FLH O-LYOUT OM OPTIONL: IP PI FLH OM OPTIONL: 種種 /IP/PI & /PI & /PI FQ,FQ,FQ,FQ,FQ, F,PI,F OM Optional 種種不不. FRN 電 FR 請 R 手手改不 0 ohm FRN:0V00000 FR:0V00000 M PI FLH OM OPTIONL: 種種 /M/PI & /M/PI /PI & /PI UTek omputer Inc. PI ddie hiu P-VM O 0. ate: Friday, March, 00 heet 0 of

{,9,} O_RMRT# {9} O_PWRTN#IN {} O_PWRTN# {} TT# {,} _LP# {} O_PON# {} _TX_PWROK,} V_UL_UK_W {,,} O_PWROK {} O_VW# {} O_RTON#_IO {} O_PM# {0} RT#_I {} O_PIRT#_PIX {} O_PIRT#_PIX V OR Ohm NOT:Hardware trapping(jp~jp). 00 L V V V JP(TR#)--nable erial ROM 0=isable, =nable JP(RT#)--HFR 0=Write h to Location Twice, =Write h to Location Twice JP(OUT)--nable K 0=isable, =nable.kohm ORN JP(FN_T)--PUFNOUT0 Initial peed =00% uty, 0=0% uty JP(N_TL)--nable VRM0 onfigure =VI is VRM0, 0=VI is TTL JP(N_)--nable U lue Logic =nable, 0=isable JP(FN_T)--PUFNOUT Initial peed =00% uty, 0=0% uty.kohm ORN.KOHM ORN 0KOhm OR9.KOHM ORN.KOHM ORN.KOHM ORN.KOHM ORN V V Please place OR & O near IO side. Regin.KOHM ORN.KOHM ORN OR OR0.KOhm 0T OR.KOhm O_K_RT# V V {} _M_IO {} LRQ0# {0,,9} F_RIRQ# {,0,,0,9} _PLTRT# 0 {0,,9} F_FRM# {0,,9} F_L0 {0,,9} F_L {0,,9} F_L {0,,9} F_L {} _LP_IO O_PWRTN#IN_R O {0,0} H_VI UF/0V {0,0} H_VI /W {0,0} H_VI {0,0} H_VI {0,0} H_VI {0,0} H_VI {0,0} H_VI {0,0} H_VI0 OR {} O_0 {} O_K_RT#.KOhm F_L0 F_L F_L F_L O_PON#_R 0T O_K_RT# OU IOLK LRQ# RIRQ 0 LRT# 9 LFRM# L0 L L L PILK RMRT#/P PIN#/P POUT#/P P/U# U#/P PON#/P P/TXP PWROK/P 9 P0/PWR 9 P/VW# 9 P/RTON# PM# 9 RTOUT0# 9 RTOUT# RTOUT#/P {0,} H_THRM_PU {0,} H_THRM_PU- VI VI VI VI VI VI VI VI0 9 0M 0 KRT 0 PUTIN 0 PU- VI ystem lock K/M LP I/F PU TMPIN PI Reset Power-on ontrol U VRION U Version erial port NW PU K/M I/F OPN# Parallel Port P P P P P 9 P 0 P P0 T# F# RR# INIT# LIN# K# UY P LT MLK/P MT/P KLK/P KT/P TR#/P/PNROM RT#/P/HFR OUT/P/PNK #/P RI#/P0 T#/P 9 R#/P 0 IN/P Floppy I/F PU FN (PWM) KH# H# RT# WP# TRK0# W# W# 0 TP# 9 IR# # MO# INX# RVN0 PUFNOUT0 T_V OR MOhm mb_r00 O_INTRUR# {} O_P {} O_P {} O_P {} O_P {} O_P {} O_P {} O_P {} O_P0 {} O_T# {} O_F# {} O_RR# {} O_INIT# {} O_LIN# {} O_K# {} O_UY {} O_P {} O_LT {} O_M_LK {} O_M_T {} O_K_LK {} O_K_T {} O_TR#_R O_RT#_R O_TX_R O_KH# {} O_HL# {} O_RT# {} O_WPT# {} O_TRK0# {} O_WT# {} O_WT# {} O_TP# {} O_IR# {} O_RV# {} O_MTR# {} O_INX# {} O_NL# {} V V /JP.KOHM ORN V OR0.KOhm /JP OR.KOhm /W OR KOhm % V IO RV. 0. eta tandard ircuit IO_W /W /JP OR KOhm % W O_0. T.KOHM ORN0 O_PUFN_PWM {} O_TR#_R {} O_RT#_R {} O_TX_R {} O_#_R {} O_RI#_R {} O_T#_R {} O_R#_R {} O_RX_R {} V.KOHM ORN0 R.0 預預 OR {} {} {} O_N_ O_IO_P9 O_IO_P90 V.KOhm OR /JP /JP {} O_PIRT#_PIX {} O_PIRT#_PIX.KOHMORN0 ORN0 V.KOHMORN0 ORN0.KOHM ORN0.KOHM ORN0 V /JP /JP 0.UF/V O /W.KOhm OR 0.UF/V O /W {} 此須須須 IO O_RRX.KOHM ORN V {,} J_OVT.KOHM ORN0.KOHM ORN0 {} O_T {} H_PI_IO {} IO_PI O_IO_P O_IO_P {} H_TLRF_OV# {} H_TLRF_OV# {} H_TLRF_OV# {} O_.V_UL_OV# {} O_.V_UL_OV# O_PUFNOUT_T O_PUFNOUT0_T O_N_TL O_N_ ORN.KOHM Push-pull (V level) YFNOUT 0 P0/PUFNOUT T 0 PI 0 PI PI I/F Fan ontrol () P0/RI# P/# P/O 9 P/ P/K P/TR# 0 P/RT# 9 P/R# P/T# P/OUT/IRTX/FN_T P/IN/IRRX /FN_TPL P0/WTO#/N_TL P/UL/N_ 9 RTOUT#/P/ 90 RTOUT#/P/L UXFNOUT MI#VT# 0 UXTIN WH- NO trapping/ Jumperless PIO Hardware Monitoring Fan Tachometer H/W Monitor Power & M/ TempIN PUFNIN0 UXFNIN0 YFNIN I/UXFNIN P/PUFNIN 9 Voltage Input igital/nalog Power VIN0 99 VIN 9 PUVOR 00 VIN 9 VIN 9 igital VRF 0 YTIN 0 Vtt 0 V V V V 9 V VT V 0 V N 09 N 0 O_N_PUFN {} O_N_HFN {} O_VIN {} O_VIN {} O_VRF {} O_TR_M {} VTTPU 0.UF/V O V <Variant Name> UTeK OMPUTR IN V VOR O_PWROK O_PWROK_R T_V ate: Friday, March, 00 heet of V V 0.UF/V O9 0.UF/V O /W P-VM O 0.UF/V O OR KOhm % OR.KOhm OR KOhm % O9 0UF/0V 個須須 IO 00 0.UF/V O 0.UF/V O WH-.W. Hunag 0.

0. eta O_KM_V_F KM ----Mouse (reen) O_KM_V_F ----Keyboard (Purple) ORN.KOHM O_KM_V_L ORN.KOHM.Please choose K_U or KM connector.please choose KPWR (dual power or with jumper) {} {} O_K_T O_M_T ORN OL O_K_T_R Ohm O_KM_V_F ORN.KOHM /00Mhz O_K_T_L ON 0PF/0V XR KM V N KT P MOU I_ 0 V N N O_K_LK_L ON 0PF/0V XR MT 9 MLK ORN OL OL I_ Ohm O_M_T_R O_M_T_L O_M_LK_L MINI_IN_XP /00Mhz /00Mhz I_ I_ I_ N KLK OL /00Mhz O_K_LK_R O_M_LK_R O_KM_V_F ORN.KOHM ORN Ohm ORN Ohm O_K_LK {} O_M_LK {} ON 0PF/0V XR ON 0PF/0V XR Intrudor KPWR(ual Power) T_V V_UL_UK OF./V O 0.UF/V /KPWR OL O_KM_V_F O_KM_V_L /00Mhz O 0.UF/V /KPWR HI HR_XP_K V O_INTRUR#_R OR 0MOhm O_INTRUR# {} OQ HN0 HI: MINI_JUMPR UTeK OMPUTR IN P-VM O.W. Hunag WH-(KM/U) ate: Friday, March, 00 heet of 0.

0. eta Floppy,tandard (efault) V 0.KOHM ORP 0.KOHM ORP 0.KOHM ORP 0.KOHM ORP 0.KOHM ORP 0.KOHM ORPF 0.KOHM ORP 9 0.KOHM ORPH FLOPPY 9 9 9 0 0 0 O_NL# {} O_INX# {} O_MTR# {} O_RV# {} O_IR# {} O_TP# {} O_WT# {} O_WT# {} O_TRK0# {} O_WPT# {} O_RT# {} O_HL# {} O_KH# {} OX_H_XP_K UTeK OMPUTR IN P-VM O.W. Hunag WH-(FLOPPY) ate: Friday, March, 00 heet of 0.

0. eta OM Right ngle (efault) OM 0 I_0 RIN Function V V (reen) (tandard) O_# O_R# O_RX O_RT# O_TX O_T# O_TR# O_RI# 9 R# RRT# # RRX TTX T# TR# RRI# I U_9P {} O_# O_R# O_RX O_RT# O_TX O_T# O_TR# O_RI# O_RI# 0PF/0V ON XR 0PF/0V ON XR 0PF/0V ON XR 0PF/0V ON XR 0PF/0V ON XR 0PF/0V ON XR O9 0.UF/V mb_c00 /OM 0PF/0V ON XR 0PF/0V ON XR -V O 0.UF/V mb_c00 /OM 9 0 V R R R Y Y R Y R V OU V 0 RY 9 RY RY RY RY PWR O0 0.UF/V mb_c00 /OM O_#_R {} O_R#_R {} O_RX_R {} O_RT#_R {} O_TX_R {} O_T#_R {} O_TR#_R {} O_RI#_R {} UTeK OMPUTR IN WH-(OM).W. Hunag P-VM O ate: Friday, March, 00 heet of 0.

0. eta Hardware Monitor for Temperature O_VRF {} OM Option Voltage Mode urrent Mode (efault) {0,} H_THRM_PU OR9 KOhm % /Voltage Mode OR0 0KOhm % O 0.UF/V OR9 V X O 00PF/0V /urrent Mode/Voltage Mode O_TR_M {} O V V {0,} H_THRM_PU- OJP OT 0KOhm % O 0.UF/V /W HORTPIN /W Hardware Monitor for VIN V V VOR OR KOhm % OR 0KOhm % V VOR VIN OR O.9KOhm 0.UF/V % mb_c00 /W O_VIN {} O_VIN {} OR O.99KOhm 0.UF/V % mb_c00 /W Refer to schematic check list O 0.UF/V mb_c00 /W UTeK OMPUTR IN P-VM O.W. Hunag WH-(H/W Monitor) ate: Friday, March, 00 heet of 0.

0. eta -U P LPT I_ I_ LIN# LT P UY K# P P P P P 9 O_LT O_P O_UY O_K# O_P_R O_P_R O_P_R O_P_R O_P_R O_LIN#_R O_P_R O_INIT#_R O_P_R O_RR# O_P0_R O_F#_R O_T#_R V O_LPT_V O T# LPT O_LT {} O_P {} O_UY {} O_P_R O_P_R O_P_R O_P_R O_P_R O_LIN#_R O_P_R O_INIT#_R O_P_R O_P0_R O_F#_R O_T#_R O_K# {} O_P {} O_P {} O_P {} O_P {} O_P {} O_LIN# {} O_P {} O_INIT# {} O_P {} O_RR# {} O_P0 {} O_F# {} O_T# {} XR XR XR XR XR XR XR XR XR XR XR XR XR XR XR XR 0PF/0V ON 0PF/0V ON 0PF/0V ON 0PF/0V ON 0PF/0V ON.KOHM ORP.KOHM ORPF.KOHM ORP 0 0 ORN Ohm ORN Ohm ORN Ohm ORN Ohm ORN9 Ohm 0PF/0V ON 0PF/0V ON.KOHM ORP.KOHM ORPF.KOHM ORP 9.KOHM ORPH.KOHM ORP.KOHM ORP 0 0 0 ORN Ohm ORN9 Ohm ORN9 Ohm ORN9 Ohm 0PF/0V ON 0PF/0V ON.KOHM ORP.KOHM ORP.KOHM ORP 0 0 PINIT# RROR# F# I_ P P P0 0 0 9 _U_P 0PF/0V ON 0PF/0V ON 0PF/0V ON 0PF/0V ON 0PF/0V ON 0PF/0V ON.KOHM ORP.KOHM ORP.KOHM ORP 9.KOHM ORPH 0 0 0 ORN Ohm 0PF/0V ON 0PF/0V O.KOhm OR 0 0 0 0 0 0 ORN Ohm ORN Ohm UTeK OMPUTR IN P-VM O WH-(LPT) Regin_hiang ate: Friday, March, 00 heet of.00

{} O_N_PUFN {} _N_PUFN OR0.KOhm OR0.KOHM ORN0.KOHM PU Fan ORN0 ORN0 O_N_PUFN_R O_N_PUFN_R /T.KOHM V ORN0.KOHM V PU_FN O_N_PUFN_R PUFN_PWM NP_N WFR_H_P O 0.UF/V mb_c00 /PU_FN {} O_N_HFN OR0 ORN ORN O_N_HFN_R O_N_HFN_R hassis Fan.KOHM.KOHM ORN.KOHM V ORN.KOHM H_FN V O_N_HFN_R N N WFR_H_P 0. eta V O0 0.UF/V mb_c00 /H_FN V V V PUFN_PWM Level hift V ORN0.KOHM /PU_FN_ ORN0.KOHM /PU_FN_ ORN0.KOHM /PU_FN_ ORN0.KOHM /PU_FN_ O0 TW /PU_FN_IO PUFN_PWM {} _PUFN_PWM {} O_PUFN_PWM OR /PU_FN_ OR0 0 PUFN_PWM_Q PUFN_PWM_R OQ0 PM90 /PU_FN_ OR /PU_FN_IO /PU_FN_IO L ORN 00 PU_FN OM Option ontrol IO ontrol Power Fan OR0 /PU_FN_ X /PU_FN_IO V OR X V O0 X V OR V X ORN0 V X PWR_FN V OQ0 V X V N N WFR_H_P O9 0.UF/V mb_c00 /PWR_FN UTeK OMPUTR IN P-VM O.W. Hunag WH-(FN/Intrudor) ate: Friday, March, 00 heet of 0.

0. eta 二種個 {} _TX_PWROK Pin TX onnector V V V V V 0.UF/V /PWR_ON mb_c00 TXPWR V V V V PWR0K 9 V 0 V V V hold hold POWR_ON_P V -V PON# 9 -V 0 V V V V -V V PF/0V O_PON# {} 二種個 Pin V onnector TXV Regin 自自自自 NP_N POWR_ON_P V_PU 0.UF/V /PWR_ON mb_c00 ypass/mi apacitor V V V -V V 0.UF/V 0.UF/V 9 0.UF/V 0 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V /PWR_ON mb_c00 /PWR_ON mb_c00 /PWR_ON mb_c00 /PWR_ON mb_c00 /PWR_ON mb_c00 /PWR_ON mb_c00 /PWR_ON mb_c00 /PWR_ON mb_c00 U TeK omputer IN P-VM O Power onnnecter Kenny hen ate: Friday, March, 00 heet of 0.

Front Panel tandard ircuit Panel/ Front Panel/Intel PowerONN Panel/L /crewhole /Hottart //0/ Pin(onnecter) TX/uTX RIL/Hottart 0. eta PRT Reference 電 IO 共請 O 並並 00 編個 an be del if you don't connect to UIO H_L L RV. O_0. eta I_H_L- {} _PP {} _PL- {} T_TL# {0} I_IT# O0 WW V VUL ORN00 ORN00 R.0:Regin hange ORN00 T circuit value from 00 ohm to 0 ohm V _PL _PL- I_H_L- I_H_L PNL {,,} O_RTON# OR0.KOhm mb_r00 {} O_PWRTN#IN O_RTON# O0 000PF/0V /PNL O0 000PF/0V /PNL 9 0 O0 000PF/0V /PNL _PP O0 000PF/0V /PNL V V UZZR 00Hz /PNL _PKR need to check the output type of Push-pull or O/ {} _PKR O00 0.UF/V mb_c00 O0 0.UF/V /PNL mb_c00 olor:white OR0.KOhm mb_r00 HR_X0P O0 0.UF/V /PNL mb_c00 _PKR_R O0 0.UF/V /PNL mb_c00 OR0 Ohm mb_r00 _PKR_Q OQ00 PM90 hange the net name to combine the H L active 請請請如請 Net name 自改 : I_ITP# I_ITP# I_IT# I_IT# T_TL# T_TL# 請不連請 net 請 elete, 並並 x hipset ction INTL Nvdia VI I IH IH IH9 K0 MP VT VT 9L ()Keep "OR0" ()The "O_RTON#" is connected to ()elete "O_RTON#" off-page net on IO page ()Keep "OR0" ()The "O_RTON#" is connected to ()elete "O_RTON#" off-page net on IO page ()dd serial R ( ohm) on "O_RTON#" by P note for issue.please add R on chipset page. ()elete "OR0" ()The "O_RTON#" is connected to IO ()heck pull-up resistor & pull-up level on IO page ()elete "OR0" ()The "O_RTON#" is connected to IO ()heck pull-up resistor & pull-up level on IO page R.0:Regin hange ORN00 T circuit value from 00 ohm to 0 ohm tandby L ORN00 V ORN00 TI 00 ()elete "OR0" ()The "O_RTON#" is connected to IO ()heck pull-up resistor & pull-up level on IO page 二種個是並並 P 或電 PM 並並 Hot tart P_TRIR O_TN {} O_L_PWR _PWR RN ()The "O_TN[:]" of PI need pull-up, Plz check pull-up resistor value & level on IO or page () 種種請 PI 是要是 standby plane, 電以可可 MI 請 PIO, default 電不值 PI 或 PO, 是要需,, 電以可可 PI state 不不不 reset 或 power OK 不被請 HR_XP /HOTTRT U TeK omputer IN Panel&Hottart Kenny hen P-VM O ate: Friday, March, 00 heet 9 of 0.