a b c d e f g C2 C1 2

a b c d e f g C2 C1 2

IN1 IN2 0 2 to 1 Mux 1 IN1 IN2 0 2 to 1 Mux 1 Sel= 0 M0 High C2 C1 Sel= 1 M0 Low C2 C1 1 to 2 decoder M1 Low 1 to 2 decoder M1 High 3

BCD 1Hz clk 64Hz BCD 4 4 0 1 2 to 1 Mux sel 4 C2 C1 sel 1 to 2 decoder M0 M1 4

clk Clk_out1 Clk_in Clk_out2 Clk_1Hz Clk_64Hz clk ce Rst-n q_one q_ten 4 4 q_one Seg-out Seg-one-en q_ten clk Seg-ten-en Seg-en Clk_div_1_64 Up_counter4_10 Bin2seg0_scan ce Rst_n Seg_en Led_en 4 Led_en bin 4 to 8 decoder Bin2led Led() Led(6) Led(5) Led(4) Led(3) Led(2) Led(1) Led(0) 5

6 b b a f g COM1 COM2 c e dot d SEGx2 VCC LED0 Led_en a LED5 e SW1 Seg_ten_en LED3 LED1 ce Seg_out0 SW2 SW3 U EPM064S/LCC44 4 5 6 8 9 11 12 14 16 1 18 19 20 21 24 25 26 2 3 39 41 40 43 I/GCLK1 d Seg_out6 Seg_en CLK f Seg_out5 LED2 Seg_one_en g C2 VCC Seg_out1 Seg_out3 C1 Seg_out4 SW4 Seg_out2 Rst_n LED4 LED c dot LED6

11 ---------------------------------------------- 12 entity clk_div_1_64 is 13 port( 14 clk_in : in std_logic; 15 clk_out1: out std_logic; 16 clk_out2: out std_logic 1 ); 18 end clk_div_1_64; 19 20 architecture a of clk_div_1_64 is 21 22 ------SIGNAL DECLARED------------- 23 signal cnt : std_logic_vector(20 downto 0); --** counter 24 signal reset: std_logic; --reset 25 begin 26 2 ------PROGRAM BODY-------------------- 28 process (clk_in) 29 begin 30 if reset='1' then 31 cnt<="000000000000000000000"; 32 elsif clk_in'event and clk_in='1' then 33 cnt<=cnt+1; 34 end if; 35 end process; 36 3 reset<='1' when cnt=25000000 else '0'; --** divisor 25000000 38 clk_out1<=cnt(20); 39 clk_out2<=cnt(14); 40 41 end a;

12 entity up_counter4_10 is 13 port( 14 clk : in std_logic; --system clock 15 rst_n : in std_logic; --reset 16 ce : in std_logic; --chip enable 1 q_one : out std_logic_vector(3 downto 0); --counter one output 18 q_ten : out std_logic_vector(3 downto 0) --counter ten output 19 ); 20 end up_counter4_10; 21 22 architecture a of up_counter4_10 is 23 24 ---------SIGNAL DECLARED------------------------ 25 signal q_one_temp : std_logic_vector(3 downto 0); --temp q_one 26 signal q_ten_temp : std_logic_vector(3 downto 0); --temp q_ten 2 begin 28 8

29-----------PROGRAM BODY-------------------------- 30 process (clk) 31 begin 32 if (ce='0' or rst_n='0') then 33 q_one_temp<="0000"; 34 q_ten_temp<="0000"; 35 elsif clk'event and clk='1' then 36 if (q_one_temp>=9) then --carry in (one) 3 q_one_temp<="0000"; 38 if (q_ten_temp>=9) then --carry in (ten) 39 q_ten_temp<="0000"; 40 else 41 q_ten_temp<=q_ten_temp+1; 42 end if; 43 else 44 q_one_temp<=q_one_temp+1; 45 end if; 46 end if; 4 end process; 48 49 q_one<=q_one_temp; 50 q_ten<=q_ten_temp; 51 52 end a; 9

23 entity bin2seg0_scan is 24 port ( 25 clk : in std_logic; --64hz clock 26 seg_en: in std_logic; --segment enable 2 q_one: in std_logic_vector(3 downto 0); --binary input of one 28 q_ten: in std_logic_vector(3 downto 0); --binary input of ten 29 seg_out : out std_logic_vector(6 downto 0); --segment output 30 seg_one_en: out std_logic; --segment one enable 31 seg_ten_en: out std_logic --segment ten enable 32 ); 33 end bin2seg0_scan; 34 35 architecture arch of bin2seg0_scan is 36 3-------SIGNAL DECLARED------------------------------------------- 38 signal bin: std_logic_vector(3 downto 0); --binary code 39 signal seg: std_logic_vector(6 downto 0); --segment code 40 signal sel: integer range 0 to 1; --scan coutnter 41 begin 10

42 43 ---------PROGRAM BODY-------------- 44 ----------scan and signal assign--- 45 process (clk, seg_en) 46 begin 4 if clk'event and clk='1' then 48 if (seg_en='0') then 49 seg_one_en<='0'; 50 seg_ten_en<='0'; 51 sel<=0; 52 else 53 sel<=sel+1; 54 case sel is 55 when 0 => 56 bin<=q_one; 5 seg_out<=seg; 58 seg_one_en<='0'; 59 seg_ten_en<='1'; 60 when 1 => 61 bin<=q_ten; 62 seg_out<=seg; 63 seg_one_en<='1'; 64 seg_ten_en<='0'; 65 when others => 66 null; 6 end case; 68 end if; 69 end if; 0 end process; 1 11

2 ------binary to seven segment decoder----- 3 process (bin) 4 begin 5 case bin is 5 when "0000" => seg <= "1000000"; -- 0 active low '0' when "0001" => seg <= "1111001"; -- 1 8 when "0010" => seg <= "0100100"; -- 2 9 when "0011" => seg <= "0110000"; -- 3 80 when "0100" => seg <= "0011001"; -- 4 81 when "0101" => seg <= "0010010"; -- 5 82 when "0110" => seg <= "0000010"; -- 6 83 when "0111" => seg <= "1111000"; -- 84 when "1000" => seg <= "0000000"; -- 8 85 when "1001" => seg <= "0010000"; -- 9 86 when others => seg <= "1111111"; 8 end case; 88 end process; 89 90 end arch; 12

2 -------COMPONENT DECLARED--------------------- 11 entity up_scan_top is 28 ---------clk_div 1hz 64hz component---------- 12 port ( 29 component clk_div_1_64 13 clk : in std_logic; -- 1.8432 MHz 30 port( 14 rst_n : in std_logic; 31 clk_in : in std_logic; 15 ce : in std_logic; 32 clk_out1: out std_logic; 16 led_en : in std_logic; 33 clk_out2: out std_logic 1 seg_en : in std_logic; 34 ); 18 led : out std_logic_vector( downto 0); 35 end component; 19 seg_out : out std_logic_vector(6 downto 0); 36 20 seg_one_en: out std_logic; 3 ---------up_counter_4_10 component---------- 21 seg_ten_en: out std_logic 38 component up_counter4_10 22 ); 39 port( 23 end up_scan_top; 40 clk : in std_logic; --system clock 24 41 rst_n : in std_logic; --reset 25 architecture arch of up_scan_top is 42 ce : in std_logic; --chip enable46 end 26 component; 13

43 q_one : out std_logic_vector(3 downto 0); --counter one output 44 q_ten : out std_logic_vector(3 downto 0) --counter ten output 45 ); 46 end component; 4 48 ---------binary to segment decoder--------- 49 component bin2seg0_scan 50 port ( 51 clk : in std_logic; --64hz clock 52 seg_en : in std_logic; --segment enable 53 q_one : in std_logic_vector(3 downto 0); 54 q_ten : in std_logic_vector(3 downto 0); 55 seg_out : out std_logic_vector(6 downto 0); 56 seg_one_en: out std_logic; 5 seg_ten_en: out std_logic 58 ); 59 end component; 60 14

61 ---------binary to led8 decoder--------- 62 component bin2led0_10 63 port ( 64 led_en : in std_logic; 65 bin : in std_logic_vector (3 downto 0); led : out std_logic_vector ( downto 0) 6 ); 68 end component; 69 0 ---------SIGNAL DECLARED---------------------- 1 signal clk_1hz : std_logic; 2 signal clk_64hz: std_logic; 3 signal q_one: std_logic_vector(3 downto 0); 4 signal q_ten: std_logic_vector(3 downto 0); 5 6 begin 8 ----------Frequency divider---------- 9 u1: clk_div_1_64 port map (clk, clk_1hz, clk_64hz); 80 81 ----------4 bit up counter---------- 82 u2: up_counter4_10 port map (clk_1hz, rst_n, ce, q_one, q_ten); 83 84 ----------binary to LED decoder---------- 85 u3: bin2led0_10 port map (led_en, q_one, led); 86 8 ----------binary to seven segment decoder---------- 88 u4: bin2seg0_scan port map (clk_64hz, seg_en, q_one, q_ten, seg_out, 89 seg_one_en, seg_ten_en); 90 91 end arch; 15

16 VCC clk INPUT VCC led_en INPUT VCC seg_en INPUT VCC ce INPUT VCC rst_n INPUT seg_out[6..0] OUTPUT led[..0] OUTPUT seg_ten_en OUTPUT seg_one_en OUTPUT clk_in clk_out1 clk_out2 clk_div _1_64 inst clk rst_n ce q_one[3..0] q_ten[3..0] up_counter4_10 inst1 clk seg_en q_one[3..0] q_ten[3..0] seg_out[6..0] seg_one_en seg_ten_en bin2seg0_scan inst2 led_en bin[3..0] led[..0] bin2led0_10 inst3

CPLD Rst_n 222 Seg_out(0) 203 ce 223 Seg_out(1) 202 Seg_en 225 Seg_out(2) 201 clk 28 Seg_out(3) 200 Seg_out(4) 199 Seg_out(5) 198 Seg_out(6) 19 Seg_one_en 195 Seg_tne_en 194 1