4.1 VHDL VHDL 4-1 a b & c 4-1 2

4.1 VHDL 4.2 VHDL 4.3 VHDL 4.4 VHDL 4.5 1

4.1 VHDL 4.1.1 VHDL 4-1 a b & c 4-1 2

( 4-1 ) (1) a b c ( 1 ) (2) c=a b CPU VHDL 3

VHDL 4-2 a b & c a c b c a b 4-2 VHDL 4

1 ENTITY IS d0 & 1 q END d1 & sel 1 4-3 5

4-1 4-3 VHDL ENTITY mux2 IS GENERIC(m: TIME:=1ns) PORT (d0 d1 sel: IN BIT END mux2 q: OUT BIT) ARCHITECTURE connect OF mux2 IS SIGNAL tmp: BIT BEGIN PROCESS (d0 d1 sel) VARIABLE tmp1 tmp2 tmp3: BIT 6

BEGIN tmp1=d0 AND sel tmp2=d1 AND ( NOT sel) tmp3=tmp1 OR tmp2 tmp<=tmp3 q<=tmp AFTER m END PROCESS END connect 7

1) 4-1 GENERIC (m:time=1 ns) m 1 ns q<=tmp AFTER m tmp 1 ns q GENERIC q 8

2) ( ) : PORT( { }: { }: ) (1) 4-3 d0 d1 sel q 9

(2) 4-3 d0 d1 sel IN q OUT IN OUT 4-1 IN OUT INOUT BUFFER LINKAGE ( ) ( ) 10

4-1 OUT BUFFER 4-4 d clk q OUT & d clk q BUFFER (a) (b) 4-4 OUT BUFFER (a) OUT (b) BUFFER 11

(3) VHDL 10 : BIT BIT_VECTOR BIT 1 0 1 0 BIT ( 1 0 ) BIT_VECTOR 8 BIT_VECTOR 8 4-2 12

4-2 PORT (d0 d1 sel: IN BIT q: OUT BIT bus: OUT BIT_VECTOR(7 DOWNTO 0)) d0 d1 sel q BIT bus BIT_VECTOR (7 DOWNTO 0) bus 8 B7 B0 8 8 13

2 3 ( ) ( ) ( ) 14

ARCHITECTURE OF IS BEGIN END ARCHITECTURE OF IS END 15

1) OF IS ARCHITECTURE structural OF mux IS 2) ARCHITECTURE BEGIN 3) BEGIN END 16

4.1.2 VHDL (Object) 3 (Signal) (Variable) (Constant) 3 3 4-2 4-2 VHDL 3 ARCHITECTURE PACKAGE ENTITY PROCESS FUNCTION PROCEDURE 17

1 (Constant) : CONSTANT : := : CONSTANT VCC: REAL:=5.0 CONSTANT DALY: TIME:=100 ns CONSTANT FBUS: BIT_VECTOR:="0101" 18

2 (Variable) VHDL : VARIABLE : := VARIABLE x y: INTEGER VARIABLE count: INTEGER RANGE 0 TO 255:=10 tmp1 tmp2 tmp3 : tmp3:=tmp1+tmp2 AFTER 10 ns 19

3 (Signal) SIGNAL : := : SIGNAL sys_clk: BIT:= '0' SIGNAL ground: BIT:= 0 <= := s1 s2 s2 10 ns s1 : s1<=s2 AFTER 10 ns 20

4 1) <= := 2) ( BLOCK ) (PROCESS) (SUBPROGRAM) 3) ( 3 ) 21

4.1.3 1 4-3 32-2 147 483 647 2 147 483 647-1.0E+38 +1.0E+38 0 1 ASCII fs ps ns s ms sec min hr NOTE WARNING ERROR FAILURE ( 0 0 ) 22

2 VHDL : TYPE { } VHDL : TYPE { } 23

: (Enumerated) (Integer) (Real) (Floating) (Array) (Access) (File) (Record) (Time) ( ) 24

3 SUBTYPE IS STD_LOGIC_VECTOR : SUBTYPE iobus IS STD_LOGIC_VECTOR(7 DOWNTO 0) SUBTYPE digit IS INTEGER RANGE 0 TO 9 25

4 VHDL VHDL STD_LOGIC_1164 STD_LOGIC_ARITH STD_LOGIC_UNSIGNED 4-4 26

STD_LOGIC_1164 TO_STDLOGICVECTOR(A) TO_BITVECTOR(A) TO_STDLOGIC(A) TO_BIT(A) 4-4 BIT_VECTOR STD_LOGIC_VECTOR STD_LOGIC_VECTO BIT_VECTOR BIT STD_LOGIC STD_LOGIC BIT STD_LOGIC_ARITH INTEGER UNSDGNED SIGNED CONV_STD_LOGIC_VECTOR(A ) STD_LOGIC_VECTOR UNSIGNED SIGNED CONV_INTEGER(A) INTEGER STD_LOGIC_UNSIGNED CONV_INTEGER(A) STD_LOGIC_VECTOR INTEGER 27

5 VHDL : SIGNAL a: STD_LOGIC_VECTOR (7 DOWNTO 0) a<="01101010" 01101010 (String) (Bit_Vector) STD_LOGIC_VECTOR : CASE (a & b & c) IS WHEN "001"=>Y<="01111111" WHEN "010"=>Y<="10111111" END CASE 28

a&b&c ( C ) ' : a<=std_logic_vector ' ("01101010") SUBTYPE STD3BIT IS STD_LOGIC_VECTOR (0 TO 2) CASE STD3BIT ' (a & b & c) IS WHEN "000"=>Y<="01111111" WHEN "001"=>Y<="10111111" 29

6 IEEE STD_LOGIC STD_LOGIC_VECTOR VHDL BIT 0 1 'X' IEEE 1993 (IEEE STD1164) STD_LOGIC 9 : 30

'U' 'X' '0' 0 '1' 1 'Z' 'W' 'L' 0 'H' 1 '-' STD_LOGIC STD_LOGIC_VECTOR IEEE VHDL 31

4.1.4 VHDL 4 (Logical) (Relational) (Arithmetic) (Concatenation) NOT 4-5 32

4-5 AND OR NAND NOR XOR = /= < > <= >= + - & + - * / MOD REM ** ABS NOT 33

1 VHDL 6 NOT AND OR NAND NOR XOR 6 STD_LOGIC BIT STD_LOGIC_VECTOR C VHDL : X<=(a AND b) OR (NOT c AND d) 34

AND OR XOR : a<=b AND c AND d AND e a<=b OR c OR d OR e a<=b XOR c XOR d XOR e a<=((b NAND c) NAND d) NAND e ( ) a<=(b AND c) OR (d AND e) ( ) NOT 35

2 VHDL 10 + - * / MOD REM +( ) -( ) ** ABS ( ) ( ) ( ) 36

+ - * * 16 2000 / MOD REM 2 STD_LOGIC_VECTOR + ( ) - ( ) * 37

3 VHDL 6 = /= < <= > >= = /= (INTEGER) (REAL) (STD_LOGIC) (STD_LOGIC_VECTOR) 38

4 & 4 & 4 4 & 8 4-6 39

en & y(0) b(0) b(1) b(2) b(3) & & & y(1) y(2) y(3) a(0) y(4) a(1) y(5) a(2) y(6) a(3) y(7) tmp_b b AND(en & en & en & y a & tmp_b; 4-6 40

4-6 en b(0) b(3) y(0) y(7) : y(0)=b(0) y(2)=b(2) y(4)=a(0) y(6)=a(2) y(1)=b(1) y(3)=b(3) y(5)=a(1) y(7)=a(3) 41

: tmp_b<=b AND (en&en&en&en) y<=a&tmp_b b 4 en 4 4 a 4 b ( ) 8 y : tmp_b<=(en en en en) : a<=(a tmp_b) 42

tmp_b<=(3=>en 2=>en 1=>en 0=>en) tmp_b<=(3 DOWNTO 0=>en) OTHERS : tmp_b<=(others=>en) OTHERS b b(2) 0 en tmp_b<=(2=>'0' OTHERS=>en) 43

4.1.5 (ATTRIBUTE) VHDL 44

1 'EVENT 'EVENT D D VHDL? 'EVENT 4-6 D 4-6 PROCESS (clk) BEGIN IF(clk'EVENT AND clk='1') THEN q<=d END IF END PROCESS 45

2 'RANGE 'REVERSE_RANGE VHDL RANGE REVERSE_RANGE 4-7 FUNCTION vector_to_int(vect: STD_LOGIC_VECTOR) RETURN INTEGER IS VARIABLE result: INTEGER:=0 BEGIN FOR i IN vect'range LOOP result:=result*2 IF Vect(i)= '1' THEN result:=result+1 END IF END LOOP RETURN result END vector_to_int 46

4.2 VHDL 4.2.1 VHDL VHDL 5 1 4-8 47

4-8 ENTITY mux2 IS PROT(d0 d1 sel: IN BIT q: OUT BIT) END mux2 ARCHITECTURE rtl OF mux2 IS BEGIN PROCESS (d0 d1 sel) VARIABLE tmp1 tmp2 tmp3: BIT BEGIN tmp1:=d0 AND sel tmp2:=d1 AND (NOT sel) tmp3:=tmp1 OR tmp2 q<=tmp3 END PROCESS END rtl 48

2 4-9 4-9 LIBRARY IEEE -- USE IEEE.STD_LOGIC_1164.ALL -- ENTITY mux2 IS -- PORT(d0 d1 sel: IN STD_LOGIC q: OUT STD_LOGIC) END mux2 ARCHITECTURE rtl1 OF mux2 IS -- BEGIN PROCESS(d0 d1 sel) VARIABLE tmp1 tmp2 tmp3: STD_LOGIC BEGIN tmp1:=d0 AND sel tmp2:=d1 AND(NOT sel) tmp3:=tmp1 OR tmp2 END PROCESS END rtl1 49

ARCHITECTURE rtl2 OF mux2 IS -- END rtl2 CONFIGURATION rtl_mux2 OF mux2 IS FOR rtl1 END FOR END rtl_mux2 -- 50

3 VHDL STD_LOGIC STD_LOGIC_VECTOR SIGNAL a: STD_LOGIC SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0) a<='x' --X b<="xxxx" --X 51

VHDL ( ) (1) (2) _ ( ) (3) _ SIGNAL a_bus: STD_LOGIC_VECTOR(7 DOWNTO 0) SIGNAL 302_bus:...-- SIGNAL b_@bus:...--@ SIGNAL a bus:...-- _ SIGNAL b_bus_...-- _ 52

4.2.2 VHDL 3 : BLOCK PROCESS SUBPROGRAMS 53

1 BLOCK 1) BLOCK BLOCK : : BLOCK BEGIN END BLOCK 54

2) BLOCK VHDL BLOCK BLOCK VHDL BLOCK 4-7 55

ENTITY separate ARCHITECTURE BLOCK1 BLOCK2 1 3 2 4 BLOCK 1: BLOCK BLOCK 2: BLOCK BLOCK3 BLOCK4 BLOCK 3: BLOCK BLOCK 4: BLOCK 4-7 BLOCK 56

3) BLOCK BLOCK VHDL (Concurrent Statement) VHDL 57

2 (PROCESS) 1) PROCESS PROCESS : : PROCESS( 1 2 ) BEGIN END PROCESS PROCESS PROCESS END PROCESS PROCESS PROCESS 4-12 58

4-12 ENTITY mux IS PORT(d0 d1 sel: IN BIT q: OUT BIT) END mux ARCHITECTURE connect OF mux IS BEGIN cale: PROCESS(d0 d1 sel) VARIABLE tmp1 tmp2 tmp3: BIT BEGIN tmp1:=d0 AND sel tmp2:=d1 AND (NOT sel) tmp3:=tmp1 OR tmp2 q<=tmp3 END PROCESS END connect 59

2) (PROCESS) VHDL BLOCK PROCESS BLOCK PROCESS BLOCK C Pascal VHDL PROCESS SUBPROGRAMS 60

3) PROCESS PROCESS 1 PROCESS PROCESS PROCESS(d0 d1 sel) d0 d1 sel VHDL ( 0 1 1 0 ) PROCESS PROCESS PROCESS PROCESS 61

4) (PROCESS) 4-12 PROCESS PROCESS PROCESS 4-8 62

to_a '1' A B to_b '1' ENTITY pros_com IS PORT(event_a IN BIT); END pros_com; ARCHITECTURE catch_ball OF pros_com IS SIGNAL to_a, to_b BIT: '0'; BEGIN A PROCESS(event_a, to_a) BEGIN IF(event_a'EVENT AND event_ OR (to_a' EVENT AND to_a '1' THEN to_b '1'AFTER 20 ns, '0'AFTER 30 ns END IF; END PROCESS A; B: PROCESS(to_b) BEGIN IF(to_b' EVENT AND to_b '1') THEN to_a '1' AFTER 10 ns, '0' AFTER 20 ns; END IF; END PROCESS B; END catch_ball; 63

4-8 A B A B to_b='1' to_b B to_b to_b='1' B B A to_a='1' to_a A to_a to_a='1' A B 64

3 (SUBPROGRAM) VHDL (Procedure) (Function) 65

1) (1) VHDL : PROCEDURE ( 1 2 ) IS ( ) BEGIN ( ) END PROCEDURE VHDL 66

4-13 PROCEDURE vector_to_int ( z: IN STD_LOGIC_VECTOR x_f1ag: OUT BOOLEAN q: INOUT INTEGER) IS BEGIN q:=0 x_f1ag:=false FOR i IN z RANGE LOOP q:=q*2 IF (z(i)=1) THEN q:=q+1 ELSIF(z(i) /=0) THEN x_f1ag:=true END IF END LOOP END vector_to_int 67

x_flag=true z x_flag q IN OUT INOUT 4-14 4-14 PROCEDURE shift( din: IN STD_LOGIC_VECTOR SIGNAL dou: OUT STD_LOGIC_VECTOR) END shift 68

(2) PROCESS OUT INOUT 69

2) (1) VHDL : FUNCTION ( 1 2 ) RETURN IS BEGIN RETURN END VHDL FUNCTION IN FUNCTION FUNCTION 70

3) (1) 4-12 PROCESS(...) BEGIN vector_to_int(z x_flag q) END PROCESS BLOCK PROCESS 71

(2) BLOCK PROCESS 4-14 selq<=digit_sel(comcnt,min 10,min,sec 10,sec,sec 11,sec 12) segment<=seg_dec(selq) common<=com_dec(comcnt) VHDL 72

4.2.3 1 (Library) UNIX MS-DOS VHDL : LIBRARY VHDL 73

1) VHDL 5 IEEE STD ASIC WORK (1) IEEE IEEE STD_LOGIC_1164 IEEE SYNOPSYS STD_LOGIC_ARITH STD_LOGIC_UNSIGNED IEEE 74

(2) STD STD VHDL STANDARD VHDL STANDARD STD TEXTIO TEXTIO LIBRARY STD USE STD.TEXTIO.ALL 75

(3) ASIC VHDL ASIC ASIC (4) WORK WORK VHDL WORK (5) 76

2) (1) 5 WORK STD 3 LIBRARY ( ) : USE LIBRARY_name.package_name.ITEM.name : LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL 77

(2) 4-16 4-16 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY and1 IS END and1 ARCHITECTURE rtl of and1 IS 78

END rtl CONFIGURATION s1 OF and1 IS END s1 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY or1 IS CONFIGURATION s2 OF or1 IS END s2 79

2 (Package) C include VHDL USE : USE IEEE.STD_LOGIC_1164.ALL VHDL STD_LOGIC_1164 80

: PACKAGE IS END PACKAGE BODY IS END 81

(Header) (Package Body) 4-14 82

4-17 LIBRARY IEEE USE IEEE STD_LOGIC_1164.ALL PACKAGE upac IS CONSTANT k: INTEGER:=4 TYPE instruction IS(add sub adc inc srf slf) SUBTYPE cpu_bus IS STD_LOGIC_VECTOR(k-1 DOWNTO 0) END upac 83

CPU cpu_bus 4 WORK USE WORK.upac.inctruction 84

3 (Configuration) 85

: CONFIGURATION OF IS END : CONFIGURATION OF IS FOR END FOR END 86

4-18 LIBRARY STD USE STD.STD_LOGIC.ALL ENTITY counter IS PORT(load clear clk: IN T_WLOGIC Data_in: IN INTEGER Data_out: OUT INTEGER) END counter ARCHITECTURE count_255 OF counter IS BEGIN PROCESS(clk) VARIABLE count: INTEGER:=0 BEGIN 87

IF clear='1' THEN Count:=0 ELSIF load='1' THEN Count:=data_in ELSIF(clk EVENT) AND (clk='1') AND (clk'last_value='0') THEN IF(count=255) THEN Count:=0 ELSE Count:=count+1 END IF END IF data_out<=count END PROCESS END count_255 88

ARCHITECTURE count_64k OF counter IS BEGIN PROCESS(clk) VARIABLE count: INTEGER:=0 BEGIN IF(clear='1') THNE count:=0 ELSIF load='1' THEN count:=data_in ELSIF(clk EVENT) AND (clk='1') AND (clk'last_value='0') THEN IF(count=65535) THEN count:=0 ELSE 89

count:=count+1 END IF END IF data_out<=count END PROCESS END count_64k CONFIGURATION small_count OF counter IS FOR count_255 END FOR END small_count CONFIGURATION big_count OF counter IS FOR count_64k END FOR END big_count 90

4-18 INTEGER( ) ( 8 16 ) 91

4.3 VHDL 4.3.1 1 VHDL a<=b a b a b <= 92

: z<=a NOR (b NAND c) 3 a b c : a<=b AFTER 5 ns b 5 ns a 5 ns 93

4-19 ENTITY and2 IS PORT (a b:in BIT END and2 c:out BIT) ARCHITECTURE and2_behav OF and2 IS BEGIN c<=a AND b AFTER 5 ns END and2_behav 94

i0 i1 i2 i3 b a q 4-9 95

4-20 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL USE IEEE.STD_LOGIC_UNSIGNED.ALL ENTITY mux4 IS PORT (i0 i1 i2 i3 a b:in STD_LOGIC END mux4 ARCHITECTURE behav OF mux4 IS BEGIN SIGNAL sel:integer WITH sel SELECT q:out STD_LOGIC) q<=i0 AFTER 10 ns WHEN 0 96

i1 AFTER 10 ns WHEN 1 i2 AFTER 10 ns WHEN 2 i3 AFTER 10 ns WHEN 3 X AFTER 10 ns WHEN OTHERS sel<= 0 WHEN a='0' AND b='0' ELSE 1 WHEN a='1' AND b='0' ELSE 2 WHEN a='0' AND b='1' ELSE 3 WHEN a='1' AND b='1' ELSE 4 END behav 97

2 VHDL VHDL 1) VHDL 98

( ) 4-10 20 ns a 10 b 20 ns 20 ns 99

b<=a AFTER 10 ns 100

2) VHDL ASIC 4-10 4-11 4-11 10 ns 20 ns 10 101

b a AFTER 20 ns a b 0 10 20 30 40 50 ns 4-10 102

b TRANSPORT a AFTER 20 n a b 0 10 20 30 40 50 ns 4-11 103

: b<=transport a AFTER 20 ns TRANSPORT 104

3 VHDL : ARCHITECTURE sample OF sample IS BEGIN a<=b AFTER 5 ns a<=d AFTER 5 ns END sample 105

sample a b d a b 5 ns a d 5 ns a a b d STD_LOGIC_1164 4-21 STD_LOGIC_1164 106

OF STD_ULOGIC - - 4-21 ACKAGE STD_LOGIC_1164 IS YPE STD_ULOGIC IS ('U' 'X' '0' '1' 'Z' 'W' 'L' 'H' '_') YPE STD_ULOGIC_VECTOR IS ARRAY (NATURAL RANGE< >) UNCTION resolved(s:std_ulogic_vector) RETURN STD_ULOGIC UBTYPE STD_LOGIC IS resolved STD_ULOGIC - - YPE STD_LOGIC_VECTOR IS ARRAY(NATURAL RANGE< >) OF STD_LOGIC ND STD_LOGIC_1164 ACKAGE BODY STD_LOGIC_1164 IS 107

CONSTANT resolution_table:stdlogic_table:=( - - U X 0 1 Z W L H - - ('U' 'U' 'U' 'U' 'U' 'U' 'U' 'U' 'U') -- U ('U' 'X' 'X' 'X' 'X' 'X' 'X' 'X' 'X') -- X ('U' 'X' '0' 'X' '0' '0' '0' '0' 'X') -- 0 ('U' 'X' 'X' '1' '1' '1' '1' '1' 'X') -- 1 ('U' 'X' '0' '1' 'Z' 'W' 'L' 'H' 'X') -- Z ('U' 'X' '0' '1' 'W' 'W' 'W' 'W' 'X') - - W ('U' 'X' '0' '1' 'L' 'W' 'L' 'W' 'X') - - L ('U' 'X' '0' '1' 'H' 'W' 'W' 'H' 'X') -- H ('U' 'X' 'X' 'X' 'X' 'X' 'X' 'X' 'X') -- - ) FUNCTION resolved (s:std_ulogic_vector) RETURN STD_ULOGIC IS - - 108

VARIABLE result:std_ulogic:= 'Z' BEGIN IF (s LENGTH=1) THEN RETURN s(s'low) ELSE FOR i IN s'range LOOP result:=resolution_table(result s(i)) END LOOP END IF RETURN result END resolved END STD_LOGIC_1164 109

4-21 : FUNCTION resolved (s:std_ulogic_vector) RETURN STD_ULOGIC s s ('0' '1' 'X') s1:=resolved(s) --s1 STD_ULOGIC 110

3 0 1 X s1 3 s1? resolved(s) X s1 X s=( 0 Z Z ) resolved(s) 0 s1 0 111

4 GENERIC GENERIC GENERIC GENERIC 4-22 GENERIC 112

4-22 ENTITY and2 IS GENERIC (rise fall:time) PORT (a b: IN BIT END and2 c: OUT BIT) ARCHITECTURE behav OF and2 IS BEGIN SIGNAL internal:bit internal<=a AND b c<=internal AFTER (rise) WHEN internal='1' ELSE END behav internal AFTER (fall) 113

4-22 12 4-12 GENERIC GENERIC MAP 4-22 12 VHDL 4-23 114

U0 ina & U0_C U2 inb & U1 q inc & ind U1_C 4-12 3 115

4-23 ENTITY sample IS GENERIC (rise fall:time) PORT (ina inb inc ind:in BIT q:out BIT) END sample ARCHITECTURE behav OF sample IS COMPONENT and2 GENERIC (rise fall:time) PORT (a b:in BIT c:out BIT) END COMPONENT 116

SIGNAL U0_C U1_C:BIT BEGIN U0:and2 GENERIC MAP (5 ns 5 ns) PORT MAP (ina inb U0_C) U1:and2 GENERIC MAP (8 ns 10 ns) PORT MAP (inc ind U1_C) U2:and2 GENERIC MAP (9 ns 11 ns) PORT MAP (U0_C U1_C q) END behav 117

4-23 GENERIC MAP and2 U0 U1 U2 U0 5 ns U1 8 ns U2 9 ns U0 5 ns U1 10 ns U2 11 ns GUARDED BLOCK VHDL 118

4.3.2 (RTL) 1 RTL RTL RTL VHDL RTL RTL VHDL 4-24 119

4-24 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL USE IEEE.STD_LOGIC_UNSIGEND.ALL ENTITY mux4 IS PORT (input:in STD_LOGIC_VECTOR (3 DOWNTO 0) sel:in STD_LOGIC_VECTOR (1 DOWNTO 0) y:out STD_LOGIC) END mux4 ARCHITECTURE rtl OF mux4 IS BEGIN y<=input(0) WHEN sel="00" ELSE input(1) WHEN sel="01" ELSE input(2) WHEN sel="10" ELSE input(3) END rtl 120

input(0) input(1) sel y 4-13 121

4-25 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL USE IEEE.STD_LOGIC_UNSIGEND.ALL ENTITY mux2 IS PORT (input:in STD_LOGIC_VECTOR (1 DOWNTO 0) sel:in STD_LOGIC y:out STD_LOGIC) END mux2 ARCHITECTURE rtl OF mux2 IS BEGIN y<=input(0) WHEN sel='1' ELSE input(1) END rtl 122

4-26 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL USE IEEE.STD_LOGIC_UNSIGEND.ALL ENTITY mux2 IS PORT (in0 in1 sel:in STD_LOGIC y:out STD_LOGIC) END mux2 ARCHITECTURE rtl OF mux2 IS SIGNAL tmp1 tmp2 tmp3:std_logic BEGIN tmp1<=in0 AND sel tmp2<=in1 AND (NOT sel) tmp3<=tmp1 OR tmp2 y<=tmp3 END rtl 123

4-25 4-26 VHDL 4-25 RTL CAD CAD 124

2 RTL 1) X RTL X RTL X RTL 125

4-27 RTL sel='1' y 0 sel='0' y 1 sel X X 1 ELSE 1 X 4-27 4-28 4-27 PROCESS (sel) BEGIN IF (sel='1') THEN y<='0' ELSE y<='1' END IF END PROCESS 4-28 PROCESS (sel) BEGIN IF (sel='0') THEN y<='1' ELSE y<='0' END IF END PROCESS 126

sel='x' y 0 4-28 y<= X PROCESS (sel) BEGIN IF (sel='1') THEN y<='0' ELSIF (sel='0') THEN y<='1' ELSE y<='x' END IF END PROCESS ELSE sel sel='x' y X ELSE RTL 127

( ) Z X Z 4-14 4-14 Z X EN Z 0 1 y & & 4-14 128

2) RTL RTL RTL (1) RTL 4-29 4-29 PROCESS (clk1 clk2) BEGIN IF (clk1'event AND clk1='1') THEN y<=a END IF IF (clk2 EVENT AND clk2='1') THEN z<=b END IF END PROCESS 129

(2) IF ELSE IF ELSE 4-30 4-30 PROCESS (clk) BEGIN IF (clk EVENT AND clk='1') THEN y<=a ELSE - - y<=b END IF END PROCESS 130

(3) 4-31 4-31 PROCESS (clk) VARIABLE tmp:std_logic BEGIN IF (clk'event AND clk='1') THEN tmp:=a END IF y<=tmp END IF 131

(4) 132

4.3.3 AND OR XOR AND OR XOR (AND ENTITY OR ENTITY XOR ENTITY) ENTITY 133

1 4-34 4-16 u3 d0 & aa d1 u1 u2 & ab u4 1 q sel nse1 4-16 134

4-34 ENTITY mux2 IS PORT (d0 d1 sel:in BIT END mux2 q:out BIT) ARCHITECTURE struct OF mux2 IS COMPONENT and2 PORT (a b:in BIT c:out BIT) END COMPONENT 135

COMPONENT or2 PORT (a b:in BIT c:out BIT) END COMPONENT COMPONENT inv PORT (a:in BIT c:out BIT) END COMPONENT SIGNAL aa ab nsel:bit BEGIN u1:inv PORT MAP (sel,nsel) u2:and2 PORT MAP (nsel,d1,ab) u3:and2 PORT MAP (d0,sel,aa) u4:or2 PORT MAP (aa,ab,q) END struct 136

4-34 COMPONENT ( AND OR NOT ) PORT MAP( ) ( u1 u2 u3 u4) 137

2 COMPONENT COMPONENT 4-33 3 COMPONENT 3 3 3 COMPONENT COMPONENT : COMPONENT GENERIC -- PORT -- END COMPONENT 138

COMPONENT ARCHITECTURE PACKAGE BLOCK COMPONENT END COMPONENT GENERIC PORT GENERIC PORT 139

3 COMPONENT_INSTANT COMPONENT_INSTANT 4-33 a b c 4-16 u2 nsel d1 ab 4-16 COMPONENT_INSTANT : PORT MAP ( ) : u2:and2 PORT MAP (nse1 d1 ab) PORT MAP : 140

1) PORT MAP( ) PORT (a b:in BIT c:out BIT) u2 u2:and2 PORT MAP (nsel d1 ab) 4-16 u2 nse1 a d1 b ab c 2) : u2:and2 PORT MAP (a=>nsel b=>d1 c=>ab) 141

4.4 VHDL 4.4.1 VHDL : 142

WAIT IF CASE LOOP NEXT EXIT NULL 143

1 WAIT WAIT 4 : : WAIT -- WAIT ON -- WAIT UNTIL -- WAIT FOR -- 144

2 (ASSERT) ASSERT ASSERT ASSERT REPORT SEVERITY ASSERT REPO-RT SEVERITY VHDL 4 FAILURE ERROR WARNING NOTE 145

3 4.3 <= : a<=b b a <= 146

4 := a:=2 b:=3.0 c:=d+e 147

5 IF 1) IF IF IF THEN END IF IF IF IF IF 148

4-39 IF (a='1') THEN c<=b END IF IF a b c a 1 b c b a 1 c<=b c b D 4-40 D VHDL 149

4-40 LIBRARY IEEE USE IEEE. STD_LOGIC_1164.ALL ENTITY dff IS PORT (clk d: IN STD_LOGIC q: OUT STD_LOGIC) END dff ARCHITECTURE rtl OF dff IS BEGIN PROCESS(clk) BEGIN IF(clk EVENT AND clk= 1 ) THEN q<=d END IF END PROCESS END rtl 150

2) IF IF IF THEN ELSE END IF 151

4-41 ARCHITECTURE rtl OF mux2 IS BEGIN PROCESS (a b sel) BEGIN IF (sel= 1 ) THEN c<=a ELSE c<=b END IF END PROCESS END rtl 152

3) IF IF IF IF THEN ELSIF THEN ELSIF THEN ELSE END IF 153

4-42 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY mux4 IS PORT(input: IN STD_LOGIC_VECTOR (3 DOWNTO 0) sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0) y: OUT STD_LOGIC) END mux4 ARCHITECTURE rtl OF mux4 IS BEGIN PROCESS(input sel) BEGIN IF(sel="00") THEN 154

y<=input(0) ELSIF(sel="01") THEN y<=input(1) ELSIF(sel="10") THEN y<=input(2) ELSE y<=input(3) END IF END PROCESS END rtl 155

6 CASE CASE IF CASE IF CASE CASE IS WHEN => END CASE 156

CASE 4 WHEN => WHEN... => WHEN TO => WHEN OTHERS=> CASE IS => CASE 4-43 157

4-43 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY mux4 IS PORT(a b i0 i1 i2 i3: IN STD_LOGIC END mux4 q: OUT STD_LOGIC) ARCHITECTURE mux4_behave OF mux4 IS BEGIN SIGNAL sel: INTEGER RANGE 0 TO 3 B: PROCESS(a b i0 i1 i2 i3) BEGIN IF (a='0' AND b='0') THEN 158

sel<=0 ELSIF (a='1' AND b='0') THEN sel<=1 ELSIF (a='0' AND b='1') THEN sel<= 2 ELSIF (a='1' AND b='1' THEN sel<=3 END IF CASE sel IS WHEN 0=>q<=i0 WHEN 1=>q<=i1 WHEN 2=>q<=i2 WHEN 3=>q<=i3 END CASE END PROCESS END mux4_behave 159

7 LOOP LOOP VHDL LOOP LOOP 1) FOR LOOP : : FOR IN LOOP END LOOP 160

2) WHILE LOOP : : WHILE LOOP END LOOP LOOP 161

8 NEXT LOOP NEXT NEXT WHEN NEXT WHEN NEXT NEXT WHEN LOOP 162

9 EXIT EXIT LOOP NEXT EXIT LOOP EXIT EXIT WHEN EXIT WHEN LOOP 163

4.4.2 VHDL (PROCESS) (Concurrent Signal Assignment) (Conditional Signal Assignment) (Selective Signal Assignment) (Concurrent Procedure Call) (BLOCK) 164

1 (PROCESS) PROCESS : WAIT 165

2 (Concurrent Signal Assignment) 4.2 ( ) ( ) : ARCHITECTURE behav OF a_var IS BEGIN output<=a(i) END behav ARCHITECTURE behav OF a_var IS BEGIN PROCESS(a i) BEGIN output<=a(i) END PROCESS END behav 166

3 (Conditional Signal Assignment) <= 1 WHEN 1 ELSE 2 WHEN 2 ELSE 3 WHEN 3 ELSE ELSE n 167

4-51 4-51 ENTITY mux4 IS PORT(i0 i1 i2 i3 a b: IN STD_LOGIC q: OUT STD_LOGIC) END mux4 ARCHITECTURE rtl OF mux4 IS SIGNAL sel: STD_LOGIC_VECTOR(1 DOWNTO 0) BEGIN sel<=b & a q<=i0 WHEN sel="00" ELSE i1 WHEN sel="01" ELSE i2 WHEN sel="10" ELSE i3 WHEN sel="11" ELSE 'X' END rtl 168

4 (Selective Signal Assignment) CASE : WITH SELECT <= 1 WHEN 1 2 WHEN 2 n WHEN n 169

4-52 LIBRARY IEEE USE IEEE.STD_LDGIC_1164.ALL ENTITY mux IS PORT(i0 i1 i2 i3 a b: IN STD_LOGIC q: OUT STD_LOGIC) END mux ARCHITECTURE behav OF mux IS SIGNAL sel: INTEGER BEGIN WITH sel SELECT q<=i0 WHEN 0 i1 WHEN 1 i2 WHEN 2 i3 WHEN 3 'X' WHEN OTHERS sel<=0 WHEN a='0' AND b='0' ELSE 1 WHEN a='1' AND b='0' ELSE 2 WHEN a='0' AND b='1' ELSE 3 WHEN a='1' AND b='1' ELSE 4 END behav 170

5 (Concurrent Procedure Call) 4.2.2 IN OUT INOUT 171

6 (BLOCK) 4.2.2 BLOCK BLOCK BLOCK : BLOCK { } BEGIN { } END BLOCK 172

7 GENERATE GENERATE FOR-GENERATE IF-GENERATE : : FOR IN GENERATE < > END GENERATE : IF GENERATE < > END GENERATE 173

FOR-GENERATE FOR-LOOP EXIT NEXT IF-GENERATE IF ELSE ( C ) D 4-17 4 D 4-56 GENERATE 4 174

a DFF X(0) z(0) z(1) DFF X(1) z(2) DFF X(2) z(3) DFF X(3) z(4) d q d q d q d q b clk clk clk clk lk 4-17 4 175

4-56 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY shift IS PORT(a clk: IN STD_LOGIC b: OUT STD_LOGIC) END shift ARCHITECTURE gen_shift OF shift IS COMPONENT dff PORT(d clk: IN STD_LOGIC q: OUT STD_LOGIC) END COMPONENT SIGNAL z: STD_LOGIC_VECTOR(0 TO 4) BEGIN z(0)<=a g1: FOR i IN 0 TO 3 GENERATE dffx: dff PORT MAP(z(i) clk z(i+1)) END GENERATE b<=z(4) END gen_shift 176

GENERATE 4 ( 4-57) 4-57 ARCHITECTURE long_way_shift OF shift IS COMPONENT dff PORT(d clk: IN STD_LOGIC q: OUT STD_LOGIC) END COMPONENT SIGNAL z: STD_LOGIC_VECTOR(0 TO 4) BEGIN z(0)<=a dff1: dff PORT MAP(z(0) clk z(1)) dff2: dff PORT MAP(z(1) clk z(2)) dff3: dff PORT MAP(z(2) clk z(3)) dff4: dff PORT MAP(z(3) clk z(4)) b<=z(4) END long_way_shift 177

4.5 4.5.1 1 1) 8421BCD 178

(1) 8421BCD 8421BCD 4-8 4-8 8421BCD s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 a b c d s 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 0 0 1 0 1 1 1 1 1 1 1 0 1 1 1 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 0 0 1 1 1 1 1 0 1 1 1 1 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 0 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 179

4-60 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY enco_bcd IS PORT(s0 s1 s2 s3 s4 s5 s6 s7 s8 s9: IN STD_LOGIC; a b c d s: OUT STD_LOGIC) END enco_bcd ARCHITECTURE rtl OF debcd IS SIGNAL tmp_in: STD_LOGIC_VECTOR(9 DOWNTO 0) SIGNAL tmp_out: STD_LOGIC_VECTOR(4 DOWNTO 0) BEGIN Tmp_in<=s9&s8&s7&s6&s5&s4&s3&s2&s1&s0 PROCESS(tmp_in) BEGIN 180

CASE tmp_in IS WHEN "1111111111"=>tmp_out<="00000" WHEN "1111111110"=>tmp_out<="00001" WHEN "1111111101"=>tmp_out<="00011" WHEN "1111111011"=>tmp_out<="00101" WHEN "1111110111"=>tmp_out<="00111" WHEN "1111101111"=>tmp_out<="01001" WHEN "1111011111"=>tmp_out<="01011" WHEN "1110111111"=>tmp_out<="01101" WHEN "1101111111"=>tmp_out<="01111" WHEN "1011111111"=>tmp_out<="10001" WHEN "0111111111"=>tmp_out<="10011" WHEN OTHERS=>tmp_out<="00000" 181

END CASE s<=tmp_out(0) d<=tmp_out(1) c<=tmp_out(2) b<=tmp_out(3) a<=tmp_out(4) END PROCESS END rtl CASE WHEN OTHERS 182

(2) 74LS148 8 3 3 74LS148 4-9 8 in0 in7 e1 3 a2 a0 cs e0 183

4-9 74LS148 e1 in0 in1 in2 in3 in4 in5 in6 in7 a2 a1 a0 cs e0 1 Ф Ф Ф Ф Ф Ф Ф Ф 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 Ф Ф Ф Ф Ф Ф Ф 0 0 0 0 0 1 0 Ф Ф Ф Ф Ф Ф 0 1 0 0 1 0 1 0 Ф Ф Ф Ф Ф 0 1 1 0 1 0 0 1 0 Ф Ф Ф Ф 0 1 1 1 0 1 1 0 1 0 Ф Ф Ф 0 1 1 1 1 1 0 0 0 1 0 Ф Ф 0 1 1 1 1 1 1 0 1 0 1 0 Ф 0 1 1 1 1 1 1 1 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 184

CASE IF CASE WHEN IF IF 74LS148 4-61 4-61 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY p_encoder PORT (e1 in0 in1 in2 in3 in4 in5 in6 in7:in STD_LOGIC e0 cs a0 a1 a2: OUT STD_LOGIC) END p_encoder ARCHITECTURE rtl of p_encoder IS SIGNAL tmp_in: STD_LOGIC_VECTOR(7 DOWNTO 0) SIGNAL tmp_out: STD_LOGIC_VECTOR(4 DOWNTO 0) 185

BEGIN Tmp_in<=in7&in6&in5&in4&in3&in2&in1&in0 Tmp_out<=a2&a1&a0&cs&e0 PROCESS(e1 tmp_in) BEGIN IF(e1='0') THEN IF(tmp_in="11111111") THEN Tmp_out<="11110" ELSIF(tmp_in(7)='0') THEN Tmp_out<="00001" ELSIF(tmp_in(6)= '0') THEN Tmp_out<="00101" ELSIF(tmp_in(5)= '0') THEN Tmp_out<="01001" ELSIF(tmp_in(4)= '0') THEN Tmp_out<="01101" ELSIF(tmp_in(3)= '0') THEN 186

Tmp_out<="10001" ELSIF(tmp_in(2)= '0') THEN Tmp_out<="10101" ELSIF(tmp_in(1)= '0') THEN Tmp_out<="11001" ELSIF(tmp_in(0)= '0') THEN Tmp_out<="11101" END IF ELSE Tmp_out<="11111" END IF e0<=tmp_out(0) cs<=tmp_out(1) a0<=tmp_out(2) a1<=tmp_out(3) a2<=tmp_out(4) END PROCESS END rtl 187

4-61 tmp_in tmp_out 8 5 IF IF e1 in(7)= '0' 0 in(7) in(6) in(0) 188

2) 7 7 VHDL (1) 4-10 e a1 a0 q3 q0 4 VHDL 4-62 189

4-10 2-4 e a1 a0 q0 q1 q2 q3 1 1 1 1 1 0 0 0 1 1 1 0 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 0 190

4-62 LIBRARY IEEE USE IEEE.STDP_LOGIC_1164.ALL ENTITY enco_2_4 IS PORT(e a0 a1: IN STD_LOGIC q0 q1 q2 q3: OUT STD_LOGIC) END enco_2_4 IS ARCHITECTURE rtl OF enco_2_4 IS SIGNAL tmp_in: STD_LOGIC_VECTOR(1 DOWNTO 0) SIGNAL tmp_out: STD_LOGIC_VECTOR(3 DOWNTO 0) BEGIN Tmp_in<=a1&a0 PROCESS(tmp_in e) BEGIN IF(e='0') THEN 191

CASE tmp_in IS WHEN"00"=>tmp_out<="1110" WHEN"01"=>tmp_out<="1101" WHEN"10"=>tmp_out<="1011" WHEN"11"=>tmp_out<="0111" WHEN OUTHERS=>tmp_out<="1111" END CASE ELSE Tmp_out<="1111" END IF q0<=tmp_out(0) q1<=tmp_out(1) q2<=tmp_out(2) q3<=tmp_out(3) END PROCESS END rtl 192

(2) 7 7 4-11 4-11 7 bi/rbo lt rbi d c b A a b c d e f g 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 1 1 Ф 0 0 0 1 1 1 0 0 1 1 1 1 2 1 Ф 0 0 1 0 1 0 0 1 0 0 1 0 3 1 Ф 0 0 1 1 1 0 0 0 0 1 1 0 4 1 Ф 0 1 0 0 1 1 0 0 1 1 0 0 5 1 Ф 0 1 0 1 1 0 1 0 0 1 0 0 6 1 Ф 0 1 1 0 1 1 1 0 0 0 0 0 7 1 Ф 0 1 1 1 1 0 0 0 1 1 1 1 8 1 Ф 1 0 0 0 1 0 0 0 0 0 0 0 9 1 Ф 1 0 0 1 1 0 0 0 1 1 0 0 10 1 Ф 1 0 1 0 1 1 1 1 0 0 1 0 11 1 Ф 1 0 1 1 1 1 1 0 0 1 1 0 12 1 Ф 1 1 0 0 1 1 0 1 1 1 0 0 13 1 Ф 1 1 0 1 1 0 1 1 0 1 0 0 14 1 Ф 1 1 1 0 1 1 1 1 0 0 0 0 15 1 Ф 1 1 1 1 1 1 1 1 1 1 1 1 193

VHDL 4-63 4-63 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY deseg7 IS PORT(lt rbi ain bin cin din: IN STD_LOGIC END deseg7 bi_rbo INOUT STD_LOGIC a b c d e f g: OUT STD_LOGIC) ARCHITECTURE rtl OF deseg7 IS SIGNAL tmp_in: STD_LOGIC_VECTOR(3 DOWNTO 0) SIGNAL tmp_out: STD_LOGIC_VECTOR(3 DOWNTO 0) SIGNAL bi_in: rbi_in rbo bi: STD_LOGIC 194

BEGIN Tmp_in<=din&cin&bin&ain bi<=bi_rbo rbi_in<=rbi PROCESS(bi) BEGIN IF(rbi=0) THEN Bi_in<='1' ELSE Bi_in<=bi END IF END PROCESS PROCESS(lt rbi_in bi_in tmp_in) BEGIN IF(bi_in='0') THEN 195

Tmp_out<="1111111" ELSIF(lt='1' AND rbi_in='1' AND tmp_in="0000") THEN Tmp_out<="10000000" ELSIF(lt='1' AND rbi_in='1' AND tmp_in/="0000") THEN CASE tmp_in IS WHEN"0001"=>tmp_out<="1111001" WHEN"0010"=>tmp_out<="0100100" WHEN"0011"=>tmp_out<="0110000" WHEN"0100"=>tmp_out<="0011001" WHEN"0101"=>tmp_out<="0010010" WHEN"0110"=>tmp_out<="0000011" WHEN"0111"=>tmp_out<="1111000" WHEN"1000"=>tmp_out<="0000000" WHEN"1001"=>tmp_out<="0011000" 196

WHEN"1010"=>tmp_out<="0100111" WHEN"1110"=>tmp_out<="0000111" WHEN"1111"=>tmp_out<="1111111" END CASE ELSIF(lt='0') THEN rbo<='1' tmp_out<="0000000" ELSE rbo<='1' tmp_out<="1111111" END IF a<=tmp_out(0) b<=tmp_out(1) c<=tmp_out(2) 197

d<=tmp_out(3) e<=tmp_out(4) f<=tmp_out(5) g<=tmp_out(6) END PROCESS PROCESS(rbi) VARIABLE rbi_v: STD_LOGIC BEGIN rbi_v:=rbi IF(rbi_v='0') THEN bi_rbo<='0' ELSE bi_rbo<='z' END IF END PROCESS END rtl 198

2 VHDL 4-12 4-12 e a1 a0 d f 1 Ф Ф Ф 0 0 0 0 D 0 D 3 D 0 0 0 1 D 0 D 3 D 1 0 1 0 D 0 D 3 D 2 0 1 1 D 0 D 3 D 3 199

e a1 a0 d3 d0 4 f VHDL 4-64 4-64 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY mux4 IS PORT(a0 a1 d0 d1 d2 d3 e: IN STD_LOGIC f: OUT STD_LOGIC) END mux4 ARCHITECTURE rtl OF mux4 IS SIGNAL a: STD_LOGIC_VECTOR(1 DOWNTO 0) BEGIN a<=a1&a0 PROCESS(e a) BEGIN 200

IF(e='0') THEN CASE a IS WHEN"00"=>f<=d0 WHEN"01"=>f<=d1 WHEN"10"=>f<=d2 WHEN"11"=>f<=d3 WHEN OTHERS=>f<='0' END CASE ELSE f<='0' END IF END PROCESS END rtl 201

3 VHDL 4-65 a b cin co s 4-65 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY adder IS PORT(a b cin: IN STD_LOGIC co s: OUT STD_LOGIC) END adder ARCHITECTURE rtl OF adder IS BEGIN PROCESS(a b cin) 202

VARIABLE cin_v ab1 ab2 abc: STD_LOGIC BEGIN Cin_v:=cin ab1:=a XOR b ab2:=a AND b abc:=cin_v AND ab1 s<=cin_v XOR ab1 co<=abc OR ab2 END PROCESS END rtl 203

4 4 4 VHDL 4-66 4-66 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY adder_4 IS PORT(ci a0 b0 a1 b1 a2 b2 a3 b3 IN STD_LOGIC END adder_4 s0 s1 s2 s3 c3_o: OUT STD_LOGIC) ARCHITECTURE rtl OF adder_4 IS COMPONENT adder PORT(a b cin: IN STD_LOGIC co s: OUT STD_LOGIC) 204

END COMPONENT SIGNAL c0_s c1_s c2_s: STD_LOGIC BEGIN u0: adder PORT MAP(a0 b0 cin co_s s0) u1: adder PORT MAP(a1 b1 c0_s c1_s s1) u2: adder PORT MAP(a2 b2 c1_s c2_s s2) u3: adder PORT MAP(a3 b3 c2_s c3_o s3) END rtl 205

VHDL 4-67 4 4-67 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL USE IEEE.STD_LOGIC_ARITH.ALL USE IEEE.STD_LOGIC_UNSIGNED.ALL ENTITY adder_4_1 IS PORT(a: IN STD_LOGIC_VECTOR(3 DOWNTO 0) b: IN STD_LOGIC_VECTOR(3 DOWNTO 0) s: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) 206

c3_o: OUT STD_LOGIC ci: IN STD_LOGIC) END adder_4_1 ARCHITECTURE rtl OF adder_4_1 IS BEGIN PROCESS(a b ci) VARIABLE a_v b_v: INTEGER RANGE 0 TO 15 VARIABLE s_v: INTEGER RANGE 0 TO 31 VARIABLE ci_v: INTEGER RANGE 0 TO 1 BEGIN IF(ci='1') THEN Ci_vi:=1 ELSE Ci_v:=0 207

END IF a_v:=conv_integer(a) b_v:=conv_integer(b) s_v:=a_v+b_v+ci_v IF(s_v>=16) THEN S_v:=s_v-16 c3_o<='1' ELSE c3_o<='0' END IF s<=conv_std_logic_vector(s_v 4) END PROCESS END rtl 208

4 n q_odd=d0 d1 dn-1 q_even = q _ odd VHDL 9 4-68 4-69 209

4-68 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY parity IS PORT(a: IN STD_LOGIC_VECTOR(8 DOWNTO 0) END parity q_odd q_even: OUT STD_LOGIC) ARCHITECTURE rtl1 OF parity IS BEGIN PROCESS(a) VARIABLE tmp: STD_LOGIC 210

BEGIN tmp :='0' FOR i IN 0 TO 8 LOOP tmp:=tmp XOR a(i) END LOOP q_odd<=tmp q_even<=not tmp END PROCESS END rtl1 211

q_eve 1 1 1 1 1 1 1 1 q_odd a(0) a(1) a(2) a(3) a(4) a(5) a(6) a(7) 4-18 4-69 212

4-18 q_odd 8 4-69 4-69 ARCHITECTURE rtl2 OF parity IS BEGIN PROCESS(a) VARIABLE tmp1: STD_LOGIC_VECTOR (3 DOWNTO 0) VARIABLE tmp2: STD_LOGIC_VECTOR (1 DOWNTO 0) VARIABLE tmp3 tmp4: STD_LOGIC BEGIN 213

tmp1(0):=a(0) XOR a(1) tmp1(1):=a(2) XOR a(3) tmp1(2):=a(4) XOR a(5) tmp1(3):=a(6) XOR a(7) tmp4:=a(8) tmp2(0):=tmp1(0) XOR tmp1(1) tmp2(1):=tmp1(2) XOR tmp1(3) tmp3:=tmp2(0) XOR tmp2(1) q_odd<=tmp3 XOR tmp4 q_even<=not q_odd END PROCESS END rtl2 214

5 1) 4-19 din dout en en= 1 dout=din en= 0 dout= z ( ) 4-13 215

din en dout 4-19 216

4-13 Din en dout X 0 z 0 1 0 1 1 1 217

VHDL 4-70 4-70 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY tri_gate IS PORT(din en: IN STD_LOGIC END tri_gate dout: OUT STD_LOGIC) ARCHITECTURE rtl OF tri_gate IS BEGIN PROCESS(din en) 218

BEGIN IF(en='1') THEN dout<=din ELSE dout<='z' END IF END PROCESS END rtl 219

2) 8 4-20 en 220

din (7 DOWNTO 0) en 8 dout (7 DOWNTO 0) 4-20 8 221

VHDL 8 4-71 4-71 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY tri_buf8 IS PORT(din: IN STD_LOGIC_VECTOR (7 DOWNTO 0) dout: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) en: IN STD_LOGIC) END tri_buf8 ARCHITECTURE rtl OF tri_buf8 IS BEGIN 222

PROCESS(din en) BEGIN IF(en='1') THEN dout<=din ELSE dout<="zzzzzzzz" END IF END PROCESS END rtl 223

3) 4-21 a b dr en en= 1 a b en= 0 dr= 0 a<=b dr= 1 b<=a 4-14 VHDL 4-72 224

a (7DOWNTO 0) dr 8 b(7 DOWNTO 0 en 4-21 225

4-14 en dr 0 0 a<=b 0 1 b<=a 1 X 226

4-72 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY tri_bigate IS PORT(a b: INTOUT STD_LOGIC_VECTOR(7 OWNTO 0) dr en: IN STD_LOGIC) END tri_bigate ARCHITECTURE rtl OF tri_bigate IS 0) BEGIN SIGNAL aout bout: STD_LOGIC_VECTOR(7 DOWNTO PROCESS(a dr en) BEGIN IF((en='0') AND (dr='1') THEN 227

bout<=a ELSE bout<="zzzzzzzz" END IF b<=bout END PROCESS PROCESS(b dr en) BEGIN IF(en='0') AND (dr='0')) THEN aout<=b ELSE aout<="zzzzzzzz" END IF a<=aout END PROCESS END rtl 228

4.5.2 1 229

1) 0 1 1 0 (1) 4-22 4-22 0 clk EVENT clk= 1 230

clk EVENT clk '1' clk clk '0' 4-22 231

(2) 4-23 4-22 1 clk'event clk='0' IF (clk'event AND clk='0') 232

clk '1' clk EVENT clk clk '0' 4-23 233

2) ( ) (1) VHDL IF IF IF 4-73 234

4-73 PROCESS(clock_signal) BEGIN IF(clock_edge_condition) THEN IF(reset_condition) THEN ELSE Signal_out<=reset_value Signal_out<=signal_in END IF END IF END PROCESS 235

(2) IF 4-74 4-74 PROCESS(clock_signal reset_signal) BEGIN IF(reset_condition) THEN Signal_out<=reset_value ELSIF(clock_edge_condition) THEN Signal_out<=signal_in END IF END PROCESS 236

2 1) (1) D 4-24 D d clk q D 4-15 D d q VHDL D 4-75 4-76 237

d q clk 4-24 D 238

4-15 D d clk q n+1 X 0 X 1 0 0 1 1 239

4-75 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY dff1 IS PORT (clk d:in STD_LOGIC q:out STD_LOGIC) END dff1 ARCHITECTURE rtl OF dff1 IS BEGIN PROCESS (clk) BEGIN IF (clk'event AND clk='1') THEN q<=d END IF END PROCESS END rtl 240

4-76 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY dff1 IS PORT (clk d:in STD_LOGIC q:out STD_LOGIC) END dff1 ARCHITECTURE rtl OF dff1 IS BEGIN PROCESS BEGIN WAIT UNTIL clk 'EVENT AND clk='1' q<=d END PROCESS END rtl 241

4-75 4-76 : IF (clk 'EVENT AND clk='0') 242

(2) D 4-25 D clr clr= 0 q 0 clr VHDL D 4-77 4-77 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY dff2 IS PORT (clk d clr:in STD_LOGIC q:out STD_LOGIC) 243

END dff2 ARCHITECTURE rtl OF dff2 IS BEGIN PROCESS (clk clr) BEGIN IF (clr='0') THEN q<='0' ELSIF (clk 'EVENT AND clk='1') THEN q<=d END IF END PROCESS END rtl 244

clr q d clk 4-25 D 245

(3) / D / 4-26 d clk q clr pset clr= 0 q= 0 pset= 0 q= 1 246

clr q d clk pset 4-26 / D 247

VHDL / 4-78 4-78 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY dff3 IS PORT (clk d clr pset:in STD_LOGIC q:out STD_LOGIC) END dff3 ARCHITECTURE rtl OF dff3 IS BEGIN PROCESS (clk pset clr) BEGIN IF (pset='0') THEN 248

q<='1' ELSIF (clr='0') THEN q<='0' ELSIF (clk'event AND clk='1') THEN q<=d END IF END PROCESS END rtl 4-78 pset='0' clr clk q 1 249

(4) D 4-27 clr (clr='1') clr= 1 clk q 0 d clr='1' d clk q 0 250

clr 1 d q d 1 clk clk 4-27 D 251

VHDL D 4-79 4-79 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY dff4 IS PORT (clk clr d:in STD_LOGIC END dff4 ARCHITECTURE rtl OF dff4 IS BEGIN PROCESS (clk) q:out STD_LOGIC) 252

BEGIN IF (clk 'EVENT AND clk='0') THEN IF (clr='0') THEN q<='0' ELSE q<=d END IF END IF END PROCESS END rtl 253

2) JK / JK 4-28 JK pset clr j k clk q qb JK 4-16 q0 0 1 1 0 254

clr j clk k pest q qb 4-28 JK 255

4-16 JK pset clr clk j K q qb 0 1 X X X 1 0 1 0 X X X 0 1 0 0 X X X X X 1 1 0 1 0 1 1 1 1 1 1 1 0 0 q0 NOT q0 1 1 1 0 1 0 1 1 0 X X q0 NOT q0 256

VHDL JK 4-80 4-80 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY jkdff IS PORT (pset clr clk j k:in STD_LOGIC q qb:out STD_LOGIC) END jkdff ARCHITECTURE rtl OF jkdff IS SIGNAL q_s qb_s: STD_LOGIC BEGIN PROCESS (pset clr clk j k) BEGIN IF (pset='0') THEN q_s<='1' qb_s<='0' 257

ELSIF (clr='0') THEN q_s<='0' qb_s<='1' ELSIF (clk' EVENT AND clk='0') THEN IF (j='0'and (k='1') THEN q_s<='0' qb_s<='1' ELSIF (j='1') AND (k='0') THEN q_s<='1' qb_s<='0' ELSIF (j='1') AND (k='1') THEN q_s<=not q_s qb_s<=not qb_s END IF END IF q<=q_s qb<=qb_s END PROCESS END rtl 258

4-80 pset clr pset='0' clr='0' q 1 qb 0 4-16 4-81 4-81 ARCHITECTURE rtl OF jkdff IS BEGIN SIGNAL q_s qb_s:std_logic PROCESS (pset clr clk j k) BEGIN q_s<='1' IF (pset='0') AND (clr='1') THEN qb_s<='0' 259

ELSIF (pset='1') AND (clr='0') THEN q_s<='0' qb_s<='1' ELSIF (clk'event AND clk='0') THEN IF (j='0') AND (k='1') THEN q_s<='0' qb_s<='1' ELSIF (j='1') AND (k='0') THEN q_s<='1' qb_s<='0' ELSIF (j='1') AND (k='1') THEN q_s<=not q_s qb_s<=not qb_s END IF END IF q<=q_s qb<=qb_s END PROCESS END rtl 260

3 4-29 a clk b 8 8 8 D GENERATE D 8 VHDL 4-82 261

a z(0) d q clk z(1) d q clk z(2) d q clk z(3) d q clk z(4) d q clk z(5) d q clk z(6) d q clk z(7) d q clk z(8) lk 4-29 262

4-82 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY shift8 IS PORT (a clk:in STD_LOGIC END shift8 b:out STD_LOGIC) ARCHITECTURE sample OF shift8 IS COMPONENT dff PORT (d clk:in STD_LOGIC q:out STD_LOGIC) END COMPONENT SIGNAL z:std_logic_vector (0 TO 8) 263

BEGIN z(0)<=a g1:for i IN 0 TO 7 GENERATE dffx:dff PORT MAP (z(i) clk z(i+1)) END GENERATE b<=z(8) END sample dff GENERATE 8 D 264

4 1) ( ) (1) 3 clr en ( ) clk ( ) qa qb qc 3 VHDL 4-83 265

4-83 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL USE IEEE.STD_LOGIC_ARITH.ALL ENTITY cnt6 PORT(clr en clk: IN STD_LOGIC qa qb qc: OUT STD_LOGIC) END cnt6 ARCHITECTURE rtl OF ont6 IS SIGNAL q: STD_LOGIC_VECTOR(2 DOWNTO 0) BEGIN PROCESS(clk) VARIABLE q6: INTEGER BEGIN IF(clk'EVENT AND clk='1') THEN 266

IF(clr='0') THEN q6:=0 ELSIF(en='1') THEN IF(q6=5) THEN q6:=0 ELSE q6:=q6+1 END IF END IF END IF q<=conv_std_logic_vector(q6 3) qa<=q(0) qb<=q(1) qc<=q(2) END PROCESS END rtl 267

CONV_STD_LOGIC_VECTOR(q6 3) q6 2 3 q6 3 268

(2) enab up_down reset cnt_out cntclk 9 DOWNTO 0 4-30 10 269

4-84 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL USE IEEE.STD_LOGIC_ARITH.ALL ENTITY up_down_cnt10 IS PORT(enab up_down reset cntclk: IN STD_LOGIC END up_down_cnt10 Cnt_out: OUT STD_LOGIC_VECTOR(9 DOWNTO 0)) ARCHITECTURE rtl OF up_down_cnt10 IS BEGIN PROCESS(cntclk) BEGIN VARIABLE cnt: INTEGER RANGE -512 TO 511 VARIABLE dir: INTEGER RANGE -1 TO 1 270

IF(up_down='1') THEN dir:=1 ELSE dir:= -1 END IF IF(cntclk'EVENT AND cntclk='1') THEN IF(reset='0') THEN cnt:=0 ELSIF(enab='1') THEN cnt:=cnt+dir END IF END IF Cnt_out<=CONV_STD_LOGIC_VECTOR(cnt 10) END PROCESS END rtl 271

4-84 enab up_down cntclk reset cnt_out 10 272

2) ( ) 4-31 4 D 4 16 00002 10112 12 11002 1111 2 4-85 VHDL 273

reset1 reset2 reset & & reset_out d res q0 count(0) d res q1 count(1) d res q2 count(2) d res q3 count(3) lk clk q0b clk q1b clk q2b clk q3b count_clk unt_clk(0) count_clk(1) q0 count_clk(2) count_clk(3) q1 q2 q3 4-31 274

4-85 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY cont12f IS PORT(reset clk: IN STD_LOGIC END cont12f Count_out: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)) ARCHITECTURE rtl OF cont12f IS COMPONENT dff PORT(clk reset d: IN STD_LOGIC END COMPONENT q qb: OUT STD_LOGIC) SIGNAL count: STD_LOGIC_VECTOR(3 DOWNTO 0) SIGNAL count_clk: STD_LOGIC_VECTOR(4 DOWNTO 0) 275

SIGNAL reset1 reset2 reset_out: STD_LOGIC BEGIN reset1<=reset count_clk(0)<=clk gen1: FOR i IN 0 TO 3 GENERATE u0: dff PORT MAP(clk=>count_clk(i) reset=>reset_out d=>count_clk(i+1) q=>count(i) qb=>count_clk(i+1)) END GENERATE reset2<=not (count(2) AND count(3)) reset_out<=reset1 AND reset2 END rtl 276

3) 00011101 8 8 3 8 3 4-32 8 VHDL 4-86 277

000 001 011 111 100 010 101 110 4-32 8 278

4-86 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY q8 IS PORT(clk reset: IN STD_LOGIC q8_out: OUT STD_LOGIC) END q8 ARCHITECTURE rtl OF q8 IS SIGNAL q_s: STD_LOGIC_VECTOR(2 DOWNTO 0) BEGIN q8_out<=q_s(2) PROCESS(clk) BEGIN IF(clk'EVENT AND clk='1') THEN 279

IF(reset='1') THEN q_s<="000" ELSE CASE q_s IS WHEN"000" =>q_s<="001" WHEN"001" =>q_s<="011" WHEN"011" =>q_s<="111" WHEN"111" =>q_s<="110" WHEN"110" =>q_s<="101" WHEN"101" =>q_s<="010" WHEN"010" =>q_s<="100" WHEN"100" =>q_s<="000" WHEN OTHERS=>q_s<="000" END CASE END IF END IF END PROCESS END rtl 280

4-86 8 clk reset 8 281

4.1 4.2 4.3 VHDL 4.4 VHDL VHDL 4.5 282

4.6 4.7 VHDL 3 4.8 4.9 VHDL 283

4.10 SIGNAL atmp:std_logic_vector(7 DOWNTO0); SIGNAL btmp:std_logic_vector(0 TO 7); SIGNAL cint:integer; SIGNAL dtmp:std_logic_vector(15 DOWNTO 0); Atmp<=cint; Atmp<=btmp; Btmp<=dtmp; 284

4.11 4.12 count_int (STD_LOGIC_VECTOR) count_out 4.13 BIT STD_LOGIC 4.14 VHDL 3 A<=NOT b AND c OR d; A<=(NOT b AND c) OR d; A<=NOT b AND (c OR d); 285

4.15 SIGNAL a STD_LOGIC SIGNAL eb:std_logic SIGNAL b:std_logic_vector(3 DOWNTO 0) SIGNAL d STD_LOGIC_VECTOR(7 DOWNTO 0) b<=a&a&eb&eb; d<=b&eb&eb&eb&eb; 4.16 (ATTRIBUTE) VHDL 4.17 VHDL 286

4.18 VHDL 4.19 BLOCK 4.20 BLOCK BLOCK 4.21 0 1 1 0 4.22 287

4.23 4.24 PROCESS(a,b) SINGAL c:std_logic; BEGIN C<=a AND b; END PROCESS; 4.25 288

4.26 4.27 VHDL 4.28 4.29 VHDL 4.30 4.31 VHDL 4.32 5 ns 289

4.33 resolved(s) 3 1 Z 0 4.34 RTL RTL 4.35 RTL 4.36 4.37 D 4-1 D 290

reset a b clk & reset d q clk 4-1 D 291

4.38 WAIT 4.39 WAIT FOR 20 ns 4.40 IF 4.41 CASE 4.42 IF CASE 4.43 CASE WHEN OTHERS WHEN 292

4.44 FOR LOOP FOR LOOP ( 8 ) 4.45 4.46 4.47 GENERATE ( ) 293