混訊設計流程_04.PDF

CIC Referenced Flow for Mixed-signal IC Design Version 1.0

(Date) (Description) (Version) V. 1.0 2010/11/ Abstract CIC IC (Mixed-signal Design Flow) IC (Front End) (Back End) Function Timing Power DRC IC 5 1. (Cell-based) 2. (Full-custom) 3. / (Co-simulation) 4. / Layout 5. CIC CIC Cell Library 1

..1 Abstract.1..2 1. Overview....4 2. Design Flow for Digital Part (Cell-based)...... 6 2-1 RTL Verification......8 2-1-1 RTL Coding....8 2-1-2 RTL Simulation......8 2-1-3 Co-simulation.....9 2-2 Gate-level Pre-layout Verification...9 2-2-1 Logic Synthesis.....9 2-2-2 Gate-level Pre-layout Simulation.10 2-2-3 Co-simulation...10 2-3 Gate-level Post-layout Verification.11 2-3-1 APR..11 2-3-2 Gate-level Post-layout Simulation 11 2-3-3 Co-simulation...11 2-3-4 DRC/Block Box LVS.... 12 3. Design Flow for Analog Part (Full-custom)..13 3-1 Pre-layout Verification.14 3-1-1 Netlist/Schematic Editing.14 3-1-2 Pre-layout Simulation... 14 3-1-3 Netlist/Schematic Optimization....16 3-1-4 Co-simulation...16 3-2 Post-layout Verification...16 3-2-1 Layout Editing. 16 3-2-2 DRC/LVS.....17 3-2-3 LPE/Post-layout Simulation.... 17 3-2-4 Co-simulation...... 18 3-3 LEF Generation......18 4. Digital/Analog Co-sim ulatio n...19 4-1 AMS Environment..21 2

4-2 Ultrasim/UltrasimVerilog Environment.. 22 4-3 Nanosim+VCS Environment...23 5. Digital/Analog Layout Integration and Verification..24 5-1 Full-Chip Gate-level Post-layout Verification.....25 5-1-1 Layout Integration...25 5-1-2 DRC/Block Box LVS.. 26 5-2 PVS Transistor-level Post-layout Verification. 26 5-2-1 PVS DRC/LPE/Nanosim Simulation..27 6. Tape Out 27 7. Measurement.27...28 3

1 Overview CIC IC (Mixed-signal Design Flow) IC (Front End) (Back End) Function Timing Power DRC CIC Mixed-signal Design Flow IC 5 1. (Cell-based) 2. (Full-custom) 3. / (Co-simulation) 4. / Layout 5. (Front End) (System Analysis) Digital Part Analog Part HDL / Netlist (Cell-based) (Co-simulation) (Full-custom) (Back End) APR Layout / Gate-level DHL / Layout Integrated Layout (Tape Out) Full-custom Layout / LEF (Measurement) CIC Mixed Signal Design Flow Overview 4

CIC CIC Cell Library 5

2 Design Flow for Digital Part (Cell-based) CIC CIC Cell Library [1][2] IC Cell-based Design Flow[3] [4] IC CIC Cell Library Cell-based Design Flow IC RTL Coding RTL HDL Code (From Analog Part) Verified Netlist/Schematic RTL Simulation Function Correct Verified RTL HDL Code Co-simulation Co-simVerified RTL HDL Code RTL Verification Logic Synthesis Front End Gate-level Code & Delay Information Gate-level Pre-layout Simulation Function/Timing/Power Meet Spec. Gate-level Pre-layout Verification Verified Gate-level Code & Delay Information Co-simulation (From Analog Part) Verified Netlist/Schematic Verified Netlist with parasitic Information Co-sim Verified Gate-level Code & Delay Information LEF File Released Pre-layout Gate-level Code & Delay Information Back End APR Layout DRC Verification DRC-clean APR Layout APR Gate-level Post-layout Verification Gate-level Post-layout Code & Delay Information Gate-level Post -layout Simulation Function/Timing/Power Meet Spec. (From Analog Part) Verified Netlist/Schematic Verified Netlist with parasitic Information Block Box LVS Verification Released APR Layout Verified Gate-level Post -layout Code & Delay Information Released Gate-level Post-layout Code & Delay Information Co-simulation Design Flow for Digital Part in Mixed-Signal IC Design (Cell-based) 6

Design Flow for Digital Part 3 1. RTL Verification 2. Gate-level Pre-layout Verification 3. Gate-level Post-layout Verification Cell-based IC [3] 1. IC Co-simulation Gate-level Pre-layout Verification Gate-level Post-layout Verification IC 2. Cell-based IC Gate-level Post-layout Verification IC IC Gate-level Post-layout Verification IC Layout Full-custom RTL Coding Layout IC D A ( ) Gate-level Pre-layout Verification Pre-layout Verification Co-simulation Gate-level Post-layout Verification IC IC A D ( ) Gate-level Post-layout Verification Layout LEF 5-1-1 Layout Integration by APR Tool Layout APR Layout 7

IC A D D A IC Cell-based Design Flow for Digital Part 2-1 RTL Verification RTL Verification RTL Coding RTL Simulation Co-simulation Function 2-1-1 RTL Coding RTL Coding (Hardware Description Language HDL Verilog VHDL) (Register Transfer Level RTL) Cycle-accurate (Combinational Logic) (Sequential Logic) (Module) (Hierarchical) Verilog VHDL [5] [6] 2-1-2 RTL Simulation HDL RTL Code HDL Verilog VHDL Simulator (Input Test Pattern) Simulator Debug Tool Cross Probe CIC Verilog Simulator Cadence NC-Verilog Verilog-XL VHDL Simulator Cadence 8

NC-VHDL Synopsys VCS VHDL Simulator Debug Tool CIC Spring Soft Verdi Verilog VHDL Simulator [5] [6] Debug Tool Verdi [7] [8] 2-1-3 Co-simulation HDL RTL Code IC (Logic Synthesis) IC (Co-simulation) RTL HDL Code RTL HDL Code 4 Digital/Analog Co-simulation 2-2 Gate-level Pre-layout Verification Gate-level Pre-layout Verification Logic Synthesis Gate-level Pre-layout Simulation Co-simulation Gate-level Pre-layou t 2-2-1 Logic Synthesis IC RTL RTL HDL Code RTL Code AND OR (Gate-level) Gate-level HDL Code RTL Code Standard Cell Standard Cell Gate-level HDL Code Timing Power Area (Coding Style) 9

(Constraint) CIC Synopsys Design Compiler [9] Cell Library [1][2] Design Compiler Low-power (Design for Test and ATPG) [10] [11] 2-2-2 Gate-level Pre-layout Simulation Gate-level HDL Code (Input Test Pattern) HDL Simulator Gate-level Pre-layout Verification RTL Debug Tool Gate-level Pre-layout Verification [5] [6] [9] 2-2-3 Co-simulation Gate-level Code IC (Co-simulation) RTL RTL Gate-level Code Layout Layout Layout 10

2-3 Gate-level Post-layout Verification Gate-level Post-layout Verification APR Gate-level Post-layout Simulation Co-simulation DRC/Block Box LVS Gate-level Post-layout 2-3-1 APR IC Gate-level / Layout Gate-level HDL Code (Auto Place & Route, APR) Layout APR Standard Cell Layout Cell Library Layout Gate-level Post-layout HDL Code Timing Power Area Clock Tree Balance Signal Integrity Power Domain Isolation Cell IC CIC APR Cadence SoC Encounter Synopsys IC Compiler [12] [13] 2-3-2 Gate-level Post-layout Simulation APR Gate-level Post-layout HDL Code Delay Gate-level Pre-layout Verification (Input Test Pattern) HDL Simulator Gate-level Post-layout Verification Debug Tool 2-3-3 Co-simulation Gate-level Post-layout HDL Code IC 11

(Co-simulation) Gate-level Pre-layout Verification APR Gate-level Post-layout HDL Code Release 2-3-4 DRC/Block Box LVS APR Layout DRC (Design Rule Check) Layout Design Rule DRC Layout APR Gate-level Post-layout Code Block Box LVS (Layout vs. Schematic) Layout (Extract) Schematic Gate-level Post-layout Code Block Box CIC Standard Cell Standard Cell Standard Cell LVS Block Box LVS Layout Release DRC LVS CIC Mentor Graphics Calibre DRC Block Box LVS [12][13] Calibre DRC/LVS [14] 12

3 Design Flow for Analog Part (Full-custom) CIC TSMC35/TSMC18/UMC90 [15] 3 IC Full-custom Design Flow IC Full-custom / Full-custom [16] IC Co-simulation LEF Generation Netlist/Schematic Editing (From Digital Part) Verified RTL HDL Code Verified Gate -level Code & Delay Information Netlist/Schematic Optimization Netlist/Schematic Pre -layout Verification Verified Gate -level Post-layout Code & Delay Information Pre-layout Simulation Function/Timing/Power Correct Front End Verified Netlist/Schematic Co-simulation Co -sim Verified Netlist/Schematic Layout Editing Back End Full-custom Layout (From Digital Part) DRC Verification Verified Gate -level Code & Delay Information Verified Gate -level Post -layout Code & Delay Information DRC -clean Full-custom Layout LVS DRC/LVS -clean Full-custom Layout LPE LEF Transforming Netlist with parasitic Information Post-layout Verification Released Full-custom LEF Released Full-custom Layout Post-layout Simulation Function/Timing/Power Meet Spec. LEF Generation Verified Netlistwith parasitic Information Co-simulation Released Netlist with parasitic Information Design Flow for Analog Part in Mixed-Signal IC Design (Full-custom) 13

Full-custom Design Flow for Analog Part 3 1. Pre-layout Verification 2. Post-layout Verification 3. LEF Generation IC Design Flow for Analog Part 3-1 Pre-layout Verification Pre-layout Verification Netlist/Schematic Editing Netlist/Schematic Optimization Pre-layout Simulation Co-simulation Function 3-1-1 Netlist/Schematic Editing ( ) (Schematic) (Netlist) Circuit Simulator Netlist/Schematic Editing Netlist/Schematic Editing Timin g Power Area 3-1-2 Pre-layout Simulation Full-custom Design Flow Netlist Schematic Circuit Simulator 4 1. SPICE Netlist Synopsys HSPICE SPICE Circuit Simulator SPICE Netlist SPICE Netlist HSPICE 14

[17] 2. Cadence Composer Schematic Schematic HSPICE Netlist HSPICE SPICE SPICE (Hierarchy) Composer Schematic HSPICE Netlist HSPICE [16] 3. Cadence Composer Schematic Cadence Spectre ( Analog Design Environment ADE Analog Artist) Schematic Spectre Netlist Spectre Cadence HPSICE Spectre Circuit Simulator Cadence ADE Co-simulation Cadence Circuit Optimization Tool IC Full-Custom ADE Spectre Netlist Spectre [18] 4. SPICE Netlist Fast SPICE Simulator Fast SPICE Simulator HSPICE VLSI Fast SPICE Simulator SPICE 3%~5% Circuit Simulator 50k CIC Fast SPICE Simulator Synopsys Nanosim Cadence Ultrasim Chip Level Nanosim [19] Ultrasim [18] 15

3-1-3 Netlist/Schematic Optimization Schematic/Netlist ( ) CIC Cadence NeoCircuit Cadence Spectre NeoCircuit NeoCircuit NeoCircuit Spectre [20] NeoCircuit Spectre 3-1-4 Co-simulation Schematic/Netlist Full-custom/ Full-custom IC Layout Editing IC (Co-simulation) Schematic/Netlist Schematic/Netlist Layout Editing 4 Digital/Analog Co-simulation 3-2 Post-layout Verification Post-layout Verification Layout Editing DRC/LVS LPE/Post-layout Simulation Co-simulation Post-layout 3-2-1 Layout Editing IC Full-custom/ Schematic/Netlist Schematic/Netlist 16

Layout Editor Schematic/Netlist Layout Layout Full-custom/ Layout CIC Layout Editor Cadence Virtuoso-XL Spring Soft Laker Virtuoso-XL Full-custom/ Layout ( ) Layout [16] Full-custom/ Layout [14] Laker Virtuoso-XL 3-2-2 DRC/LVS Layout Editor Layout DRC (Design Rule Check) Layout Design Rule DRC Layout Pre-layout Verification Schematic/Netlist LVS(Layout vs. Schematic) Layout (Extract) Schematic Pre-layout Verification Schematic DRC LVS CIC Mentor Graphics Calibre Virtuoso-XL Laker Layout Calibre DRC/LVS [16] [21] Calibre DRC/LVS [14] 3-2-3 LPE/Post-layout Simulation DRC/LVS Layout LPE (Layout Parasitic Extraction) Netlist Post-layout Simulation Post-layout Simulation Timing Power Area Full-custom/ Release Schematic/Netlist Layout CIC LPE Tool Calibre XRC Calibre XRC SPICE Netlist HSPICE Post-layout Verification 17

LPE Post-layout Verification [16] Calibre XRC [14] 3-2-4 Co-simulation IC Full-custom/ Post-layout Simulation (Co-simulation) Post-layout Simulation Schematic/Netlist Layout LEF Generation Layout 4 Digital/Analog Co-simulation 3-3 LEF Generation IC Full-custom/ GDSII Layout APR LEF (Layout Extraction File) IC Layout APR Cell Stand Cell Layout LEF APR Layout Cell Boundary IO Pin CIC GDSII LEF Cadence Abstract Generator [18] 18

4 Digital/Analog Co-simulation (Co-simulation) IC CIC Cell-based RTL Verification Cell-based Pre-layout Verification Full-custom Pre-layout Verification Full-custom Post-layout Verification Cell-based Post-layout Verification 5 5 co-sim. Cell-Based RTL Verification 1. Full-custom Pre-layout Verification co -sim. co -sim. co-sim. 2. co-sim. co -sim. co-sim. Cell-Based Pre-layout Verification 3. 4. Full-custom Post-layout Verification co -sim. co-sim. co-sim. 5. co-sim. Cell-Based Post-layout Verification co-sim. co-sim. Cell-based / Full-custom Layout Integration Required co-sim. Optional co -sim. Digital/Analog Co-simulation in Mixed-Signal IC Design IC 5 CIC 2 2. 19

2. /Cell-based Pre-layout Verification /Full-custom Pre -layout Verification Standard Cell Full-custom/ Layout /Full-custom Pre -layout Layout Layout 4 Layout Layout ( 5-2 ) 1. 3. 4. 5. 1. /Cell-based RTL Verification /Full-custom Pre -layout Verification 3. /Cell-based Pre-layout Verification Standard Cell /Full-custom Post-layout Verification 4. Layout /Cell-based Post-layout Verification Layout /Full-custom Pre-layout Verification Standard Cell /Full-custom IC Layout Pre-layout Verification 20

5. Layout Layout /Cell-based Post-layout Verification /Full-custom Post-layout Verification Layout Layout Layout 2 CIC / 3 1 4-1 AMS Environment Cadence AMS Designer Cadence Virtuoso IC Schematic Verilog Cadcnce Spectre Cadcnce NC-Sim AMS SimVision NC-Sim Digital Simulator Spectre Analog Simulator AMS Simulator Mixed Language Debugger Mixed Waveform Display AMS Environment in Mixed-Signal IC Co-simulation AMS Virtuoso Cell Configuration View Configuration View Connect Module ADE Spectre Virtuoso Schematic 21

/Full-custom Pre-layout Verification /Cell-based Verilog RTL Pre-layout Post-layout Gate-level HDL Code AMS [18] 4-2 UltrasimVerilog Environment Cadence AMS Designer Cadence Virtuoso IC Schematic Verilog Cadcnce Fast SPICE Simulator Ultrasim Cadcnce Verilog-XL SimVision Verilog-XL Digital Simulator Ultrasim Analog Simulator UltrasimVerilog Simulator Mixed Language Debugger Mixed Waveform Display UltrasimVerilog Environment in Mixed-Signal IC Co-simulation UltrasimVerilog Virtuoso Cell Configuration View Configuration View IE Models ADE Ultrasim Virtuoso Schematic /Full-custom Pre-layout Verification /Cell-based Verilog RTL Pre-layout Post-layout Gate-level HDL Code Fast SPICE Simulator Ultrasim Spectre A D Pre-layout UltrasimVerilog Ultrasim [18] 22

4-3 Nanosim Integrated with VCS Environment (NIV) Synopsys Fast SPICE Simulator Nanosim /Full-custom SPICE Netlist Synopsys Verilog Simulator VCS Spring Soft Verdi SPICE Netlist Transistor Verilog Netlist Verilog NanoSim VCS Simulation output Waveform Viewer Simulation output NIV Environment in Mixed-Signal IC Co-simulation NIV IC /Full-custom SPICE Verilog ( SPICE-top) Verilog /Full-custom SPICE ( Verilog-top) 2 NIV Command Line SPICE Netlist Verilog HDL Code /Full-custom Pre-layout Post-layout SPICE Netlist /Cell-based Verilog RTL Pre-layout Post-layout Gate-level HDL Code A D Pre-layout Nanosim VCS [19] 23

5 Digital/Analog Layout Integration and Full Chip Post-layout Verification IC CIC Layout Released Full-custom LEF Released Pre -layout Gate-level Code & Delay Information Released Full-custom Layout Released APR Layout Layout Integration Integrated Layout DRC Verification DRC-clean Integrated Layout Block Box LVS Verification Full-Chip Gate-level Post-layout Verification Block Box DRC/LVS -clean Integrated Layout PVS DRC PVS DRC-clean Integrated Layout PVS LPE Whole Chip Netlist with parasitic Information PVS NanosimSimulation Function/Timing/Power Meet Spec. Verified Whole Chip Layout Verified Whole Chip Netlist with parasitic Information PVS Transistor-level Post-layout Verification Digital/Analog Layout Integration and Verification in Mixed-Signal IC Design 24

Digital/Analog Layout Integration and Verification 2 1. Full-Chip Gate-level Post-layout Verification 2. PVS Transistor-level Post-layout Verification Full-Chip Gate-level Post-layout Verification 2 Design Flow for Digital Part Gate-level Post-layout Verification DRC Block Box LVS Gate-level Post-layout Verification PVS Transistor-level Post-layout Verification CIC Full Chip Transistor-level Post-layout Verification IC CIC PVS Transistor-level Post-layout 5-2 Full-Chip Gate-level Post-layout Verification Transistor-level Post-layout Verification CIC IC Digital/Analog Layout Integration and Verification 5-1 Full-Chip Gate-level Post-layout Verification Full-Chip Gate-level Post-layout Verification Layout Integration DRC/Block Box LVS Gate-level Post-layout 5-1-1 Layout Integration IC 2 Layout Integration 1. Layout Integration by Layout Editor IC APR Physical Layout APR 25

CIC Layout Editor (Cadence Virtuoso-XL Spring Soft Laker) / GDSII Layout Full-custom IC / Layout Layout 2. Layout Integration by APR Tool IC APR / Physical Layout CIC APR (Cadence SoC Encounter) / LEF APR IC Layout Layout Layout [18] 5-1-2 DRC/Block Box LVS IC IC Cell-based DRC Block Box LVS Layout DRC LVS IC CIC Cell-based Design Kit DRC Block Box LVS IC Layout DRC Block Box LVS [18] 5-2 PVS Transistor-level Post-layout Verification Full-Chip Gate-level Post-layout Verification CIC Post-layout Verification CIC PVS (Post-Layout Verification System) Layout DRC LPE PVS Transistor-level Post-layout Verification 26

5-2-1 PVS DRC/LPE/Nanosim Simulation (Remote Login) CIC Full-Chip Layout CIC CIC 4 PVS Transistor-level Post-layout Verification 1. Standard Cell Standard Cell Layout CIC Standard Cell Layout Block Box 2. Calibre Layout DRC 3. Calibre Layout LPE IO Pad Netlist 4. Nanosim Layout Transistor-level Post-layout Verification IC IC PVS PVS Transistor-level Post-layout Verification [18] [19] 6 Tape Out IC CIC CIC IC CIC TSMC35 TSMC18 7 Measurement CIC 93000 SoC IC [22] [23] CIC PCB CIC 27

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