2 2009 2 ACTA ELECTRONICA SINICA Vol. 37 No. 2 Feb. 2009 1, 1, 1, 2, 1 (11, 310027 ;21, 310012) :, (SoC).. SoC,,. H1264. SoC,. : ; ; : TP368 : A : 037222112 (2009) 0220305207 A Multiproce ssor Prototype and Its SoC De sign Methodology HUANG Kai 1,YIN Liao 1,LIN Feng2yi 1,GE Hai2tong 2,YAN Xiao2lang 1 (11 Institute of VLSI design, Zhejiang University, Hangzhou, Zhejiang 310027, China ; 21 C2Sky Microsystems Company, Hangzhou, Zhejiang 310012, China) Abstract : Fast development of embedded application drives the SoC design more complex. How to design multiprocessor SoC efficiently and reliably is becoming a challenge to the designers. To address this challenge,a new multiprocessor prototype and its SoC design methodology are proposed in this paper. It combines multi processors and their communication into one software2 hardware prototype in different abstraction levels. The method of seamless refinement from high level abstraction to low level VLSI implementation can design and verify the software/ hardware interface and improve designing software/ hardware architecture effi2 ciently. The experiment of H. 264 decoder shows the feasibility of multiprocessor prototype in both function and physical implemen2 tation. The seamless refinement method based on this prototype can ensure the correctness of SoC design and be helpful for its soft2 ware/ hardware architecture optimization. 1 Key words : multi2processor prototype ;System on Chip (SoC) ;software2hardware co2design, (SoC) IC., (MPSoC) [1]., MPSoC : (1) ; (2) ; (3) [2]., MPSoC, MPSoC [3]. SoC :,,. 2, SoC : (Virtual Prototype) ( Fast Prototype). ( SpecC System C ) SoC,, SoC [4]. SpecC [5],. CoWare ConvergenSC [6],Mentor Seamless CVE [7] SystemC,,, :2007211230 ; :2008210220
306 2009.,.,, IP,. ( FPGA ) SoC,. Xilinx DSPTM System Genera2 tor [8] Altera DSP BuilderTM [9] Simulink, FPGA.,. FPGA,, FPGA,., ARM FPGA SoC., SoC. 1, SoC., : (1) SoC, ; (2), ; (3) ( ) ( ).. 3 SoC 311,,,,., : ( Simulink) (System C TLM) RTL (Verilog) FPGA(Xilinx). 31111 2 : (CPU SS) (Memory SS).,.., ( Multi2Core HAD Con2 troller) ( Performance Monitor Controller) (Cache OP. Snooper) (Power Management),.,,,, ;, ;,. 2( a), ( ),,. (Mail Box). 2( b),. (CPU SS Interface) AHB AHB, DMA. ( Cache Sync). ( SS Monitor),,. DMA. 2( b), DMA,,.., AHB
2 : 307., DMA. AHB 32 64 128,. TAP..,.,. (AHB HPROT ).,. ( ),,... 31112 3 ( a),,,. 3( b), : ( Hardware Dependent Software, HDS) ( Hardware Abstraction Layer, HAL).,, HDS API( 3 ( c) recv - data send - data).,. HDS,, ( GFIFO HWFIFO). uclinux Linux. HDS, HAL (Firmware), IO..,,. 312 SoC. SoC Simulink SoC [11], 4. 31211 ( 1 2) Simulink
308 2009. Simulink : Simulink Simulink. Simulink, ( S2function) Simulink. 1, ( C/ C + + ) Simulink,,. 2,Simulink Simulink ( CAAM),. CAAM,. CPU,.,Simulink CAAM XML Colif CAAM. Colif,, CAAM. 31212 ( 3 4) Colif CAAM.,. : (Virtual Architecture,VA) (Transaction2Accurate,TA) (Virtu2 al Prototype,VP). : CPU.,. CPU.,.,,,., HDS. CPU., BFM CPU., HAL, HDS.,. ( ISS), HAL. 4, ( Hardware archi2 tecture Gen) (Multithread code Gen) Colif CAAM., ; Colif CAAM, CPU., Main Makefile ; ; HDS,.
2 : 309 31213 ( 5 6 7),., RTL. SoC Colif CAAM RTL, RTL. SoC (Config Parser) Colif CAAM, IP IP ( IP Integrator) ( Platform Gen). IP, IP,. IP,, (Regress).,RTL FPGA. 411 H1264 JM713, 30 QCIF Foreman. H1264 Simulink 83 24 310 43 IF,5 FOR 101 Simulink. ( :8 3. 16GHz Intel Xeon) FPGA ( Virtex24 XC4VLX1602FF15) 2,VA (18 ),. TA, 30 %,. TA [13], 80 %,. VP ISS, 90 %,,. 4 32 CKCore,,,. 1, : CK510 Application VA TA VP FPGA CK520 ( ) CK560 (MMU) CK510E H. 264 302frame 4s 18s 380s 4260s (DSP ) [11] QCIF Foreman (50M Hz). H1264 Timing Accuracy 0 % 30 80 % 90 % 100 %, SoC 41111 H. 264 H1264 GNU GCC, 5 ( a) ( d)
310 2009. H1264 120K, 300K,. VA, H1264. 2, 1,3 4 Deblocking. 5 ( d), p2 p4 p1, MB 015K byte. TA VP HdS, HdS 17K: OS kernel OS C 118K 112K 318K, HAL DMA LCD. 41112 H. 264 5 ( i) ( j), Cache 2K 4K 8K,H1264 Cache,8K Cache 9815 %, Cache (miss) (Refill),, Cache 8K Cache 90 %., 5 ( g),vp, Cache Cache.,,., CPU2, 70 % 16K 48K 32K, CPU2,. FPGA ( 8 256KB, DDR ) 5( i) Cache, (MO) ( 12 %)., H1264,. 5 ( h) ( xp x ),,. 5 ( j), : (comp, ), (idle, ) (comm, ). 2 P, 1 ( p1), 2( p2). p2, : Deblocking ( p2,4 P p3) ( p3,4 P p4). p1, : ( p1) ( p2). 4 P 1 P. 412 SMIC 0113 m, 6. 208, AHB. 24141, CKCore 85 %. (Worst Case), 240MHz, 120MHz,, 20 30 QCIF H1264. 5 SoC, SoC.,,. SoC,,. H1264. SoC,.,,. : [1] A A Jerraya,et al. Special Issue on MPSoC[J ]. IEEE Comput2 er,2005,38 (7) :36-40. [2 ] Grant Martin. Overview of the MPSoC Design Challenge [ A ]. 43th DAC[ C ]. New York :ACM,2006. 274-279. [ 3 ] Ahmed Jerraya, Wayne Wolf. Multiprocessor Systems2on2Chip [ M ]. San Francisco : Elsevier Morgan Kaufmann, 2005. 11-13. [ 4 ] Keutzer K et al. System2level design :Orthogonalization of con2
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