查询 供应商 FEATURES 2.7-V to 5.5-V Analog Supply, Low Power: 10.6 mw (+VA = 2.7 V, +VBD = 1.8 V) 500-kHz Sampling Rate Excellent DC Performance ±1.2 LSB Typ, ±2 LSB Max INL ±0.6 LSB Typ, ±1 LSB Max DNL APPLICATIONS Communications Transducer Interface Medical Instruments Magnetometers Industrial Process Control Data Acquisition Systems Automatic Test Equipment DESCRIPTION LOW POWER, 16-BIT, 500-kHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE 16-Bit NMC Over Temperature ±0.5 mv Max Offset Error at 2.7 V ±1 mv Max Offset Error at 5 V The is a low power, 16-bit, 500-ksps Excellent AC Performance at f i = 10 khz with analog-to-digital converter with a unipolar input. The 91 db SNR, 101 db SFDR, 98 db THD device includes a 16-bit capacitor-based SAR A/D Built-In Conversion Clock (CCLK) converter with inherent sample and hold. 1.65 V to 5.5 V I/O Supply The is based on the same core and includes a 2-to-1 input MUX with programmable SPI/DSP Compatible Serial option of TAG bit output. Both the and SCLK up to 50 MHz offer a high-speed, wide voltage serial Comprehensive Power-Down Modes: interface and are capable of chain mode operation Deep Powerdown when multiple converters are used. Nap Powerdown These converters are available in a 16-lead TSSOP package and are fully specified for operation over the Auto Nap Powerdown industrial -40 C to +85 C temperature range. Unipolar Input Range: 0 V to V ref Software Reset Low Power, High-Speed SAR Converter Family Global CONVST (Independent of CS) Type/Speed 500 khz 1 MHz Programmable Status/Polarity /INT Single ADS8329 16 Bit Pseudo-Diff 16-Pin TSSOP Package Multi-Chip Daisy Chain Mode Programmable TAG Bit Output Manual/Auto Channel Select Mode () 捷多邦, 专业 PCB 打样工厂,24 小时加急出货 Dual ADS8330 +IN1 +IN0 COM NC +IN IN REF+ REF + _ SAR CDAC COMPARATOR OSC OUTPUT LATCH and 3 STATE DRIVER CONVERSION and CONTROL LOGIC SDO FS/CS SCLK SDI CONVST /INT/CDI Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Copyright 2006, Texas Instruments Incorporated
MODEL This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) MAXIMUM MAXIMUM MAXIMUM INTEGRAL DIFFERENTIAL OFFSET PACKAGE PACKAGE TEMPERATURE ORDERING LINEARITY LINEARITY ERROR TYPE DESIGNATOR RANGE INFORMATION (LSB) (LSB) (mv) TRANSPORT MEDIA QUANTITY IPW Tube 90 I ±3 1/+2 ±0.8 TSSOP-16 PW 40 C to 85 C Tape and reel IPWR 2000 IBPW Tube 90 IB ±2 ±1 ±0.5 TSSOP-16 PW 40 C to 85 C Tape and reel IBPWR 2000 IPW Tube 90 I ±3 1/+2 ±0.8 TSSOP-16 PW 40 C to 85 C Tape and reel IPWR 2000 IBPW Tube 90 IB ±2 ±1 ±0.5 TSSOP-16 PW 40 C to 85 C Tape and reel IBPWR 2000 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) Voltage +IN to AGND IN to AGND +VA to AGND UNIT 0.3 V to +VA + 0.3 V 0.3 V to +VA + 0.3 V 0.3 V to 7 V Voltage range +VBD to BDGND 0.3 V to 7 V AGND to BDGND Digital input voltage to BDGND Digital output voltage to BDGND 0.3 V to 0.3 V 0.3 V to +VBD + 0.3 V 0.3 V to +VBD + 0.3 V T A Operating free-air temperature range 40 C to 85 C T stg Storage temperature range 65 C to 150 C Junction temperature (T J max) 150 C Vapor phase (60 sec) 215 C Lead temperature, soldering TSSOP-16 Infrared (15 sec) 220 C Package Power dissipation (T J Max - T A )/θ JA θ JA thermal impedance 47 C/W (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 Submit Documentation Feedback
SPECIFICATIONS T A = 40 C to 85 C, +VA = 2.7 V, +VBD = +VA 1.5 to +1.65 V, V ref = 2.5 V, f SAMPLE = 500 khz (unless otherwise noted) ANALOG INPUT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Full-scale input voltage (1) +IN ( IN) or (+INx COM) 0 +V ref V Absolute input voltage +IN, +IN0, +IN1 AGND 0.2 +VA + 0.2 IN or COM AGND 0.2 AGND + 0.2 Input capacitance 40 45 pf No ongoing conversion, Input leakage current -1 1 na DC Input Input channel isolation, only SYSTEM PERFORMANCE At dc 108 V I = ±1.25 V pp at 50 khz 101 Resolution 16 Bits No missing codes 16 Bits IB, 2 ±1.2 2 INL Integral linearity IB LSB (2) I, I 3 ±2 3 IB, Differential 1 ±0.6 1 DNL IB LSB linearity (2) I, I 1 ±1 2 IB, 0.5 ±0.1 0.5 E O Offset error (3) IB mv I, I 0.8 ±0.1 0.8 Offset error drift 0.2 PPM/ C E G Gain error 0.25 0.07 0.25 %FSR Gain error drift 0.3 PPM/ C At dc 70 CMRR Common mode rejection ratio db V I = 0.4 V pp at 1 MHz 50 Noise 33 µv RMS PSRR Power supply rejection ratio At FFFFh output code (3) 78 db SAMPLING DYNAMICS t CONV Conversion time 18 CCLK t SAMPLE1 Manual trigger 3 Acquisition time t SAMPLE2 Auto trigger 3 Throughput rate 500 khz Aperture delay 5 ns Aperture jitter 10 ps Step response 100 ns Overvoltage recovery 100 ns (1) Ideal input span, does not include gain or offset error. (2) LSB means least significant bit (3) Measured relative to an ideal full-scale input [+IN ( IN)] of 2.5 V when +VA = 2.7 V. V db CCLK Submit Documentation Feedback 3
SPECIFICATIONS (continued) T A = 40 C to 85 C, +VA = 2.7 V, +VBD = +VA 1.5 to +1.65 V, V ref = 2.5 V, f SAMPLE = 500 khz (unless otherwise noted) DYNAMIC CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V IN = 2.5 V pp at 10 khz -98 THD Total harmonic distortion (4) db V IN = 2.5 V pp at 100 khz -83.5 V IN = 2.5 V pp at 10 khz 88.5 SNR Signal-to-noise ratio db V IN = 2.5 V pp at 100 khz 85 V IN = 2.5 V pp at 10 khz 88.5 SINAD Signal-to-noise + distortion db V IN = 2.5 V pp at 100 khz 81 V IN = 2.5 V pp at 10 khz 101 SFDR Spurious free dynamic range db V IN = 2.5 V pp at 100 khz 84 CLOCK -3dB Small signal bandwidth 30 MHz Internal conversion clock frequency 10.5 11 12.2 MHz SCLK External serial clock EXTERNAL VOLTAGE REFERENCE INPUT V ref Used as I/O clock only 33 As I/O clock and conversion clock 1 21 Input reference V ref (REF+ REF ) 3.6 V +VA 2.7 V 0.3 2.525 range (REF ) AGND 0.1 0.1 Resistance (5) Reference input 80 kω DIGITAL INPUT/OUTPUT Logic family CMOS V IH High-level input voltage (+VA 1.5) V +VBD 1.65 V 0.65 (+VBD) +VBD + 0.3 V V IL Low-level input voltage (+VA 1.5) V +VBD 1.65 V 0.3 0.35 (+VBD) V I I Input current V I = +VBD or BDGND -50 50 na C i Input capacitance 5 pf (+VA 1.5) V +VBD 1.65 V, V OH High-level output voltage +VBD 0.6 +VBD V I O = 100 µa (+VA 1.5) V +VBD 1.65 V, V OL Low-level output voltage 0 0.4 V I O = 100 µa C O Output capacitance 5 pf C L Load capacitance 30 pf Data format straight binary POWER SUPPLY REQUIREMENTS Power supply +VBD 1.65 +VA 1.5 (+VA) V voltage +VA 2.7 3.6 V 500-kHz Sample rate 3.8 5 Supply current Nap mode 0.2 0.4 PD Mode 2 50 na Buffer I/O supply current 500 KSPS 0.2 ma Power dissipation +VA = 2.7 V, +VBD = 1.8 V 10.6 14 mw TEMPERATURE RANGE T A Operating free-air temperature 40 85 C (4) Calculated on the first nine harmonics of the input frequency (5) Can vary ±30% MHz V ma 4 Submit Documentation Feedback
SPECIFICATIONS T A = 40 C to 85 C, +VA = 5 V, +VBD = +5.5 V to +1.65 V, V ref = 4.096 V, f SAMPLE = 500 khz (unless otherwise noted) ANALOG INPUT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Full-scale input voltage (1) +IN ( IN) or (+INx COM) 0 +V ref V Absolute input voltage +IN, +IN0, +IN1 AGND 0.2 +VA + 0.2 IN or COM AGND 0.2 AGND + 0.2 Input capacitance 40 45 pf No ongoing conversion, Input leakage current -1 1 na DC Input Input channel isolation, only SYSTEM PERFORMANCE At dc 109 V I = ±1.25 V pp at 50 khz 101 Resolution 16 Bits No missing codes 16 Bits IB, 2 ±1.5 2 INL Integral linearity IB LSB (2) I, I -3 ±2 3 IB, Differential 1 ±0.7 1 DNL IB LSB linearity (2) I, I 1 ±1 2 IB, 1 ±0.4 1 E O Offset error (3) IB mv I, I 1.25 ±0.4 1.25 Offset error drift 0.5 PPM/ C E G Gain error 0.25 0.07 0.25 %FSR Gain error drift 0.3 PPM/ C At dc 70 CMRR Common mode rejection ratio db V I = 1 V pp at 1 MHz 50 Noise 33 µv RMS PSRR Power supply rejection ratio At FFFFh output code (3) 78 db SAMPLING DYNAMICS t CONV Conversion time 18 CCLK t SAMPLE Manual trigger 3 1 Acquisition time t SAMPLE Auto trigger 3 2 Throughput rate 500 khz Aperture delay 5 ns Aperture jitter 10 ps Step response 100 ns Overvoltage recovery 100 ns (1) Ideal input span, does not include gain or offset error. (2) LSB means least significant bit (3) Measured relative to an ideal full-scale input [+IN ( IN)] of 4.096 V when +VA = 5 V. V db CCLK Submit Documentation Feedback 5
SPECIFICATIONS (continued) T A = 40 C to 85 C, +VA = 5 V, +VBD = +5.5 V to +1.65 V, V ref = 4.096 V, f SAMPLE = 500 khz (unless otherwise noted) DYNAMIC CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V IN = 4.096 V pp at 10 khz -96 THD Total harmonic distortion (4) V IN = 4.096 V pp at 100 khz, /28IB -95.7 db V IN = 4.096 V pp at 100 khz, /28I -95.7 V IN = 4.096 V pp at 10 khz 91 SNR Signal-to-noise ratio db V IN = 4.096 V pp at 100 khz 89 V IN = 4.096 V pp at 10 khz 91 SINAD Signal-to-noise + distortion db V IN = 4.096 V pp at 100 khz 88 V IN = 4.096 V pp at 10 khz 100 SFDR Spurious free dynamic range V IN = 4.096 V pp at 100 khz, /28IB 98.8 db CLOCK V IN = 4.096 V pp at 100 khz, /28I 98.8-3dB Small signal bandwidth 30 MHz Internal conversion clock frequency 10.9 12 12.6 MHz SCLK External serial clock EXTERNAL VOLTAGE REFERENCE INPUT V ref Used as I/O clock only 50 As I/O clock and conversion clock 1 21 Input reference V ref (REF+ REF ) 5.5 V +VA 4.5 V 0.3 4.096 4.2 range (REF ) AGND 0.1 0.1 Resistance (5) Reference input 80 kω DIGITAL INPUT/OUTPUT Logic family CMOS V IH High-level input voltage 5.5 V +VBD 4.5 V 0.65 (+VBD) +VBD + 0.3 V V IL Low-level input voltage 5.5 V +VBD 4.5 V 0.3 0.35 (+VBD) V I I Input current V I = +VBD or BDGND -50 50 na C i Input capacitance 5 pf 5.5 V +VBD 4.5 V, V OH High-level output voltage +VBD 0.6 +VBD V I O = 100 µa 5.5 V +VBD 4.5 V, V OL Low-level output voltage 0 0.4 V I O = 100 µa C O Output capacitance 5 pf C L Load capacitance 30 pf Data format straight binary POWER SUPPLY REQUIREMENTS Power supply +VBD 1.65 3.3 5.5 V voltage +VA 4.5 5 5.5 V 500-kHz Sample rate 5 6.2 Supply current Nap mode 0.3 0.5 PD Mode 6 50 na Buffer I/O supply current 500 KSPS 1 ma Power dissipation TEMPERATURE RANGE +VA = 5 V, +VBD = 5 V 30 38.5 +VA = 5 V, +VBD = 1.8 V 25.4 32 T A Operating free-air temperature 40 85 C (4) Calculated on the first nine harmonics of the input frequency (5) Can vary ±30% MHz V ma mw 6 Submit Documentation Feedback
TIMING CHARACTERISTICS All specifications typical at 40 C to 85 C, +VA = 2.7 v, +VBD = 1.8 V (1)(2) PARAMETER MIN TYP MAX UNIT External, 0.5 10.5 fcclk Frequency, conversion clock, CCLK f CCLK = 1/2 f SCLK MHz Internal 10.5 12 12.2 t su(csf-) Setup time, falling edge of CS to 1 CCLK t h(csf-) Hold time, falling edge of CS to 0 ns t wl(convst) Pulse duration, CONVST low 40 ns t su(csf-) Setup time, falling edge of CS to 20 ns t h(csf-) Hold time, falling edge of CS to 20 ns t su(csr-) Setup time, rising edge of CS to 20 ns t h(csr-) Hold time, rising edge of CS to 20 ns t c(sclk) tsu(csf-sclk1r) Setup time, falling edge of CS to SCLK 5 ns - 5 t c(sclk) twl(sclk) Pulse duration, SCLK low 8 ns - 8 t c(sclk) twh(sclk) Pulse duration, SCLK high 8 ns - 8 I/O Clock only 30 I/O and conversion clock 47.6 1000 t c(sclk) Cycle time, SCLK ns I/O Clock, chain mode 30 I/O and conversion clock, chain mode 47.6 1000 Delay time, falling edge of SCLK to SDO t d(sclkf-sdoinvalid) 10-pF Load 8 ns invalid Delay time, falling edge of SCLK to SDO t d(sclkf-sdovalid) 10-pF Load 25 ns valid Delay time, falling edge of CS to SDO valid, t d(csf-sdovalid) 10-pF Load 25 ns SDO MSB output t su(sdi-sclkf) Setup time, SDI to falling edge of SCLK 8 ns t h(sdi-sclkf) Hold time, SDI to falling edge of SCLK 4 ns Delay time, rising edge of CS/FS to SDO t d(csr-sdoz) 5 ns 3-state Setup time, last falling edge of SCLK before t su(lastsclkf-csr) 10 ns rising edge of CS/FS Delay time, CDI high to SDO high in daisy t d(sdo-cdi) 10-pF Load, chain mode 25 ns chain mode (1) All input signals are specified with t r = t f = 1.5 ns (10% to 90% of V DD ) and timed from a voltage level of (V IL + V IH )/2. (2) See timing diagrams. Submit Documentation Feedback 7
TIMING CHARACTERISTICS All specifications typical at 40 C to 85 C, +VA = +VBD = 5 V (1)(2) PARAMETER MIN TYP MAX UNIT External, 0.5 10.5 fcclk Frequency, conversion clock, CCLK f CCLK = 1/2 f SCLK MHz Internal 10.9 12 12.6 t su(csf-) Setup time, falling edge of CS to 1 CCLK t h(csf-) Hold time, falling edge of CS to 0 ns t wl(convst) Pulse duration, CONVST low 40 ns t su(csf-) Setup time, falling edge of CS to 20 ns t h(csf-) Hold time, falling edge of CS to 20 ns t su(csr-) Setup time, rising edge of CS to 20 ns t h(csr-) Hold time, rising edge of CS to 20 ns t c(sclk) - t su(csf-sclk1r) Setup time, falling edge of CS to SCLK 5 ns 5 t c(sclk) - t wl(sclk) Pulse duration, SCLK low 8 ns 8 t c(sclk) - t wh(sclk) Pulse duration, SCLK high 8 ns 8 I/O Clock only 20 I/O and conversion clock 47.6 1000 t c(sclk) Cycle time, SCLK ns I/O Clock, chain mode 20 I/O and conversion clock, chain mode 47.6 1000 Delay time, falling edge of SCLK to SDO t d(sclkf-sdoinvalid) 10-pF Load 5 ns invalid Delay time, falling edge of SCLK to SDO t d(sclkf-sdovalid) 10-pF Load 12 ns valid Delay time, falling edge of CS to SDO t d(csf-sdovalid) 10-pF Load 12 ns valid, SDO MSB output t su(sdi-sclkf) Setup time, SDI to falling edge of SCLK 8 ns t h(sdi-sclkf) Hold time, SDI to falling edge of SCLK 4 ns Delay time, rising edge of CS/FS to SDO t d(csr-sdoz) 5 ns 3-state Setup time, last falling edge of SCLK t su(lastsclkf-csr) 10 ns before rising edge of CS/FS Delay time, CDI high to SDO high in daisy t d(sdo-cdi) 10-pF Load, chain mode 16 ns chain mode (1) All input signals are specified with t r = t f = 1.5 ns (10% to 90% of V DD ) and timed from a voltage level of (V IL + V IH )/2. (2) See timing diagrams. 8 Submit Documentation Feedback
PIN ASSIGNMENTS PW PACKAGE (TOP VIEW) PW PACKAGE (TOP VIEW) +VA NC +IN IN AGND REF REF+ (REFIN) NC (REFOUT) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 +VBD SCLK BDGND SDO SDI FS/CS /INT CONVST +VA +IN1 +IN0 COM AGND REF REF+ (REFIN) NC (REFOUT) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 +VBD SCLK BDGND SDO SDI FS/CS /INT CONVST NC No internal connection Submit Documentation Feedback 9
Terminal Functions NO. NAME I/O DESCRIPTION TSSOP AGND 5 Analog ground BDGND 14 Interface ground CONVST 9 Freezes sample and hold, starts conversion with next rising edge of internal clock / INT/ CDI 10 O FS/CS 11 +IN 3 I Non inverting input Status output. If programmed as, this pin is low (default) when a conversion is in progress. If programmed as an interrupt (INT), this pin is low for a preprogrammed duration after the end of conversion and a valid data is to be output. The polarity of or INT is programmable. This pin can also be used as a chain data input when the device is operated in chain mode. Frame sync signal for TMS320 DSP serial interface or chip select input for SPI interface slave select (SS-). -IN 4 I Inverting input, usually connected to ground NC 2,8 No connection. REF+ 7 I External reference input. REF- 6 Connect to AGND through individual via. SCLK 15 Clock for serial interface SDI 12 I Serial data in SDO 13 O Serial data out +VA 1 Analog supply, +2.7 V to +5.5 VDC. +VBD 16 Interface supply Terminal Functions NO. NAME I/O DESCRIPTION TSSOP AGND 5 Analog ground BDGND 14 Interface ground COM 4 I Common inverting input, usually connected to ground CONVST 9 Freezes sample and hold, starts conversion with next rising edge of internal clock / INT/ CDI 10 O Status output. If programmed as, this pin is low (default) when a conversion is in progress. If programmed as an interrupt (INT), this pin is low for a preprogrammed duration after the end of conversion and a valid data is to be output. The polarity of or INT is programmable. This pin can also be used as a chain data input when the device is operated in chain mode. FS/CS 11 Frame sync signal for TMS320 DSP serial interface or chip select input for SPI interface +IN1 2 I Second noninverting input. +IN0 3 I First noninverting input NC 8 No connection. REF+ 7 I External reference input. REF- 6 Connect to AGND through individual via. SCLK 15 Clock for serial interface SDI 12 I Serial data in (conversion start and reset possible) SDO 13 O Serial data out +VA 1 Analog supply, +2.7 V to +5.5 VDC. +VBD 16 Interface supply 10 Submit Documentation Feedback
MANUAL TRIGGER / READ While Sampling (use internal CCLK, and INT polarity programmed as active low) CONVST Nth t wl(convst) (active low) Nth t SAMPLE1 = 3 CCLKs min t CONV = 18 CCLKs t SAMPLE1 = 3 CCLKs min INT (active low) t h(csf-) t h(csr-) th(csf-) CS/FS SCLK t h(csf-) t su(csf-) t su(csf-) 1.................... 16 t d(crs-) = 20 ns min 1 SDO Nth 1th Nth SDI 1101b 1101b READ Result READ Result Figure 1. Timing for Conversion and Acquisition Cycles for Manual Trigger (read while sampling) AUTO TRIGGER / READ While Sampling (use internal CCLK, and INT polarity programmed as active low) CONVST = 1 (active low) Nth INT (active low) CS/FS SCLK SDO t CONV = 18 CCLKs t SAMPLE2 = 3 CCLKs t CONV = 18 CCLKs t SAMPLE2 = 3 CCLKs t h(csf-) t su(csf-) t h(csf-) t su(csf-) 1...................16 1...................16 1 t h(csf-) N 1th N 1th Nth SDI 1110b.............. 1101b 1101b CONFIGURE READ Result READ Result Figure 2. Timing for Conversion and Acquisition Cycles for Autotrigger (read while sampling) Submit Documentation Feedback 11
MANUAL TRIGGER / READ While Converting (use internal CCLK, and INT polarity programmed as active low) CONVST Nth N 1th t wl(convst) Nth N + 1th (active low) t CONV = 18 CCLKs t SAMPLE1 = 3 CCLKs min INT (active low) t h(csf-) t su(csf-) t su(csr-) CS/FS SCLK SDO t su(csf-) t h(csf-) 1....................16 1 N 1th N th SDI 1101b READ Result 1101b READ Result Figure 3. Timing for Conversion and Acquisition Cycles for Manual Trigger (read while converting) AUTO TRIGGER / READ While Converting (use internal CCLK, and INT polarity programmed as active low) CONVST = 1 (active low) INT (active low) CS/FS SCLK SDO t su(csf-) t h(csr-) 1...................16 N 1 th?? t CONV = 18 CCLKs t Nth SAMPLE2 N + 1th t CONV = 18 CCLKs = 3 CCLKs min t SAMPLE2 = 3 CCLKs min t h(csf-) th(csf-) t su(csr-) 1.................. 16 1.................. 16 t su(csr-) N 1 th N th SDI 1110b............... CONFIGURE 1101b READ Result 1101b READ Result Figure 4. Timing for Conversion and Acquisition Cycles for Autotrigger (read while converting) 12 Submit Documentation Feedback
SCLK CS/FS 1 2 3 4 5 6 7 14 15 16 t su(csf SCLK1R) t wl(sclk) t c(sclk) t wh(sclk) t su(lastsclk CSR) t d(sclkf SDOINVALID) SDO Hi Z t d(csr SDOZ) t d(sclkf SDOVALID) t d(csf SDOVALID) MSB MSB 1 MSB 2 MSB 3 MSB 4 MSB 5 MSB 6 LSB+2 LSB+1 LSB SDI t h(sdi SCLKF) MSB MSB 1 MSB 2 MSB 3 MSB 4 MSB 5 MSB 6 LSB+2 LSB+1 LSB t su(sdi SCLKF) Figure 5. Detailed SPI Transfer Timing MANUAL TRIGGER / READ While Sampling (use internal CCLK active high, and INT active low, TAG enabled, auto channel select) Nth CH0 Nth CH0 CONVST t wl(convst) t wl(convst) (active low) Nth CH0 t SAMPLE1 t CONV = 3 CCLKs min = 18 CCLKs Nth CH1 t CONV = 18 CCLKs INT (active low) t su(csf-) t h(csf-) CS/FS SCLK SDO SDI Hi Z 1....................... 16 17 1....................... 16 17 t d(csr-) = 20 ns MIN 1101b READ Result N 1th CH1 TAG = 1 1101b READ Result Nth CH0 Figure 6. Simplified Dual Channel Timing TAG = 0 Hi Z Submit Documentation Feedback 13
TYPICAL CHARACTERISTICS At 40 C to 85 C, V ref (REF+ REF ) = 4.096 V when +VA = +VBD = 5 V or V ref (REF+ REF ) = 2.5 V when +VA = +VBD = 2.7 V, f SCLK = 21 MHz, f i = DC for DC curves, f i = 100 khz for AC curves (unless otherwise noted) CROSSTALK DIFFERENTIAL NONLINEARITY INTEGRAL NONLINEARITY vs vs vs FREQUENCY FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 110 0.9 1.8 Crosstalk - db 105 100 95 90 +VA = 5 V DNL - LSB 0.8 0.7 +VA = 5 V +VA = 2.7 INL - LSB 1.7 1.6 +VA = 5 V 85 +VA = 2.7 0.6 1.5 +VA = 2.7 V 80 0 50 100 150 200 F -Frequency - khz 0.5-40 -25-10 5 20 35 50 65 80 TA - Free-Air Temperature - C 1.4-40 -25-10 5 20 35 50 65 80 TA - Free-Air Temperature - C Figure 7. Figure 8. Figure 9. DNL - LSB 2 1.5 1 0.5 0-0.5 DIFFERENTIAL NONLINEARITY INTEGRAL NONLINEARITY DIFFERENTIAL NONLINEARITY vs vs vs EXTERNAL CLOCK FREQUENCY EXTERNAL CLOCK FREQUENCY EXTERNAL CLOCK FREQUENCY +VA = 5 V MAX MIN INL - LSB 2 1.5 1 0.5 0-0.5 +VA = 5 V Max DNL - LSB 2 1.5 1 0.5 0-0.5 +VA = 2.7 V Max Min -1-1.5-2 0 5 10 15 20 External Clock Frequency - MHz -1-1.5-2 Min 0 5 10 15 20 External Clock Frequency - MHz -1-1.5-2 0 5 10 15 20 External Clock Frequency - MHz Figure 10. Figure 11. Figure 12. 14 Submit Documentation Feedback
TYPICAL CHARACTERISTICS (continued) INL - LSB 2 1.5 1 0.5 0-0.5-1 -1.5-2 INTEGRAL NONLINEARITY OFFSET VOLTAGE OFFSET VOLTAGE vs vs vs EXTERNAL CLOCK FREQUENCY FREE-AIR TEMPERATURE SUPPLY VOLTAGE +VA = 2.7 V Max Min 0 5 10 15 20 25 External Clock Frequency - MHz Offset Voltage - mv 1 0.8 0.6 0.4 0.2 +VA = 2.7 +VA = 5 V 0-40 -25-10 5 20 35 50 65 80 T A - Free-Air Temperature - C Offset Voltage - mv 1 0.8 0.6 0.4 0.2 0 2.7 3.2 3.7 4.2 4.7 5.2 +VA - Supply Voltage - V Figure 13. Figure 14. Figure 15. Gain Error - % FSR -0.065-0.068 +VA = 5 V -0.070-0.073 GAIN ERROR GAIN ERROR POWER SUPPLY REJECTION vs vs RATIO FREE-AIR TEMPERATURE SUPPLY VOLTAGE vs SUPPLY RIPPLE FREQUENCY +VA = 2.7-0.075-40 -25-10 5 20 35 50 65 80 T - Free-Air Temperature - C A Offset Voltage Change - mv -0.065-0.068-0.070-0.073-0.075 2.7 3.2 3.7 4.2 4.7 5.2 +VA - Supply Voltage - V PSRR - Power Supply Rejection Ratio - db -80-78 -76-74 -72 +VA = 2.7 V +VA = 5 V -70 0 20 40 60 80 100 Supply Ripple Frequency - khz Figure 16. Figure 17. Figure 18. SNR - Signal-To-Noise Ratio - db 92 90 88 86 SIGNAL-TO-NOISE RATIO SIGNAL-TO-NOISE AND TOTALHARMONIC DISTORTION vs DISTORTION vs INPUT FREQUENCY vs INPUT FREQUENCY INPUT FREQUENCY +VA = 5 V +VA = 2.7 V 84 0 20 40 60 80 100 f i - Input Frequency - khz SINAD - Signal-To-Noise and Distortion - db 92 90 88 86 84 82 80 +VA = 5 V +VA = 2.7 V 0 20 40 60 80 100 f - Input Frequency - khz i THD - Total Harmonic Distortion - db -150-100 -95-90 -85-80 +VA = 5 V +VA = 2.7 V 0 20 40 60 80 100 f - Input Frequency - khz i Figure 19. Figure 20. Figure 21. Submit Documentation Feedback 15
TYPICAL CHARACTERISTICS (continued) SFDR - Spurious Free Dynamic Range - db 110 105 100 SPURIOUS FREE DYNAMIC RANGE SIGNAL-TO-NOISE RATIO SIGNAL-TO-NOISE AND vs vs DISTORTION INPUT FREQUENCY FULL SCALE RANGE vs FULL SCALE RANGE 95 90 85 80 +VA = 5 V +VA = 2.7 V 0 20 40 60 80 f - Input Frequency - khz i 100 SNR - Signal-To-Noise Ratio - db 92 88 84 80 76 72 10 khz Input 2.7 V 5 V 0 1 2 3 4 5 Full Scale Range - V SINAD - Signal-To-Noise and Distortion - db 92 88 84 80 76 72 10 khz Input 2.7 V 5 V 0 1 2 3 4 5 Full Scale Range - V Figure 22. Figure 23. Figure 24. THD - Total Harmonic Distortion -db -100-96 -92-88 TOTAL HARMONIC DISTORTION SPURIOUS FREE DYNAMIC RANGE TOTAL HARMONIC DISTORTION vs vs vs FULL SCALE RANGE FULL SCALE RANGE FREE-AIR TEMPERATURE 10 khz Input 2.7 V 5 V 0 1 2 3 4 5 Full Scale Range - V SFDR - Spurious Free Dynamic Range - db 102 100 98 96 94 92 90 10 KHz 2.7 V 5 V 0 1 2 3 4 5 Full Scale Range - V THD - Total Harmonic Distortion - db -100-98 -96 +VA = 2.7 V, 10 khz Input +VA = 5 V, 100 khz Input -94-40 -25-10 5 20 35 50 65 T A - Free-Air Temperature - C Figure 25. Figure 26. Figure 27. SPURIOUS FREE DYNAMIC RANGE SIGNAL-TO-NOISE RATIO SIGNAL-TO-NOISE AND vs vs DISTORTION FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE vs FREE-AIR TEMPERATURE 80 SFDR - Spurious Free Dynamic Range - db 102 100 98 96 +VA = 2.7 V, 10 khz Input +VA = 5 V, 100 khz Input 94-40 -25-10 5 20 35 50 65 80 T A - Free-Air Temperature - C SNR - Signal-To-Noise Ratio - db 92 91 90 89 88 +VA = 5 V, 100 khz Input +VA = 2.7 V, 10 khz Input 87-40 -25-10 5 20 35 50 65 80 T A - Free-Air Temperature - C SINAD - Signal-To-Noise and Distortion - db 92 91 90 89 88 +VA =5 V, 100 khz Input +VA = 2.7 V, 10 khz Input 87-40 -25-10 5 20 35 50 65 80 T A - Free-Air Temperature - C Figure 28. Figure 29. Figure 30. 16 Submit Documentation Feedback
TYPICAL CHARACTERISTICS (continued) ENOB - Effective Number of Bits - bits 14.9 14.7 14.5 14.3 EFFECTIVE NUMBER OF BITS INTERNAL CLOCK FREQUENCY INTERNAL CLOCK FREQUENCY vs vs vs FREE-AIR TEMPERATURE SUPPLY VOLTAGE FREE-AIR TEMPERATURE +VA = 5 V, 100 khz Input +VA = 2.7 V, 10 khz Input -40-25 -10 5 20 35 50 65 80 T - Free-Air Temperature - C A Internal Clock Frequency - MHz 12 11.8 11.6 11.4 11.2 11.0 2.7 3.2 3.7 4.2 4.7 5.2 5.7 +VA - Supply Voltage - V Internal Clock Frequency - MHz 12 11.8 11.6 11.4 11.2 +VA = 5 V +VA = 2.7 V 11-40 -25-10 5 20 35 50 65 T A - Free-Air Temperature - C Figure 31. Figure 32. Figure 33. ANALOG SUPPLY CURRENT ANALOG SUPPLY CURRENT ANALOG SUPPLY CURRENT vs vs vs SUPPLY VOLTAGE SUPPLY VOLTAGE SUPPLY VOLTAGE 80 5.6 500 ksps 320 NAP Mode 12 PD Mode Analog Supply Current - ma 5.1 4.6 4.1 Analog Supply Current - A 300 280 260 240 220 Analog Supply Current - na 10 8 6 4 2 3.6 2.7 3.2 3.7 4.2 4.7 5.2 +VA - Supply Voltage - V 200 2.7 3.2 3.7 4.2 4.7 5.2 +VA - Supply Voltage - V 0 2.7 3.2 3.7 4.2 4.7 5.2 +VA - Supply Voltage - V Figure 34. Figure 35. Figure 36. Analog Supply Current - ma 6 5 4 3 2 1 ANALOG SUPPLY CURRENT ANALOG SUPPLY CURRENT ANALOG SUPPLY CURRENT vs vs vs SAMPLE RATE SAMPLE RATE FREE-AIR TEMPERATURE Autonap Mode +VA = 5 V +VA = 2.7 V Analog Supply Current - A 400 300 200 100 PD Mode +VA = 5 V +VA = 2.7 V Analog Supply Current - ma 5.5 5 4.5 4 3.5 500 ksps Sample Rate +VA = 5 V +VA = 2.7 V 0 0 100 200 300 400 500 600 Sample Rate - ksps 0 0 5 10 15 20 25 Sample Rate - ksps 3-40 -25-10 5 20 35 50 65 80 T - Free-Air Temperature - C A Figure 37. Figure 38. Figure 39. Submit Documentation Feedback 17
TYPICAL CHARACTERISTICS (continued) ANALOG SUPPLY CURRENT vs FREE-AIR TEMPERATURE Analog Supply Current - ma 0.4 0.3 0.2 0.1 NAP Mode +VA = 5 V +VA = 2.7 0-40 -25-10 5 20 35 50 65 80 T A - Free-Air Temperature - C Figure 40. INL DNL 3 2.5 2 f i = 500 ksps, +VA = 5 V, V ref = 4.096 V 2 1.5 f i = 500 ksps, +VA = 5 V, V ref = 4.096 V 1.5 1 INL - Bits 1 0.5 0-0.5-1 DNL - Bits 0.5 0-0.5-1.5-1 -2-1.5-2.5-3 -2 0 10000 20000 30000 40000 50000 60000 70000 0 10000 20000 30000 40000 50000 60000 70000 Code Code Figure 41. Figure 42. 18 Submit Documentation Feedback
TYPICAL CHARACTERISTICS (continued) INL DNL 3 2.5 2 f i = 500 ksps, +VA = 2.7 V, V ref = 2.5 V 2 1.5 f i = 500 ksps, +VA = 2.7 V, V ref = 2.5 V 1.5 1 INL - Bits 1 0.5 0-0.5-1 DNL - Bits 0.5 0-0.5-1.5-1 -2-2.5-1.5 3 0 10000 20000 30000 40000 50000 60000 70000 Code -2 0 10000 20000 30000 40000 50000 60000 70000 Code Figure 43. Figure 44. FFT FFT 0 0-20 1 khz Input,+VA = 2.7 V, V ref = 2.5 V, f s = 500 ksps -20 10 khz Input,+VA = 2.7 V, V ref = 2.5 V, f s = 500 ksps -40-40 Amplitude - db -60-80 -100 Amplitude - db -60-80 -100-120 -120-140 -140-160 -160 0 50 100 150 200 250 0 50 100 150 200 250 f - Frequency - khz f - Frequency - khz Figure 45. Figure 46. Submit Documentation Feedback 19
TYPICAL CHARACTERISTICS (continued) FFT FFT 0 0-20 -40 100 khz Input, +VA = 2.7 V, V ref = 2.5 V, f s = 500 ksps -20-40 1 khz Input,+VA = 5 V, V ref = 4.096 V, f s = 500 ksps Amplitude - db -60-80 -100 Amplitude - db -60-80 -100-120 -120-140 -140-160 -160 0 50 100 150 200 250 0 50 100 150 200 250 f - Frequency - khz f - Frequency - khz Figure 47. Figure 48. FFT FFT 0 0-20 10 khz Input,+VA = 5 V, V ref = 4.096 V, f s = 500 ksps -20 100 khz Input,+VA = 5 V, V ref = 4.096 V, f s = 500 ksps -40-40 Amplitude - db -60-80 -100 Amplitude - db -60-80 -100-120 -120-140 -140-160 -160 0 50 100 150 200 250 0 50 100 150 200 250 f - Frequency - khz f - Frequency - khz Figure 49. Figure 50. THEORY OF OPERATION The /28 is a high-speed, low power, successive approximation register (SAR) analog-to-digital converter (ADC) that uses an external reference. The architecture is based on charge redistribution, which inherently includes a sample/hold function. The /28 has an internal clock that is used to run the conversion but can also be programmed to run the conversion based on the external serial clock, SCLK. The has one analog input. The analog input is provided to two input pins: +IN and -IN. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both +IN and -IN inputs are disconnected from any internal function. The has two inputs. Both inputs share the same common pin - COM. The negative input is the same as the -IN pin for the. The can be programmed to select a channel manually or can be programmed into the auto channel select mode to sweep between channel 0 and 1 automatically. 20 Submit Documentation Feedback
ANALOG INPUT THEORY OF OPERATION (continued) When the converter enters hold mode, the voltage difference between the +IN and -IN inputs is captured on the internal capacitor array. The voltage on the -IN input is limited between AGND - 0.2 V and AGND + 0.2 V, allowing the input to reject small signals which are common to both the +IN and -IN inputs. The +IN input has a range of -0.2 V to V ref + 0.2 V. The input span (+IN - (-IN)) is limited to 0 V to V ref. The (peak) input current through the analog inputs depends upon a number of factors: sample rate, input voltage, and source impedance. The current into the /28 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (45 pf) to a 16-bit settling level within the minimum acquisition time (238 ns). When the converter goes into hold mode, the input impedance is greater than 1 GΩ. Care must be taken regarding the absolute analog input voltage. To maintain linearity of the converter, the +IN and -IN inputs and the span (+IN - (-IN)) should be within the limits specified. Outside of these ranges, converter linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass filters should be used. Care should be taken to ensure that the output impedance of the sources driving the +IN and -IN inputs are matched. If this is not observed, the two inputs could have different settling times. This may result in an offset error, gain error, and linearity error which change with temperature and input voltage. Device in Hold Mode +IN 150 40 pf 4 pf +VA IN 4 pf AGND 150 40 pf AGND Figure 51. Input Equivalent Circuit Driver Amplifier Choice The analog input to the converter needs to be driven with a low noise, op-amp like the THS4031 or OPA356. An RC filter is recommended at the input pins to low-pass filter the noise from the source. Two resistors of 20Ω and a capacitor of 470 pf is recommended. The input to the converter is a unipolar input voltage in the range 0 V to V ref. The minimum -3dB bandwidth of the driving operational amplifier can be calculated to: f 3db = (ln(2) (n+1))/(2π t ACQ ) where n is equal to 16, the resolution of the ADC (in the case of the /28). When t ACQ = 238 ns (minimum acquisition time), the minimum bandwidth of the driving amplifier is 7.9 MHz. The bandwidth can be relaxed if the acquisition time is increased by the application. The OPA365, OPA827, or THS4031 from Texas Instruments are recommended. The THS4031 used in the source follower configuration to drive the converter is shown in the typical input drive configuration, Figure 52. Bipolar to Unipolar Driver In systems where the input is bipolar, the THS4031 can be used in the inverting configuration with an additional DC bias applied to its + input so as to keep the input to the /28 within its rated operating voltage range. This configuration is also recommended when the /28 is used in signal processing applications where good SNR and THD performance is required. The DC bias can be derived from the REF3225 or the REF3240 reference voltage ICs. The input configuration shown in Figure 53 is capable of delivering better than 91-dB SNR and -96-dB THD at an input frequency of 10 khz. In case bandpass filters are used to filter the input, care should be taken to ensure that the signal swing at the input of the bandpass filter is small so as to keep the Submit Documentation Feedback 21
THEORY OF OPERATION (continued) distortion introduced by the filter minimal. In such cases, the gain of the circuit shown in Figure 53 can be increased to keep the input to the /28 large to keep the SNR of the system high. Note that the gain of the system from the + input to the output of the THS4031 in such a configuration is a function of the gain of the AC signal. A resistor divider can be used to scale the output of the REF3225 or REF3240 to reduce the voltage at the DC input to THS4031 to keep the voltage at the input of the converter within its rated operating range. Input Signal (0 V to 4 V) /28 +VA 5 V THS4031 50 20 470 pf 20 +IN/(+IN1 or +IN0) IN/COM Figure 52. Unipolar Input Drive Configuration 5 V 1 V DC 600 Input Signal ( 2V to 2 V) THS4031 600 20 470 pf 20 +VA +IN/(+IN1 or +IN0) IN/COM Figure 53. Bipolar Input Drive Configuration REFERENCE The /28 can operate with an external reference with a range from 0.3 V to 4.2 V. A clean, low noise, well-decoupled reference voltage on this pin is required to ensure good performance of the converter. A low noise band-gap reference like the REF3240 can be used to drive this pin. A 10-µF ceramic decoupling capacitor is required between the REF+ and REF- pins of the converter. These capacitors should be placed as close as possible to the pins of the device. The REF- should be connected to its own via to the analog ground plane with the shortest possible distance. CONVERTER OPERATION The /28 has an oscillator that is used as an internal clock which controls the conversion rate. The frequency of this clock is 10.5 MHz minimum. The oscillator is always on unless the device is in the deep powerdown state or the device is programmed for using SCLK as the conversion clock (CCLK). The minimum acquisition (sampling) time takes 3 CCLKs (this is equivalent to 238 ns at 12.6 MHz) and the conversion time takes 18 conversion clocks (CCLK) (~1500 ns) to complete one conversion. The conversion can also be programmed to run based on the external serial clock, SCLK, if is so desired. This allows a system designer to achieve system synchronization. The serial clock SCLK, is first reduced to 1/2 of its frequency before it is used as the conversion clock (CCLK). For example, with a 21-MHz SCLK this provides a 10.5-MHz clock for conversions. If it is desired to start a conversion at a specific rising edge of the SCLK when the external SCLK is programmed as the source of the conversion clock (CCLK) (and manual start of conversion 22 Submit Documentation Feedback
THEORY OF OPERATION (continued) is selected), the setup time between CONVST and that rising SCLK edge should be observed. This ensures the conversion is complete in 18 CCLKs (or 36 SCLKs). The minimum setup time is 20 ns to ensure synchronization between CONVST and SCLK. In many cases the conversion can start one SCLK period (or CCLK) later which results in a 19 CCLK (or 37 SCLK) conversion. The 20 ns setup time is not required once synchronization is relaxed. The duty cycle of SCLK is not critical as long as it meets the minimum high and low time requirements of 8 ns. Since the /28 is designed for high-speed applications, a higher serial clock (SCLK) must be supplied to be able to sustain the high throughput with the serial interface and so the clock period of SCLK must be at most 1 µs (when used as conversion clock (CCLK). The minimum clock frequency is also governed by the parasitic leakage of the capacitive digital-to-analog (CDAC) capacitors internal to the /28. CFR_D10 Conversion Clock (CCLK) = 1 OSC = 0 Divider 1/2 SPI Serial Clock (SCLK) Figure 54. Converter Clock Manual Channel Select Mode The conversion cycle starts with selecting an acquisition channel by writing a channel number to the command register (CMR). This cycle time can be as short as 4 serial clocks (SCLK). Auto Channel Select Mode Channel selection can also be done automatically if auto channel select mode is enabled. This is the default channel select mode. The dual channel converter,, has a built-in 2-to-1 MUX. If the device is programmed for auto channel select mode then signals from channel 0 and channel 1 are acquired with a fixed order. Channel 0 is accessed first in the next cycle after the command cycle that configured CFR_D11 to 1 for auto channel select mode. This automatic access stops the cycle after the command cycle that sets CFR_D11 to 0. Start of a Conversion The end of acquisition or sampling instance () is the same as the start of a conversion. This is initiated by bringing the CONVST pin low for a minimum of 40 ns. After the minimum requirement has been met, the CONVST pin can be brought high. CONVST acts independent of FS/CS so it is possible to use one common CONVST for applications requiring simultaneous sample/hold with multiple converters. The /28 switches from sample to hold mode on the falling edge of the CONVST signal. The /28 requires 18 conversion clock (CCLK) edges to complete a conversion. The conversion time is equivalent to 1500 ns with a 12-MHz internal clock. The minimum time between two consecutive CONVST signals is 21 CCLKs. A conversion can also be initiated without using CONVST if it is so programmed (CFR_D9 = 0). When the converter is configured as auto trigger, the next conversion is automatically started 3 conversion clocks (CCLK) after the end of a conversion. These 3 conversion clocks (CCLK) are used as the acquisition time. In this case the time to complete one acquisition and conversion cycle is 21 CCLKs. Submit Documentation Feedback 23
Status Output /INT Power-Down Modes THEORY OF OPERATION (continued) 100 Table 1. Different Types of Conversion MODE SELECT CHANNEL START CONVERSION Auto Channel Select (1) Automatic No need to write channel number to the CMR. Use internal sequencer for the. Manual Write the channel number to the CMR. Manual Channel Select (1) Auto channel select should be used with auto trigger and also with the TAG bit enabled. Auto Trigger Start a conversion based on the conversion clock CCLK. Manual Trigger Start a conversion with CONVST. When the status pin is programmed as and the polarity is set as active low, the pin works in the following manner: The output goes LOW immediately following CONVST going LOW when manual trigger is programmed. stays LOW throughout the conversion process and returns to HIGH when the conversion has ended. The output goes low for 3 conversion clocks (CCLK) after the previous rising edge of, if auto trigger is programmed. This status pin is programmable. It can be used as an output (CFR.D[7:6] = 1, 1) where the low time is equal to the conversion time. This status pin can be used as INT. (CFR.D[7:6] = 1, 0) which is set LOW at the end of a conversion is brought to HIGH (cleared) by the next read cycle. The polarity of this pin, used as either function ( or INT), is programmable through CFR_D7. The /28 has a comprehensive built-in power-down feature. There are three power-down modes: Deep power-down mode, Nap power-down mode, and auto nap power-down mode. All three power-down modes are enabled by setting the related CFR bits. The first two power-down modes are activated when enabled. A wakeup command, 1011b, can resume device operation from a power-down mode. Auto nap power-down mode works slightly different. When the converter is enabled in auto nap power-down mode, an end of conversion instance () puts the device into auto nap powerdown. The beginning of sampling resumes operation of the converter. The contents of the configuration register is not affected by any of the power-down modes. Any ongoing conversion when nap or deep powerdown is activated is aborted. +VA Supply Current A 10 1 0.1 20 10020 20020 30020 40020 Settling Time ns Figure 55. Typical Analog Supply Current Drop vs Time After Powerdown 24 Submit Documentation Feedback
Deep Power-Down Mode Deep power-down mode can be activated by writing to configuration register bit CFR_D2. When the device is in deep power-down mode, all blocks except the interface are in powerdown. The external SCLK is blocked to the analog block. The analog blocks no longer have bias currents and the internal oscillator is turned off. In this mode, power dissipation falls from 5 ma to 1 µa in 2 µs. The wake-up time after a powerdown is 1 µs. When bit D2 in the configuration register is set to 0, the device is in deep powerdown. Setting this bit to 1 or sending a wake-up command can resume the converter from the deep power-down state. Nap Mode In nap mode the /28 turns off biasing of the comparator and the mid-volt buffer. In this mode power dissipation falls from 5 ma in normal mode to about 0.3 ma in 200 ns after the configuration cycle. The wake-up (resume) time from nap power-down mode is 3 CCLKs (238 ns with a 12.6-MHz conversion clock). As soon as the CFR_D3 bit in the control register is set to 0, the device goes into nap power-down mode, regardless of the conversion state. Setting this bit to 1 or sending a wake-up command can resume the converter from the nap power-down state. Auto Nap Mode Auto nap mode is almost identical to nap mode. The only difference is the time when the device is actually powered down and the method to wake up the device. Configuration register bit D4 is only used to enable/disable auto nap mode. If auto nap mode is enabled, the device turns off biasing after the conversion has finished, which means the end of conversion activates auto nap powerdown mode. Power dissipation falls from 12 ma in normal mode to about 0.3 ma in 200 ns. A wake-up command resumes the device and turns biasing on again in 3 CCLKs (238 ns with a 12.6-MHz conversion clock). The device can also be woken up by disabling auto nap mode when bit D4 of the configuration register is set to 1. Any channel select command 0XXXb or the set default mode command 1111b can also wake up the device from auto nap powerdown. TYPE OF POWERDOWN Normal operation NOTE: 1. This wake-up command is the word 1011b in the command word. This command sets bits D2 and D3 to 1 in the configuration register but not D4. But a wake-up command does remove the device from either one of these power-down states, deep/nap/auto nap powerdown. 2. Wake-up time is defined as the time between when the host processor tries to wake up the converter and when a convert start can occur. POWER CONSUMPTION 5 ma/3.8 ma Table 2. Power-Down Mode Comparisons ACTIVATED BY ACTIVATION TIME RESUME POWER BY RESUME TIME ENABLE Deep powerdown 6 na/2 na Setting CFR 100 µs Woken up by command 1011b 1 µs Set CFR Woken up by command 1011b to achieve 6.6 ma Nap powerdown 0.3 ma/0.2 ma Setting CFR 200 µs 3 CCLKs Set CFR since (1.3 + 12)/2 = 6.6 Woken up by CONVST, any channel select (end of Auto nap powerdown 200 µs command, default command 1111b, or wake up 3 CCLKs Set CFR conversion) command 1011b. Submit Documentation Feedback 25
CONVST N Converter N+1 State Converter State N th Conversion N+1 th Sampling N+1 th Conversion Read While Converting 20 ns MIN 1 CCLK MIN CS (For Read Result) Read N 1 th Result Read While Sampling 0 ns MIN 20 ns MIN CS (For Read Result) Read N th Result Figure 56. Read While Converting vs Read While Sampling (Manual trigger) Manual Trigger CONVST N N+1 Converter State Resume N th Sampling >=3CCLK N th Conversion =18 CCLK Activation Resume N+1 th Sampling N+1 th Conversion Activation >=3CCLK =18 CCLK 20 ns MIN Read While Converting CS 1 CCLK MIN Read N 1 th Result 20 ns MIN Read N th Result Read While Sampling CS 20 ns MIN Read N 1 th Result 20 ns MIN 0 ns MIN Read N th Result 20 ns MIN 20 ns MIN 20 ns MIN 20 ns MIN Figure 57. Read While Converting vs Read While Sampling with Deep or Nap Powerdown 26 Submit Documentation Feedback
Manual Trigger Case 1 40 ns MIN CONVST (programmed Active Low) N N+1 Converter State Resume N th Sampling >=3CCLK N th Conversion =18 CCLK POWERDOWN Resume N+1 th Sampling >=3CCLK N+1 th Conversion =18 CCLK POWERDOWN 6 CCLKs 6 CCLKs Read While Converting 20 ns MIN 20 ns MIN CS Read N 1 th Result Read N th Result 20 ns MIN 20 ns MIN Read While Sampling 1 CCLK MIN 0 ns MIN 1 CCLK MIN CS Read N 1 th Result Read N th Result 20 ns MIN 20 ns MIN Manual Trigger Case 2 (wake up by CONVST) 40 ns MIN CONVST N N+1 (programmed Active Low) Converter State Resume N th Sampling >=3CCLK N th Conversion =18 CCLK POWER DOWN Resume N+1 th Sampling >=3CCLK N+1 th Conversion =18 CCLK POWER DOWN Read While Converting 20 ns MIN 20 ns MIN CS Read N 1 th Result Read N th Result Read While Sampling 20 ns MIN 20 ns MIN 0 ns MIN 20 ns MIN 20 ns MIN CS Read N 1 th Result Read N th Result 20 ns MIN 20 ns MIN Figure 58. Read While Converting vs Read While Sampling with Auto Nap Powerdown Total Acquisition + Conversion Cycle Time: Automatic: = 21 CCLKs Manual: 21 CCLKs Manual + deep powerdown: 4SCLK + 100 µs + 3 CCLK + 18 CCLK +16 SCLK + 1 µs Manual + nap powerdown: 4 SCLK + 3 CCLK + 3 CCLK + 18 CCLK +16 SCLK Manual + auto nap 4 SCLK + 3 CCLK + 3 CCLK + 18 CCLK +16 SCLK (use wakeup to resume) powerdown: Manual + auto nap 1 CCLK + 3 CCLK + 3 CCLK + 18 CCLK +16 SCLK (use CONVST to resume) powerdown: Submit Documentation Feedback 27
DIGITAL INTERFACE The serial interface is compatible with Motorola SPI. The serial clock is designed to accommodate the latest high-speed processors with an SCLK up to 50 MHz. Each cycle is started with the falling edge of FS/CS. The internal data register content which is made available to the output register at the is presented on the SDO output pin at the falling edge of FS/CS. This is the MSB. Output data are changed at the falling edge of SCLK so that the host processor can read it at the next rising edge. Serial data input is latched at the falling edge of SCLK. The complete serial I/O cycle starts with the first rising edge of SCLK after the falling edge of FS/CS and ends 16 (see NOTE) falling edges of SCLK later. The serial interface is very flexible. It works with both CPOL = 0 or CPOL = 1. The interface ignores data if a falling edge arrives before the first rising edge. This means the falling edge of FS/CS may fall while SCLK is high. The same relaxation applies to the rising edge of FS/CS where SCLK may be high or low as long as the last SCLK falling edge happens before the rising edge of FS/CS. Internal Register WRITING TO THE CONVERTER NOTE: There are cases where a cycle is 4 SCLKs or up to 24 SCLKs depending on the read mode combination. See Table 3 for details. The internal register consists of two parts, 4 bits for the command register (CMR) and 12 bits for configuration data register (CFR). Table 3. Command Set Defined by Command Register (CMR) (1) WAKE UP FROM MINIMUM SCLKs D[15:12] HEX COMMAND D[11:0] R/W AUTO NAP REQUIRED 0000b 0h Select analog input channel 0 (2) Don't care Y 4 0001b 1h Select analog input channel 1 (2) Don't care Y 4 0010b 2h Reserved Reserved Y 4 0011b 3h Reserved Reserved Y 4 0100b 4h Reserved Reserved Y 4 0101b 5h Reserved Reserved Y 4 0110b 6h Reserved Reserved Y 4 0111b 7h Reserved Reserved Y 4 1000b 8h Reserved Reserved 1001b 9h Reserved Reserved 1010b Ah Reserved Reserved 1011b Bh Wake up Don't care Y 4 W 1100b Ch Read CFR Don't care 16 R 1101b Dh Read data Don't care 16 R 1110 Eh Write CFR CFR Value 16 W 1111b Fh Default mode (load CFR with default value) Don't care Y 4 W (1) When SDO is not in 3-state (FS/CS low and SCLK running), the bits from SDO are always part (depending on how many SCLKs are supplied) of the previous conversion result. (2) These two commands apply to the only. There are two different types of writes to the register, a 4-bit write to the CMR and a full 16-bit write to the CMR plus CFR. The command set is listed in Table 3. A simple command requires only 4 SCLKs and the write takes effect at the 4th falling edge of SCLK. A 16-bit write or read takes at least 16 SCLKs (see Table 5 for exceptions that require more than 16 SCLKs). 28 Submit Documentation Feedback
Configuring the Converter and Default Mode READING THE CONFIGURATION REGISTER The converter can be configuring with command 1110b (write to the CFR) or command 1111b (default mode). A write to the CFR requires a 4-bit command followed by 12-bits of data. A 4-bit command takes effect at the 4th falling edge of SCLK. A CFR write takes effect at the 16th falling edge of SCLK. A default mode command can be achieved by simply tying SDI to +VBD. As soon as the chip is selected at least four 1s are clocked in by SCLK. The default value of the CFR is loaded into the CFR at the 4th falling edge of SCLK. CFR default values are all 1s (except for CFR_D1, this bit is ignored by the and is always read as a 0). The same default values apply for the CFR after a power-on reset (POR) and SW reset. The host processor can read back the value programmed in the CFR by issuing command 1100b. The timing is similar to reading a conversion result except CONVST is not used and there is no activity on the /INT pin. The CFR value read back contains the first four MSBs of conversion data plus valid 12-bit CFR contents. SDI BIT CFR - D[11-0] Channel select mode Table 4. Configuration Register (CFR) Map DEFINITION D11 Default = 1 0: Manual channel select enabled. Use channel select commands to 1: Auto channel select enabled. All channels are sampled and access a different channel. converted sequentially until the cycle after this bit is set to 0. D10 Default = 1 D9 Default = 1 Conversion clock (CCLK) source select 0: Conversion clock (CCLK) = SCLK/2 1: Conversion clock (CCLK) = Internal OSC Trigger (conversion start) select: start conversion at the end of sampling (). If D9 = 0, the D4 setting is ignored. 0: Auto trigger automatically starts (4 internal clocks after inactive) 1: Manual trigger manually started by falling edge of CONVST D8 Default = 1 Don't care Don't care D7 Default = 1 D6 Default = 1 D5 Default = 1 D4 Default = 1 D3 Default = 1 D2 Default = 1 Pin 10 polarity select when used as an output (/INT) 0: Active high / INT active high 1: Active low / INT active low Pin 10 function select when used as an output (/INT) 0: Pin used as INT 1: Pin used as Pin 10 I/O select for chain mode operation 0: Pin 10 is used as CDI input (chain mode enabled) 1: Pin 10 is used as /INT output Auto nap powerdown enable/disable (mid voltage and comparator shut down between cycles). This bit setting is ignored if D9 = 0. 0: Auto nap powerdown enabled (not activated) 1: Auto nap powerdown disabled Nap powerdown (mid voltage and comparator shut down between cycles). This bit is set to 1 automatically by wake-up command. 0: Enable/activate device in nap powerdown 1: Remove device from nap powerdown (resume) Deep powerdown. This bit is set to 1 automatically by wake-up command. 0: Enable/activate device in deep powerdown 1: Remove device from deep powerdown (resume) D1 Default = TAG bit enable. This bit is ignored by the and is alway read 0. 0: 1: 0: TAG bit disabled. 1: TAG bit output enabled. TAG bit appears at the 17th SCLK. D0 Default = 1 Reset 0: System reset 1: Normal operation READING CONVERSION RESULT The conversion result is available to the input of the output data register (ODR) at and presented to the output of the output register at the next falling edge of CS or FS. The host processor can then shift the data out via the SDO pin any time except during the quiet zone. This is 20 ns before and 20 ns after the end of sampling () period. End of sampling () is defined as the falling edge of CONVST when manual trigger is used or the end of the 3rd conversion clock (CCLK) after if auto trigger is used. Submit Documentation Feedback 29