DS1870 rev1 DS.C

Transcription

1 Rev 1; 5/4 AB LDMOS ( ) (LUT)256 A/D(ADC) LDMOS RF 13 ADCV CC V D I D1 I D2 ADC Hi/Lo 32 I 2 C TM 8 5V 16 TSSOP -4 C +95 C I 2 C Philips Corp. Maxim Integrated Products, Inc. I 2 C Philips I 2 C Philips I 2 C PART TEMP RANGE PIN-PACKAGE E-1-4 C to +95 C 16 TSSOP (173 mil) TOP VIEW 1 L 1 V CC 16 2 W 1 H COM 15 3 W 2 SDA 14 4 L 2 SCL 13 5 I D1 A I D2 A V D A 1 8 GND FAULT 9 TSSOP (173 mil) Maxim Integrated Products 1 Maxim Maxim Maxim Maxim

2 LDMOS RF ABSOLUTE MAXIMUM RATINGS Voltage Range on V CC, H COM, SDA, and SCL Pins Relative to Ground...-.5V to +6.V Voltage Range on A, A 1, A 2, FAULT, V D, I D1, I D2 Relative to Ground V to V CC +.5V, not to exceed +6.V Voltage Range on L, L1, W, and W1 Relative to Ground...-.5V to H COM +.5V, not to exceed +6.V Operating Temperature Range...-4 C to +95 C EEPROM Programming Temperature Range... C to +7 C Storage Temperature Range C to +125 C Soldering Temperature...See IPC/JEDEC J-STD-2A Specification Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (T A = -4 C to +95 C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage V CC (Note 1) V Input Logic 1 (SDA, SCL, A 2, A 1, A ) Input Logic (SDA, SCL, A 2, A 1, A ) V IH V IL x V CC + V CC.3 H COM Voltage V L X and W X Voltage -.3 Wiper Current ma +.3 x V CC H COM +.3 V V V DC ELECTRICAL CHARACTERISTICS (V CC = +4.5 to 5.5V, T A = -4 C to +95 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Current I CC (Note 2) 1 2 ma Input Leakage I LI na Low-Level Output Voltage V OL1 3mA sink current.4 V (SDA, FAULT) V OL2 6mA sink current.6 V I/O Capacitance C I/O 1 pf Digital Power-On Reset V POD V Analog Power-On Reset V POA V 2

3 LDMOS RF ANALOG VOLTAGE-MONITORING CHARACTERISTICS (V CC = +4.5 to 5.5V, T A = -4 C to +95 C.) V D Monitor Factory- Calibrated FS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS V CC Monitor Factory- Calibrated FS Code FFF8h V Code FFF8h V I D1 and I D2 Monitor Factory- Calibrated FS Resolution (V CC, V D, I D1, I D2 ) Accuracy (V CC, V D, I D1, I D2 ) Code FFF8h V.122 %FS.25.5 %FS Update Rate for V CC, V D, I D1, I D2 t frame 5 ms DIGITAL THERMOMETER CHARACTERISTICS (V CC = +4.5 to 5.5V, T A = -4 C to +95 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Thermometer Error T ERR -4 C to 95 C C Update Rate t frame 5 ms ANALOG POTENTIOMETER CHARACTERISTICS (V CC = +4.5 to 5.5V, T A = -4 C to +95 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Wiper Resistance +25 C 5 1 Ω Potentiometer End-to-End Resistance R POT +25 C kω Resolution.4 %FS Absolute Linearity (Note 3) LSB Relative Linearity (Note 4) LSB Ratiometric Temperature Coefficient 5 ppm/ C End-to-End Temperature Coefficient 7 ppm/ C -3dB Cutoff Frequency (Note 5) 1 MHz Series Resistors from L1, L2 to GND R S +25 C kω V HCOM /V LX

4 LDMOS RF LOOKUP TABLE CHARACTERISTICS (V CC = +4.5 to 5.5V, T A = -4 C to +95 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POT1 and POT2 Temp LUT Size 72 POT1 and POT2 Temp LUT Index Range Bytes each C Temp Step 2 C Temp Hysteresis (Note 6) 1 C POT1 and POT2 Drain LUT Size 64 Bytes each POT1 and POT2 Drain LUT V D Index Range POT1 and POT2 Drain LUT V D Step POT1 and POT2 Drain LUT V D Hysteresis POT1 and POT2 Drain LUT I DX Index Range POT1 and POT2 Drain LUT I DX Step POT1 and POT2 Drain LUT I DX Hysteresis 8 FE Hex 2 Hex (Note 6) 1 Hex 7E Hex 2 Hex (Note 6) 1 Hex 4

5 LDMOS RF AC ELECTRICAL CHARACTERISTICS (V CC = +4.5V to 5.5V, T A = -4 C to +95 C, timing referenced to V IL(MAX) and V IH(MIN).) (Figure 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCL Clock Frequency f SCL (Note 7) 4 khz Bus Free Time Between Stop and Start Conditions t BUF 1.3 µs Hold Time (Repeated) Start Condition t HD:STA.6 µs Low Period of SCL t LOW 1.3 µs High Period of SCL t HIGH.6 µs Data Hold Time t HD:DAT.9 µs Data Setup Time t SU:DAT 1 ns Start Setup Time t SU:STA.6 µs SDA and SCL Rise Time t R (Note 8) 2 +.1C B 3 ns SDA and SCL Fall Time t F (Note 8) 2 +.1C B 3 ns Stop Setup Time t SU:STO.6 µs SDA and SCL Capacitive Loading C B (Note 8) 4 pf EEPROM Write Time t W (Note 9) 1 2 ms NONVOLATILE MEMORY CHARACTERISTICS (V CC = +4.5V to 5.5V, T A = C to +7 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Writes +7 C (Note 5) 5, Note 1: All voltages referenced to ground. Note 2: Supply current is measured with all logic inputs at their inactive state (SDA = SCL = V CC ) and driven to well-defined logic levels. All outputs are disconnected. Note 3: Absolute linearity is the difference of measured value from expected value at the DAC position. Expected value is a straight line from measured minimum position to measured maximum position. Note 4: Relative linearity is the deviation of an LSB DAC setting change vs. the expected LSB change. Expected LSB change is the slope of the straight line from measured minimum position to measured maximum position. Note 5: This parameter is guaranteed by design. Note 6: See Figure 1. Note 7: I 2 C interface timing shown is for fast-mode (4kHz) operation. This device is also backward compatible with I 2 C standard-mode timing. Note 8: C B total capacitance of one bus line in picofarads. Note 9: EEPROM write begins after a stop condition occurs. 5

6 LDMOS RF (V CC = +5.V, T A = +25 C, unless otherwise noted.) SUPPLY CURRENT (ma) SUPPLY CURRENT vs. SUPPLY VOLTAGE toc1 SUPPLY CURRENT (ma) SUPPLY CURRENT vs. TEMPERATURE V CC = 5.5V V CC = 5.V 6 55 V CC = 4.5V SUPPLY VOLTAGE (V) TEMPERATURE ( C) H COM VOLTAGE (V) toc2 HCOM CURRENT (ma) H COM CURRENT vs. H COM VOLTAGE toc3 WIPER VOLTAGE (V) POTENTIOMETER 1 AND 2 OUTPUT VOLTAGE vs. POSITON H COM = 5V L1 AND L2 NOT CONNECTED toc4 DIFFERENTIAL NONLINEARITY (LSB) POTENTIOMETER 1 DIFFERENTIAL NONLINEARITY vs. WIPER POSITION toc5 DIFFERENTIAL NONLINEARITY (LSB) POTENTIOMETER 2 DIFFERENTIAL NONLINEARITY vs. WIPER POSITION toc WIPER POSITION (DEC) WIPER POSITION (DEC) WIPER POSITION (DEC) INTEGRAL NONLINEARITY (LSB) POTENTIOMETER 1 INTEGRAL NONLINEARITY vs. WIPER POSITION toc7 INTEGRAL NONLINEARITY (LSB) POTENTIOMETER 2 INTEGRAL NONLINEARITY vs. WIPER POSITION toc8 WIPER RESISTANCE (Ω) POTENTIOMETER 1 AND 2 WIPER RESISTANCE vs. WIPER VOLTAGE H COM = 5.V toc WIPER POSITION (DEC) WIPER POSITION (DEC) WIPER VOLTAGE (V) 6

7 LDMOS RF ( ) (V CC = +5.V, T A = +25 C, unless otherwise noted.) WIPER RESISTANCE (Ω) POTENTIOMETER 1 AND 2 WIPER RESISTANCE vs. WIPER VOLTAGE H COM = 5.V WIPER VOLTAGE (V) toc9 RESISTANCE CHANGE FROM 25 C (PPM/C) POTENTIOMETER 1 AND 2 WIPER RESISTANCE vs. TEMPERATURE H 1 COM = 5V WIPER VOLTAGE = 4V TEMPERATURE ( C) toc1 CHANGE FROM RESISTANCE AT 25 C (PPM/C) POTENTIOMETER END-TO-END RESISTANCE vs. TEMPERATURE R POT2 + R S2 R POT1 + R S TEMPERATURE ( C) toc11 OUTPUT DRIFT (PPM/C) POTENTIOMETER LOW TERMINAL VOLTAGE vs. TEMPERATURE L L2-15 H COM = 5.V toc12 ERROR (% FS) V CC CONVERSION ERROR vs. SUPPLY VOLTAGE DEFAULT V CC CALIBRATION toc13 ERROR (% FS) VD CONVERSION ERROR vs. INPUT VOLTAGE DEFAULT VD CALIBRATION toc TEMPERATURE ( C) SUPPLY VOLTAGE (V) INPUT VOLTAGE (V) ID1 CONVERSION ERROR vs. INPUT VOLTAGE toc ID2 CONVERSION ERROR vs. INPUT VOLTAGE toc ERROR (% FS) ERROR (% FS) DEFAULT ID1 CALIBRATION DEFAULT ID2 CALIBRATION INPUT VOLTAGE (V) INPUT VOLTAGE (V) 7

8 LDMOS RF 1 L W W L I D1 1 6 I D2 2 7 V D 8 GND 9 FAULT 1 A 11 A 1 12 A 2 13 SCL 14 SDA 15 H COM 16 V CC I 2 C11A 2 A 1 A I 2 C / I 2 C 1 2 8

9 LDMOS RF V CC SDA SCL A A 1 A 2 V CC I 2 C INTERFACE CONTROL ADDRESS GENERATION 32 BYTES USER MEMORY OFFSET CALIBRATION REGISTERS BIT ADC GAIN CALIBRATION REGISTERS MUX ON-CHIP TEMP SENSOR V CC V D I D1 I D2 I 2 C DATA BUS V D I D1 V D I D2 LOAD INDEX POT1 DRAIN LUT TABLE 4 (64 BYTES) TEMP VD1 INDEX POT2 DRAIN LUT TABLE 5 (64 BYTES) VD2 HI AND LO LIMITS FOR TEMP, V CC, V D, I D1, I D2 MEASURED VALUES FOR TEMP, V CC, V D, I D, I D1 LIMIT COMPARATOR LIMIT FLAG REGISTERS FAULT MASK FAULT LOAD INDEX POT1 TEMP LUT TABLE 2 (72 BYTES) INDEX POT2 TEMP LUT TABLE 3 (72 BYTES) + + POT2 R POT H COM W 2 L 2 R S GND + + R S POT1 R POT W 1 L 1 9

10 LDMOS RF 1. SIGNAL +FS SIGNAL +FS (hex) -FS SIGNAL -FS (hex) V CC 6.553V FFF8 V V D 2.5V FFF8 V I D1.5V FFF8 V I D2.5V FFF8 V LDMOS AB AB (W1 W2) LDMOS 13 ADCV CC FAULT ADC I 2 C 2. SIGNAL LSB WEIGHT (µv) REGISTER VALUE (hex) INPUT VOLTAGE (V) V CC V CC 1. CF V D C V D I D I D h-69h ADC ADC t frame 1 16 LSB 65, LSB V CC V CC C347h? V CC LSB (6.553V - V) / 65,528 = 1.µV C347h 1 49,99149,99 x 1.µV = 4.999V 2 ADC 1 +FS -FS / / 13 ADC (V CC V D I D1 I D2 )16 1

11 LDMOS RF 3. SIGNAL +FS SIGNAL +FS (hex) -FS SIGNAL -FS (hex) Temp C 7FF C h 61h t frame H COM H COM 5V3 5V H COM L X L X GND 4. MSB (bin) LSB (bin) TEMPERATURE ( C) LUT LUT ADDRESS (hex) CORRESPONDING TEMPERATURE ( C) 8-4 C C C C6 C7 / LUT LUTPOT1 LUT ( 2) POT1 / LUT 4 1 POT2 LUT ( 3) POT2 / LUT C +12 C 11

12 LDMOS RF MEMORY LOCATION 9Ah 99h 98h 97h 96h DECREASING TEMPERATURE INCREASING TEMPERATURE MEMORY LOCATION 9Ah 99h 98h 97h 96h DECREASING DRAIN VOLTAGE INCREASING DRAIN VOLTAGE MEMORY LOCATION 9Ah 99h 98h 97h 96h DECREASING DRAIN CURRENT INCREASING DRAIN CURRENT 95h 95h 95h TEMPERATURE ( C) AA ACAEOO B B2 B4 DRAIN VOLTAGE CONVERSION (HEX) 2A 2C 2E DRAIN CURRENT CONVERSION (HEX) 1. LUT (LUT2 LUT3) 72-4 C +12 C 2 C -4 C+12 C -4 C +12 C ( 255) LUT 1 C( 1) LUT, 5 / LUT4 LUT564 VD1 V D I D1 POT1 LUT VD2 V D I D2 POT2 LUT VD1 VD21 85h8 ( )LUT 6. V D I DX LUT LUT ADDRESS (hex) V D VALUE (hex) I DX VALUE (hex) BE FC 7C BF FE 7E LUT V D I DX 6 V D I DX 1h ( 1) LUT LUT 16 ADC B/O_en Index_en LUT 1 Man DAC AFh (V CC V D I D1 I D2 ) ( 1 ) () (FS) 1 (FFF8h)FS 1 LSB 12

13 LDMOS RF FS65,528 (FFF8h)LSB 5µV FS 65,528 x 5µV = V FS 9 LSB 9% /* Assume that the null input is.5v */ /* Assume that the requirement for the LSB is 5µV */ FS = * 5e-6; /*3.2764V */ CNT1 =.5 / 5e-6; /* 1 */ CNT2 =.9 X FS / 5e-6; /* */ /* So the null input is.5v and 9% of FS is 2.949V */ Set the input s offset register to zero gain_result = h; /* Working register for gain calculation */ CLAMP = FFF8h; /* This is the max ADC value*/ For n = 15 down to begin gain_result = gain_result + 2 n ; Write gain_result to the input s gain register; Force the 9% FS input (2.949V); Meas2= ADC result from ; If Meas2 CLAMP Then gain_result = gain_result - 2 n ; Else Force the null input (.5V) Meas1 = ADC result from If [(Meas2-Meas1)>(CNT2-CNT1)] Then gain_result = gain_result - 2 n ; end; Write gain_result to the input s gain register; (.5V) Vh (.5V) (Meas1) Meas Offset = LUT h(t ref ) (T ) ( ( )) TempOffset = Tref T XORbitwise BB4h V CC (V POD ) I 2 C EEPROM / ( )V CC (V POA ) V CC V POA 74hRdyb1 ADC V CC V POA Rdyb 1 V POA EEPROM V CC V POD V CC Lo 1 V CC ADC V CC < V POA FAULT 13

14 LDMOS RF ( h 7Fh) ( 2) (7Fh) (8h FFh) EE ( 78h) EEPROM 1 FFFFhPWE FFFFh PWE h EEPROM 2h 3Fh 1 8h A7h SRAM EEPROM(SEE = ) EEPROMSEE = 1SRAM EEPROM EEPROMSEE = 1 EEPROM SEE = EEPROM EEPROM SEE 1 AFh 8 4 (2 ) ( 1) ( 1) / (2 X ) S2 / MAIN MEMORY h 8h 7Fh USER MEMORY; HI/LO ALARM CONFIGURATION THRESHOLDS; ADC RESULTS; CONFIGURATION AFh SEL TABLE-SELECT BYTE (7Fh) TABLE 1 TABLE 2 TABLE 3 TABLE 4 TABLE 5 8h 8h 8h 8h C7h POT1 TEMP LUT SEL C7h POT2 TEMP LUT SEL BFh POT1 DRAIN LUT SEL BFh POT2 DRAIN LUT SEL 2. 14

15 LDMOS RF ROW (HEX) LOWER MEMORY ROW WORD WORD 1 WORD 2 WORD 3 NAME BYTE BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 BYTE 7 User Row User EE User EE User EE User EE User EE User EE User EE User EE 8 User Row1 User EE User EE User EE User EE User EE User EE User EE User EE 1 User Row2 User EE User EE User EE User EE User EE User EE User EE User EE 18 User Row3 User EE User EE User EE User EE User EE User EE User EE User EE 2 Threshold Temp Hi Alarm V CC Hi Alarm VD Hi Alarm ID1 Hi Alarm 28 Threshold1 ID2 Hi Alarm Reserved Reserved Reserved 3 Threshold2 Temp Lo Alarm V CC Lo Alarm VD Lo Alarm ID1 Lo Alarm 38 Threshold3 ID2 Lo Alarm Reserved Reserved Reserved 4 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 48 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 5 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 58 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 6 A2D Value Temp Value V CC Value VD Value ID1 Value 68 A2D Value1 ID2 Value Reserved Reserved Reserved 7 Status Hi Alarm Lo Alarm Reserved Reserved I/O Status A2D Status Reserved Reserved 78 Table Select PWE Reserved Reserved Reserved Reserved Reserved Tbl Sel BYTE (HEX) EXPANDED BYTES BYTE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT NAME BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 1 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT -1F User EE EE EE EE EE EE EE EE EE 2 Temp Hi Alrm S V CC Hi Alrm VD Hi Alrm ID1 Hi Alrm ID2 Hi Alrm Temp Lo Alrm S V CC Lo Alrm VD Lo Alrm ID1 Lo Alrm ID2 Lo Alrm Temp Value S V CC Value VD Value ID1 Value ID2 Value Hi Alarm Temp Hi V CC Hi VD Hi ID1 Hi ID2 Hi Reserved Reserved Reserved 71 Lo Alarm Temp Lo V CC Lo VD Lo ID1 Lo ID2 Lo Reserved Reserved Reserved 74 I/O Status Reserved Reserved Reserved Reserved Fault Mint Reserved Rdyb 75 A2D Status Temp Rdy V CC Rdy VD Rdy ID1 Rdy ID2 Rdy Reserved Reserved Reserved 78 PWE F Tbl Sel

16 LDMOS RF ROW (HEX) TABLE 1 ( CONFIGURATION ) ROW WORD WORD 1 WORD 2 WORD 3 NAME BYTE BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 BYTE 7 8 Config Password LUT Sel Fault Ena Reserved 88 Scale Reserved Vcc Scale VD Scale ID1 Scale 9 Scale 1 ID2 Scale Reserved Reserved Reserved 98 Offset Reserved Vcc Offset VD Offset ID1 offset A Offset1 ID2 Offset Reserved Reserved Temp Offset A8 BYTE (HEX) LUT Index T Index O1 Index O2 Index POT1 base POT1 off EXPANDED BYTES POT2 base POT2 off Man Dac BYTE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT NAME BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 1 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 8 Password LUT Sel Reserved Reserved Reserved Reserved Reserved Reserved VD2 VD1 86 Fault Ena Temp Ena Vcc Ena VD Ena ID1 Ena ID2 Ena Reserved Reserved Reserved 8A Vcc C VD Scale E ID1 Scale ID2 Scale A Vcc Offset S S C VD Offset S S E ID1 S S A ID2 S S A6 Temp Offset S A8 T Index A9 O1 Index AA O2 Index AB POT1 base AC POT1 off S AD POT2 base AE POT2 off S AF Man DAC Reserved Reserved Reserved Reserved Reserved SEE B/O_en index_en 16

17 LDMOS RF ROW (HEX) TABLE 2 (POT1 TEMP LUT) ROW WORD WORD 1 WORD 2 WORD 3 NAME BYTE BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 BYTE 7 8 LUT POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 88 LUT POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 9 LUT POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 98 LUT POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 A LUT POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 A8 LUT POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 B LUT POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 B8 LUT POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 C LUT POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 C8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved D Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved D8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved E Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved E8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved F Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved F8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved BYTE (HEX) BYTE NAME EXPANDED BYTES BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 8-C7 POT

18 LDMOS RF TABLE 3 ( POT2 TEMP LUT) ROW ROW WORD WORD 1 WORD 2 WORD 3 (HEX) NAME BYTE BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 BYTE 7 8 LUT POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 88 LUT POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 9 LUT POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 98 LUT POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 A LUT POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 A8 LUT POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 B LUT POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 B8 LUT POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 C LUT POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 C8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved D Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved D8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved E Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved E8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved F Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved F8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved BYTE (HEX) BYTE NAME EXPANDED BYTES BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 8-C7 POT

19 LDMOS RF ROW (HEX) TABLE 4 ( POT1 DRAIN LUT) ROW WORD WORD 1 WORD 2 WORD 3 NAME BYTE BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 BYTE 7 8 LUT POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off 88 LUT POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off 9 LUT POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off 98 LUT POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off A LUT POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off A8 LUT POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off B LUT POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off B8 LUT POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off POT1 Off BYTE (HEX) BYTE NAME EXPANDED BYTES BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 8-BF POT1 Off S TABLE 5 (POT2 DRAIN LUT) ROW ROW WORD WORD 1 WORD 2 WORD 3 (HEX) NAME BYTE BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 BYTE 7 8 LUT POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off 88 LUT POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off 9 LUT POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off 98 LUT POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off A LUT POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off A8 LUT POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off B LUT POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off B8 LUT POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off POT2 Off BYTE (HEX) BYTE NAME EXPANDED BYTES BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 8-BF POT2 Off S

20 LDMOS RF < > <> < / > a) X X b) Y Y / (R)(W) (R/W) (V) (NV)NA EEPROM Dalls Semiconductor User EE <R/W><NV><h> NV EEPROM Threshold Temp Hi Alarm V CC Hi Alarm VD Hi Alarm ID1 Hi Alarm Threshold 1 ID2 Hi Alarm Threshold 2 Temp Lo Alarm V CC Lo Alarm VD Lo Alarm ID1 Lo Alarm Threshold 3 ID2 Lo Alarm <R/W><NV><h> <R/W><NV><h> V CC <R/W><NV><h> V D <R/W><NV><h> I D1 <R/W><NV><h> I D2 <R/W><NV><h> <R/W><NV><h> V CC <R/W><NV><h> V D <R/W><NV><h> I D1 <R/W><NV><h> I D2 2

21 LDMOS RF A2D Value Temp Value <R><NA><h> V CC Value <R><NA><h> V CC VD Value <R><NA><h> V D ID1 Value <R><NA><h> I D1 A2D Value 1 ID2 Value <R><NA><h> I D2 Status Hi Alarm <R><NA><h> a) Temp Hi b) V CC Hi V CC c) VD Hi V D d) ID1 Hi I D1 e) ID2 Hi I D2 Lo Alarm <R><NA><4h> a) Temp Lo b) V CC Lo V CC V CC POR V CC c) VD Lo V D d) ID1 Lo I D1 e) ID2 Lo I D2 I/O Status <R><NA>< > FAULT a) FAULT FAULT FAULT b) Mint FAULTFAULT FAULT Fault Ena RDBY 1 c) Rdyb Ready(V POA ) V POA I 2 C1 A2D Status <R/W><V><h> a) Temp Rdy b) V CC Rdy V CC c) VD Rdy V D d) ID1 Rdy I D1 e) ID2 Rdy I D2 21

22 LDMOS RF PWE PWE TBL Sel 1 ( ) <W><V><FFFFh> 78h 7Fh PWE Table_Select PWE <R/W><V><h> 5 (1 5)(1 5) Config Password <R/W><NV><FFFFh> PWE PWE EEPROM LUT Sel <R/W><NV> <3h> a) VD2 1V D POT2 ( 5)LUT I D2 b) VD1 1V D POT1 ( 4)LUT I D1 Fault Ena <R/W><NV> <h> FAULT a) Temp Ena FAULT b) Vcc Ena V CC FAULT c) VD Ena V D FAULT d) ID1 Ena I D1 FAULT e) ID2 Ena I D2 FAULT Scale V CC Scale <R/W><NV><XXXX> V CC V CC V FS VD Scale ID1 Scale <R/W><NV><XXXX> V D V D 2.5V FS <R/W><NV><XXXX> I D1 I D1.5V FS Scale 1 ID2 Scale <R/W><NV><XXXX> I D2 I D2.5V FS Offset V CC Offset <R/W><NV><h> V CC VD Offset ID1 Offset <R/W><NV><h> V D <R/W><NV><h> I D1 Offset 1 ID2 Offset Temp Offset LUT Index <R/W><NV><h> I D2 <R/W><NV><h> 22

23 LDMOS RF T Index O1 Index <R><NA><h> LUT2 3 <R><NA><h> V D I D1 ( LUT Sel ) LUT4 O2 Index <R><NA><h> V D I D2 ( LUT Sel ) LUT5 POT1 base <R><NA><h> POT1 T Index 2 I D2 POT1 POT1 POT2 POT1 off <R><NA><h> POT1 O1 Index 4V D I D1 LUT Sel I D2 POT1 POT1 POT2 POT2 base <R><NA><h> POT2 T Index 3 I D2 POT2 POT1 POT2 POT2 off <R><NA><h> POT1 O2 Index 5V D I D2 LUT Sel I D2 POT2 POT1 POT2 MAN Dac <R/W><NA><3h>LUT a) SEE EE EE EE 1 NVEEEE SRAMEE EE2h 3Fh 18h A7h b) B/O_en LUT POT LUT POT POT ( POT1 Base POT1 Off POT2 Base POT2 Off ) I 2 C c) Index_en LUT ( T Index O1 Index O2 Index ) LUT ( )LUT I D2 ( ) 23

24 LDMOS RF 2 (POT1LUT) 8h-C7h POT1 <R/W><NV><h> POT1 3 (POT2LUT) 8h-C7h POT2 <R/W><NV><h> POT2 4 (POT1LUT) 8h-B8h POT1 Off <R/W><NV><h> POT1 5 (POT2LUT) 8h-B8h POT2 Off <R/W><NV><h> POT2 I 2 C I 2 C SCL SDA SCL SCL SDA SCL SDA SDA SCL SCL SDA SCL SDA t BUF t HD:STA t SP t LOW t R t F SCL t HD:STA t HIGH t SU:STA STOP START t SU:DAT REPEATED START t SU:STO t HD:DAT NOTE: TIMING IS REFERENCED TO V IL(MAX) AND V IH(MIN). 3. I 2 C 24

25 LDMOS RF MOST SIGNIFICANT BIT 4. 7-BIT SLAVE ADDRESS 1 1 A 2 A 1 A A 2, A 1, AND A PIN VALUES SDA SCL ()( 3) SCL SDA SCL SCL (ACK NACK) 9( ) 9 ACK 9 1 NACK ACK NACK3 ACK NACK ( ) ACK NACK 8 () ACK NACKSDA I 2 C ( 4)7 R/W R/W DETERMINES READ OR WRITE 11A 2 A 1 A () A2 A1 A 8 R/W = R/W = 1 I 2 C I 2 C I 2 C (R/W = ) (R/W = ) (1 ) 8( ) 3 6h (11h 22h 33h)6h 7h 11h 22h33h h EEPROM (R/W = ) 25

26 LDMOS RF EEPROM EEPROM(t W ) EEPROM EEPROM t W EEPROM EEPROM EEPROM 8 EEPROM 8 EEPROM 1 EEPROMSEE = 1 SRAMEEP ROM EEPROM R/W=1 NACK (R/W = ) (R/W = 1) ACK NACK 5 COMMUNICATIONS KEY S P START STOP A N ACK NOT ACK WHITE BOXES INDICATE THE MASTER IS CONTROLLING SDA SHADED BOXES INDICATE THE SLAVE IS CONTROLLING SDA NOTES: 1) ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST. 2) THE FIRST BYTE SENT AFTER A START CONDITION IS ALWAYS THE SLAVE ADDRESS, FOLLOWED BY THE READ/WRITE BIT. Sr REPEATED START X X X X X X X X 8 BITS ADDRESS OR DATA WRITE A SINGLE BYTE S 1 1 A 2 A 1 A A MEMORY ADDRESS A DATA A P WRITE UP TO AN 8-BYTE PAGE WITH A SINGLE TRANSACTION S 1 1 A 2 A 1 A A MEMORY ADDRESS A DATA A DATA A P READ A SINGLE BYTE WITH A DUMMY WRITE CYCLE TO MOVE THE ADDRESS COUNTER S 1 1 A 2 A 1 A A MEMORY ADDRESS A Sr 1 1 A 2 A 1 A 1 A DATA N P READ MULTIPLE BYTES WITH A DUMMY WRITE CYCLE TO MOVE THE ADDRESS COUNTER S 1 1 A 2 A 1 A A MEMORY ADDRESS A Sr 1 1 A 2 A 1 A 1 A DATA A DATA A DATA A DATA N P 5. I 2 C 26

27 LDMOS RF 4.7kΩ 3 PLACES 5V V CC FAULT SDA SCL A2 FACTORY-CALIBRATED 13-BIT ADC (CUSTOMER ADJUSTABLE FULL- SCALE AND OFFSET VALUES) 49.9kΩ 4.22kΩ 28V A1 A V D I D1 N.C. R POT2 R S2 R S1 R POT1 I D2 N.C. GND HCOM W2 L2 L1 W1 N.C. N.C. MAX6165B 5V REFERENCE RF IN RF POWER AMP RF OUT NOTES: 1) IN THIS CONFIGURATION, THE VOLTAGE RANGE OF W 1 AND W 2 IS 3V-5V. THIS RANGE CAN BE EXTENDED USING EXTERNAL RESISTORS. 2) ONE MAX6156B CAN BE USED WITH MULTIPLE s. NACK FFh h.1µf.1µf V CC GND 27

28 LDMOS RF SDA SCL SDA SCL / 5V 28V 4.7kΩ 3 PLACES V CC 49.9k (1%) FAULT SDA SCL A2 4.22k (1%) VD A1 A ID1 MAX48 LOW PASS FILTER R POT2 R S2 R S1 R POT1 ID2 GND HCOM W2 L2 L1 W1 MAX48 LOW PASS FILTER N.C. N.C. MAX6165B 5V REFERENCE RF IN RF POWER AMP RF OUT NOTES: 1) IN THIS CONFIGURATION, THE VOLTAGE RANGE OF W 1 AND W 2 IS 3V-5V. THIS RANGE CAN BE EXTENDED USING EXTERNAL RESISTORS. 2) ONE MAX6156B CAN BE USED WITH MULTIPLE s. TRANSISTOR COUNT: 52,353 SUBSTRATE CONNECTED TO GROUND Maxim MaximMaxim 28 Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA Maxim Integrated Products, Inc.