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1 2011 赛灵思 ( Xilinx ) FPGA 最新课程技术研讨会西安 1I/O

1 赛灵思 ( Xilinx ) FPGA 最新课程技术研讨会西安 1I/O Resources Xilinx 中国授权培训伙伴 - 依元素科技有限公司

2 2 Course Objectives After completing this module, you will be able to: Describe the I/O features in 7 series FPGAs Specify the relationship between banks and standards Explain each block in the IOB Describe the SelectIO interface logic and SERDES technology Explain the low power capabilities available in the 7 series FPGAs I/O Resources - 1-1

3 3 Overview Overview SelectIO Interface Electrical Resources SelectIO Interface Logical Resources Power Savings Using SelectIO Interface Resources Summary I/O Resources - 1-2

4 4 I/O Interface Challenges High-speed operation with maintained signal integrity Source-synchronous operation (clock forwarding) System-synchronous operation (common systems clock) Terminate transmission lines to avoid signal reflections Drive and receive data on wide parallel buses Compensate for bus skew and clock timing errors Conversion between serial and parallel data Achieve very high bit rate (> 1 Gbps) Single Data Rate (SDR) or Double Data Rate (DDR) interfaces Interface to many different standards Different voltages, drive strengths and protocols I/O Resources - 1-3

5 5 7 Series FPGA I/O Wide range of voltages 1.2V to 3.3V operation Many different I/O standards Single ended and differential Referenced inputs 3-state support Very high performance Up to 1600 Mbps LVDS Up to 1866 Mbps single-ended for DDR3 Easy interfacing to standard memories Hardware support for QDRII+ and DDR3 Digitally controlled impedance Low power Features to reduce power I/O Resources - 1-4

6 6 I/O Block Diagram I/O Resources - 1-5

7 7 I/O Types Two different types of I/O in 7 series FPGAs High Range (HR) Supports I/O standards with Vcco voltages up to 3.3V High Performance (HP) Supports I/O standards with Vcco voltages up to 1.8V only Designed for the highest performance Has ODELAY and DCI capability I/O Resources - 1-6

8 8 I/O Columns and Types - Kintex and Virtex Families I/O Resources - 1-7

9 9 I/O Columns and Types - Artix Family I/O Resources - 1-8

10 1 0 SelectIO Interface Electrical Resources Overview SelectIO Interface Electrical Resources SelectIO Interface Logical Resources Power Savings Using SelectIO Interface Resources Summary I/O Resources - 1-9

11 1 1 I/O Electrical Resources (1) P and N pins can be configured as Individual single-ended signals or Differential pair Receiver can be standard CMOS or voltage comparator When standard CMOS Logic 0 when "near" ground Logic 1 when "near" VCCO I/O Resources

12 1 2 I/O Electrical Resources (2) Receiver can be standard CMOS or voltage comparator Referenced to VREF Logic 0 when below VREF Logic 1 when above VREF Differential Logic 0 when VP < VN Logic 1 when VP > VN I/O Resources

13 1 3 I/O Versatility Each pin can be input and output (including 3-state) Each pin can be individually configured IDELAY, drive strength, input threshold, termination, weak pull-up or pull-down Based on banking rules (some standards not compatible within the same bank) Each I/O supports 40+ voltage and protocol standards, including LVCMOS LVDS, Bus LVDS LVPECL SSTL HSTL RSDS_25 (point-to-point) Many standards offer programmable slew rate I/O Resources

14 1 4 Internal Termination Using DCI (1) Digitally Controlled Impedance (DCI) Configures output driver impedance (series termination) Provides parallel termination to ½ VCCO (split termination, Thevenin equivalent) Available in HP banks only I/O Resources

15 1 5 Internal Termination Using DCI (2) Two reference pins per bank: VRP and VRN Make DCI independent of voltage, temperature, and process variations Connected to reference resistors (50 to 100 ohm) VRP pulled down to ground VRN pulled up to VCCO External resistors must be 2R for split termination; can be R or 2R for series termination I/O Resources

1 6 I/O Bank and Clock Region I/O banks are the same height as the clock region 50 I/Os per bank 50 CLBs per clock region column Each I/O bank can have one Vcco Only I/O standards compatible with

16 1 6 I/O Bank and Clock Region I/O banks are the same height as the clock region 50 I/Os per bank 50 CLBs per clock region column Each I/O bank can have one Vcco Only I/O standards compatible with Vcco can be placed in the bank Each I/O bank can have one Vref Each I/O bank can have one Vrn/Vrp pair DCI cascading can use Vrn/Vrp to/from other banks in same column Multiple I/O banks share one Vccaux_io for powering the I/O pre-drivers I/O Resources

17 1 7 SelectIO Interface Logical Resources Overview SelectIO Interface Electrical Resources SelectIO Interface Logical Resources Power Savings Using SelectIO Interface Resources Summary I/O Resources

1 8 I/O Logical Resources Two blocks of logic per I/O pair Master and slave Can operate independently or concatenated Each block contains ILOGIC/ISERDES SDR, DDR, or high-speed serial input logic

18 1 8 I/O Logical Resources Two blocks of logic per I/O pair Master and slave Can operate independently or concatenated Each block contains ILOGIC/ISERDES SDR, DDR, or high-speed serial input logic OLOGIC/OSERDES SDR, DDR, or high-speed serial output logic IDELAY Selectable fine-grained input delay ODELAY Selectable fine-grained output delay Only available on High Performance I/O I/O Resources

1 9 ILOGIC: Input SDR and DDR Logic Two types of ILOGIC blocks ILOGICE2 for High Performance banks ILOGICE3 for High Range banks Has zero hold delay capability ILOGIC inputs come from the input

19 1 9 ILOGIC: Input SDR and DDR Logic Two types of ILOGIC blocks ILOGICE2 for High Performance banks ILOGICE3 for High Range banks Has zero hold delay capability ILOGIC inputs come from the input receiver Directly or via the IDELAY block Outputs drive the FPGA fabric Directly (no clocked logic) or Via the IDDR In SDR mode on rising or falling edge of clock In DDR mode on both edges of clock o Can also use two clocks, 180 out of phase I/O Resources

20 2 0 IDDR Modes Modes control presentation of data to fabric OPPOSITE_EDGE Q1 output valid after rising edge of C, Q2 after falling edge of C SAME_EDGE Q2 is delayed to next rising edge of C SAME_EDGE_PIPELINED Q2 and Q1 are both delayed to next rising edge of C I/O Resources

2 1 OLOGIC: Output SDR and DDR Logic OLOGICE2 for HP banks, OLOGICE3 for HR banks Output of OLOGIC connects to the output driver directly, or via the ODELAY ODELAY is available in HP banks only

21 2 1 OLOGIC: Output SDR and DDR Logic OLOGICE2 for HP banks, OLOGICE3 for HR banks Output of OLOGIC connects to the output driver directly, or via the ODELAY ODELAY is available in HP banks only Output is driven directly from the fabric Directly, through an SDR flip-flop or via the ODDR using both edges of clock Each OLOGIC block contains two ODDR One for controlling the data to the output driver One for controlling the 3-state enable Both ODDR are driven by same clock and reset SAME_EDGE or OPPOSITE_EDGE only I/O Resources

2 2 ISERDES: Input Serial-to-Parallel Converter Clocks in data from input pad or IDELAY D is clocked on high speed clock (CLK) Can be SDR or DDR Sends de-serialized data to fabric Q is clocked on low

22 2 2 ISERDES: Input Serial-to-Parallel Converter Clocks in data from input pad or IDELAY D is clocked on high speed clock (CLK) Can be SDR or DDR Sends de-serialized data to fabric Q is clocked on low speed clock (CLKDIV) CLK and CLKDIV must be in phase De-serializes data Single data rate: 2, 3, 4, 5, 6, 7, 8 Double data rate: 4, 6, 8 Cascade with slave for wider ratios Double data rate: 10, 14 Has BITSLIP logic for framing parallel data I/O Resources

23 2 3 Word Alignment (Bitslip) Data sent serially needs to be re-framed Data sent by the transmitter has a known grouping of bits to words The receiver must de-serialize data back into words, but has no mechanism of knowing which N consecutive bits form a word Framing is arbitrary Control logic can assert the BITSLIP signal to change the framing Once framing is regained, the interface can carry word aligned data I/O Resources

2 4 OSERDES: Output Parallel-to-Serial Converter Serializes out data to output pad or ODELAY Q is clocked on high speed clock (CLK) Can be SDR or DDR Parallel data comes from fabric D is synchronous

24 2 4 OSERDES: Output Parallel-to-Serial Converter Serializes out data to output pad or ODELAY Q is clocked on high speed clock (CLK) Can be SDR or DDR Parallel data comes from fabric D is synchronous to low speed clock (CLKDIV) CLK and CLKDIV must be in phase Serializes data Single data rate: 2, 3, 4, 5, 6, 7, 8 Double data rate: 4, 6, 8 Cascade with slave for wider ratios Double data rate: 10, 14 When using 3-state serializer, both the data and 3-state width must be 4 Clocks are shared between both serializers I/O Resources

2 5 IDELAYE2 and ODELAYE2 Separate IDELAY and ODELAY delay lines IDELAY is available in both HR and HP banks ODELAY is only available in HP banks Delay line elements are calibrated using the

25 2 5 IDELAYE2 and ODELAYE2 Separate IDELAY and ODELAY delay lines IDELAY is available in both HR and HP banks ODELAY is only available in HP banks Delay line elements are calibrated using the IDELAYCTRL cell Delay is process, temperature, and voltage independent IDELAY and ODELAY have almost identical capabilities IDELAY can also be accessed from the fabric Tap counter value can be accessed via FPGA fabric Monitor, increment, decrement, or set the tap value; tap value can be from 0 to 31 Reference frequency can be 200 MHz in all speed grades; 300 MHz is also allowed in fastest speed grade Results in 78 ps or 52 ps per tap I/O Resources

26 2 6 Structure of ODELAYE2 and IDELAYE2 7 series devices have a pipeline register to defer loading CNTVALUEIN I/O Resources

27 2 7 IDELAYCTRL The IDELAYCTRL calibrates the individual delays used in the IDELAY and ODELAY Uses the reference clock provided on the REFCLK pin One IDELAYCTRL exists in each I/O bank Must be connected in any bank that uses an IDELAY or ODELAY User must explicitly instantiate at least one The ISE tools will replicate it in all banks that need it To aid replication, the attribute IODELAY_GROUP can be attached to an instantiated IDELAYCTRL and all IDELAY/ODELAY elements that should use that IDELAYCTRL as a reference I/O Resources

2 8 Using IDELAY for Dynamic Phase Adjustment At very high speeds, it may be impossible to statically locate the "correct" phase to sample incoming data Data eye is known to exist, but its

28 2 8 Using IDELAY for Dynamic Phase Adjustment At very high speeds, it may be impossible to statically locate the "correct" phase to sample incoming data Data eye is known to exist, but its location with respect to clock cannot be statically determined Phase of the data or clock can be dynamically adjusted to find the correct phase relationship for this PVT I/O Resources

29 2 9 Using IDELAY to Compensate for Board Skew Skewed data bus or clock Corrected with IDELAY I/O Resources

3 0 Balancing IDELAY/ODELAY Timing When added to an input or output path, the IDELAY or ODELAY adds an intrinsic delay This delay is in addition to the TAP delay

30 3 0 Balancing IDELAY/ODELAY Timing When added to an input or output path, the IDELAY or ODELAY adds an intrinsic delay This delay is in addition to the TAP delay selected For high-speed interfaces, it is often necessary to add IDELAY/ODELAY to both the clock path and data path to cancel out the intrinsic delay I/O Resources

31 3 1 Power Savings Overview SelectIO Interface Electrical Resources SelectIO Interface Logical Resources Power Savings Using SelectIO Interface Resources Summary I/O Resources

32 3 2 I/O Output Power Consumption LVDS: Highest performance, but constant high power HSLVDCI: Balances power and performance I/O Resources

33 3 3 7 Series FPGA I/O Low-Power I/O Attributes IDELAY/ODELAY (HIGH_PERFORMANCE_MODE) = TRUE/FALSE TRUE Means highest performance FALSE Lowest power (50% less) IBUF new low power mode (IBUF_LOW_PWR) = TRUE/FALSE TRUE Lowest power (50% less) at the expense of speed FALSE Highest performance I/O Resources

34 3 4 Input Power Consumption per I/O Input power varies with different standards I/O Resources

35 3 5 Example: 7 Series FPGA SelectIO Interface Lower Power I/O Resources

36 3 6 Dynamically 3-Statable Input Termination T_DCI I/O Resources

3 7 New I/O Power Savings Input disable The input buffer of an IOB consumes power When an IOBUF is driving data out, the input is not needed and can be disabled IBUF can be disabled

37 3 7 New I/O Power Savings Input disable The input buffer of an IOB consumes power When an IOBUF is driving data out, the input is not needed and can be disabled IBUF can be disabled under user control using IBUF_DISABLE signal Reduced I/O pre-driver voltage Internal voltage used by differential and referenced I/O standards Reduced from 2.5V to 1.8V I/O Resources

38 3 8 Using SelectIO Interface Resources Overview SelectIO Interface Electrical Resources SelectIO Interface Logical Resources Power Savings Using SelectIO Interface Resources Summary I/O Resources

39 3 9 I/O Electrical Resources Input, output, 3-state outputs, and I/O buffers can be inferred Primary inputs, outputs and I/O of the design will have I/O buffers inferred I/O standard and other properties of the IOB can be specified un the User Constraint File (UCF) Includes differential standards, which will automatically infer both the N and P buffers These resources can also be instantiated directly Instantiate generic IBUF, OBUF, OBUFT, IOBUF, IBUFDS, OBUFDS, OBUFTDS, IOBUFDS, IBUF_DIFF_OUT, IOBUF_DIFF_OUT Set attributes in UCF Resources are instantiated by various wizards I/O wizard, clocking wizard, memory interface generator I/O Resources

40 4 0 I/O Logical Resources SDR resources utilizing ILOGIC and OLOGIC resources can be inferred Packing of flip-flops into the ILOGIC and OLOGIC can be controlled using synthesis and map properties and attributes on the flip-flops Set attribute IOB=FALSE to not pack or TRUE to allow packing and FORCE to ensure that packing occurs Input DDR can be inferred See Xilinx Answer Record (AR #15779) Output DDR, ISERDES, and OSERDES resources must be instantiated Instantiate primitives (refer to the Xilinx Unified Library) Use the SelectIO Interface Wizard Memory Interface Generator (MIG) I/O Resources

4 1 SelectIO Interface Wizard Generates a complete I/O interfaces Pre-designed interfaces like SGMII, DVI, Camera Link Custom designed interfaces Input, output, bidirectional

41 4 1 SelectIO Interface Wizard Generates a complete I/O interfaces Pre-designed interfaces like SGMII, DVI, Camera Link Custom designed interfaces Input, output, bidirectional SDR, DDR Serialized Any width up to 16 IDELAY and/or ODELAY Generates I/O electrical and logical resources Generates clocking structures to support interface I/O Resources

4 2 Memory Interface Generator Generates a complete memory controller and interface design Output: RTL, UCF, documentation, and timing analysis

42 4 2 Memory Interface Generator Generates a complete memory controller and interface design Output: RTL, UCF, documentation, and timing analysis VHDL or Verilog Choose from a predefined catalog of available devices and interfaces Included with the CORE Generator interface I/O Resources

43 4 3 Summary Overview SelectIO Interface Electrical Resources SelectIO Interface Logical Resources Power Savings Using SelectIO Interface Resources Summary I/O Resources

44 4 4 Apply Your Knowledge 1. Can you identify the I/O resources of the 7 series? I/O Resources

45 4 5 Summary (1) Two different types of I/O High Range for 3.3V I/O High Performance for the highest throughput at up to1.8v Support for a large range of inputs, outputs and I/O Support for many I/O protocols Great performance Up to 1600 Mbps on LVDS Up to 1866 Mbps single-ended for DDR3 Hardware support for QDR2+ and DDR3 I/O Resources

46 4 6 Summary (2) Digitally controlled impedance control and on-chip termination Low power, including mechanisms to trade-off performance and power SDR, DDR, and high-speed SERDES for managing high-performance interfaces Calibrated input and output delays for precise control over data capture I/O Resources

Microsoft PowerPoint - STU_EC_Ch08.ppt

Microsoft PowerPoint - STU_EC_Ch08.ppt 樹德科技大學資訊工程系 Chapter 8: Counters Shi-Huang Chen Fall 2010 1 Outline Asynchronous Counter Operation Synchronous Counter Operation Up/Down Synchronous Counters Design of Synchronous Counters Cascaded Counters