dv3113-ylc01-01(a)090220

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1 YRV_OUT U_OUT GY_OUT V_OUT /PIF_OUT RT_R RT_L FP_LK TY MI MI MI MI OX_PIF OX_PIF RT_WITH UIO/TV/: RT_L RT_R MEMT FU_IRQ FU_LK MEMT FU_# _LK FU_LK _M FU_# _0 FU_IRQ /R_INERT MEMT RT_R RT_L GY_OUT V_OUT UIO/TV/: U_OUT RT_WITH YRV_OUT LFEOUT OX_PIF U V_G_Y Y_R_V V_ V_OUT GY_OUT U_OUT YRV_OUT PV V V RFV MV V V PV PV PV V V PV PV V PV PV U FP_OUT V_ FP_LK FP_T IRRV Y_R_V V_G_Y /PIF_OUT F F RT_L RT_R MI_IN TY RT_R RT_L _LK _M _0 /R_INERT RMINOUT LMINOUT ENOUT LFEOUT ROUT LOUT V: V(0%) V: V(.%) PWRTRL GN IR TV T LK T t middle of trace. RG tatus RT config circuit For EMI Power supply board should cut off RFV, V, V when TY = LOW Video tatus 线路图 hecked: ONNETOR HEET: HEN ZHEN MT O.,LT esign: OF VER: pprd: WG NO.:VYL00 PRT NO.: MOEL: V TY NO TY L Q0 Ω N0 R R R K R K E0 00uF/0V E0 00uF/0V R K R K F0 F00 <.m> F0 F00 <.m> 00nF 00nF N0 p/.0 N0 p/.0 TV IR T LK T GN 0pF 0pF H H H H uf uf R R 0 00nF 0 00nF R R JK0 Rx JK0 Rx 0pF 0pF R.K R.K R N/ R N/ 00pF 00pF 00nF 00nF R R R R R R Q N0 Q N0 E 0uF/0V E 0uF/0V uf uf 00pF 00pF 00pF 00pF 0pF 0pF MRK MRK. JK0 Rx JK0 Rx 00nF 00nF L0 F00 L0 F pF 0 00pF F F00 F F00 R.K R.K R0 0K R0 0K 00pF 00pF 00nF 00nF R.K % R.K % R.K R.K nf nf 0pF 0pF 00nF 00nF MRK MRK. F [Ω] F [Ω] JK0 R JK0 R N0 P/.0 N0 P/.0 00nF 00nF R R R R pf pf Q0 00 Q0 00 R.K % R.K % R0 R R0 R F F00 F F00 00pF 00pF 0 00pF 0 00pF E 0uF/0V E 0uF/0V 0 0 R R R 0K R 0K R 0K R 0K R R 00pF 00pF 00pF 00pF F F00 <0.m> F F00 <0.m> L0 F00 L0 F00 L0 F00 L0 F00 00nF 00nF L0 F00 L0 F00 L0 F00 L0 F00 N0 /MM/M N0 /MM/M pF 00pF Q N0 Q N0 N RT <Implementation> N RT <Implementation> R 0K R 0K pf pf R0 R0 R R R R F F00 F F00

2 V _REF V V _REF _REF _REF _REF _REF _REF V _TL V PV V V VPWM PV LMINOUT RMINOUT ENOUT LOUT LFEOUT ROUT PWM_L PWM_R PWM_EN PWM_LFE PWM_R VFE_YIN MI_IN RT_L RT_R PWM_L _TL OP OP OP OP OP OP OP OP OP OP OP OP Mute ircuit Value in [] is for internal. Power Off Mute Power On Mute 线路图 hecked: UIO& HEET: HEN ZHEN MT O.,LT esign: OF VER: pprd: WG NO.:VYL00 PRT NO.: MOEL: V 00pF [pf] 00pF [pf] R K R K nf [.nf] nf [.nf] 0.uF 0.uF R K R K U0 LM U0 LM R.K R.K R0.K R0.K Q N0 Q N0 R R R R R.K R.K Q N0 Q N0 R 0 R 0 R 0K R 0K nf [.nf] nf [.nf] nf nf R0 K R0 K 0 00nF 0 00nF R 0K R 0K R0 K R0 K 00nF 00nF 00pF [pf] 00pF [pf] 0 00pF [pf] 0 00pF [pf] R0 0K R0 0K R K R K E 0uF/V E 0uF/V Q N0 Q N0 R0.K R0.K R K R K R K R K 0 uf 0 uf nf nf 0 00pF [pf] 0 00pF [pf] R K R K E0.uF/0V E0.uF/0V R 0K R 0K R.K R.K R0 K R0 K 0 nf [.nf] 0 nf [.nf] R.K R.K U0 LM U0 LM R K R K R0 K R0 K Q N0 Q N0 R K R K E.uF/0V E.uF/0V R0 0K R0 0K R K R K E.uF/0V E.uF/0V R K R K E 0uF/V E 0uF/V E.uF/0V E.uF/0V R R E.uF/0V E.uF/0V R.K R.K nf [.nf] nf [.nf] U0 LM U0 LM R K R K R 00K R 00K R.K R.K T T R0 K R0 K E 00uF/0V E 00uF/0V R0 K R0 K R K R K 0 nf [.nf] 0 nf [.nf] nf nf R 0K R 0K 0 nf [.nf] 0 nf [.nf] nf nf R0 0K R0 0K Q 0 Q 0 R K R K R 0K R 0K R0 K R0 K Z0 V Z0 V 00 00pF [pf] 00 00pF [pf] R K R K R K R K R K R K R00 0K R00 0K Q0 0 Q0 0 00nF 00nF U0 LM U0 LM nf nf R.K R.K Q 0 Q 0 U0 LM U0 LM R 0K R 0K 0 00nF 0 00nF R0 R0 Q N0 Q N0 E.uF/0V E.uF/0V E 00uFV E 00uFV 0 00nF 0 00nF R K R K U0 LM U0 LM R K R K nf nf Q0 N0 Q0 N0 Q N0 Q N0 00nF 00nF R0 K R0 K R 00K R 00K 0 00pF [pf] 0 00pF [pf]

3 线路图 PV R.R E 00uF/0V 0 00nF M_V M_ M_V M_ EMF urrent Type(efault) N0 is used for anyo/amsung/ony OPUs Q0 0 PV R L_V VR_ VR_V R R PL_EN P_M R.R R.R R K 00nF 0 PL_EN PV GN GN F F T T /V_W RF F 0 GN/P V(VREF) V E N VR VRV L M HFM 0 N VL GNL pf OPUV V nf TT TT FT FT pf nf VL OPU_HFM L VR_V VR_ Q0 0 L0 0uH R R <0.m> R.R.V E 00uF/0V R nf R [.m] RF_E V RF_F RF_ RF_ RF RF_ RF_ L_ E 00uF/0V RFV RFV R.K _V nf PI ontrol: V=LOW =HIGH _V FOU_ V_RV U0 M VINF FERR(TR_) NYO H0 RIM 0 TY I R 0 V R 0 RV P_MOT R K T PL_EN PL_EN Pin/0.MM N0 00nF 00nF E 00uF/0V V_F LE_ V_F FERR(REGO) VINL VINL(REGO) VINTK TKERR(TR_) TKERR(N) TRK_ V_RV VOL(FW) VINL PL_ LOE LOE VNFF(REV) PREGN MV MV V PV E 0uF/0V 0 00nF 0 PV(LO) PGN(LO) VOL(VOL) VNFTK(N) PGN(V) VOL 0 LO LO L_MOT P_M L_MOT VOL(VOL) VOL P_MOT EM lose to N0 VL L FT FT VOF VOF GN 0 GN VOTK VOTK TT TT FOU_ TRK_ PL_ LE_ lose to Vaddis! R0 K R K R K R K FOU_PWM TRK_PWM PL_PWM LE_PWM 0pF [0pF] 0pF [0pF] nf nf nf nf PV MV 0 N00 N00 00/0 N0 LE LE LE LE GN GN P P P P P/.0 L_MOT L_MOT P_MOT P_MOT R.K remove c nf V_RV Q0 0 PV V_F R.K % 0 N00 E 00uF/0V V_RV Q0 0 R %.V V_F.V PV E Q0,Q0 must have enough large pads for thermal spreading lose to motor driver. PV R R K % K V R0 K % 00nF 00nF LO LO OUTW GN INW P/.0 INW GN OUTW LO LO N0 LO LO IN_OUT_W INW IN_OUT_W INW R R K % K % Motor driver R R R (.V) K %.K % % nf nf M.K % K % % esign: MOEL: V ERVO hecked: PRT NO.: WG NO.:VYL00 pprd: HEET: OF VER: HEN ZHEN MT O.,LT

4 线路图 <.m> E0 0nF nf 00uF/0V 0nF 0nF VPWM OIN VFE_YIN RF_F PL_EN RF_E PL_EN RF_ RF_ U0 For EMI (s lose as possible to U00 ) F_ R FI / V.K O /HOL PV R PV R.K FLK /WP K.K FO GN I R lose to ENF0 _TL R _TL 0 Ohm % Reset F F_0 Gen_/VI RET Vaddis R R 0 U F V U 0 PV FO R R FO_0 GN V 0 Y_R_V FI R0 R FI_0 FO/R_F R V_ Y_R_V 0 REET# FI/R_ootsel 0.K V V_ 0 V V 0 V_G_Y FLK FLK_0 VP E0 R R V_G_Y 0 F GN 0uF/V FLK/R_ootsel OIN F _0 XIN Q0 GPIO[] OOUT _0 F XO R.K N0 _/IGPIO[] VPLL F _M PWM VPLL REET# _M _LK _M/GPIO[] GNPLL R _LK REET# R _LK/IGPIO[] U_P V U_N VaddisXE/XF 0K 0 VP VP 0 [nf] N P IRRV IRRV RM N IGPIO[] UPR0/FP_OUT RM RM[] GPIO[]/UPR0/TO/TX FP_OUT 0 RM RM[] GN /PIF_OUT RM[] GPIO[]/PIFO /PIF_OUT VPWM RM VIP VP GP0 GN RM RM[] GPIO[]/MLK/PWM0 R K GP PWM_L RM RM[] GPIO[]/PWM R K GP PWM_R RM RM[] GPIO[]/PWM R K 00nF R K GP PWM_L RM[] GPIO[]/OUT/PWM R K GP PWM_R V GPIO[]/UPR/LRLK/PWM 0 GP PWM_EN GN IGPIO[]/UPT/LK/PWM R K PWM_LFE PV PV 00pF U_N R R U_N lose to pin U_P R R U_P 0 <.m> 00nF 0nF 0nF 0nF 0nF 0nF 0nF 0nF 0nF 0nF E0 00uF/0V IPLK FOU_PWM L_V L_ M_V M_ RF_ RF_ RF_ RF_ RF_E RF_F L_V L_ INW RV IN_OUT_W LOE VFE OOUT R0 R _V V RM0 RM RM0 RMWE RMQM RM RM RM0 RM RM RMR RM IPLK RMT RMT RMT RMT RMT0 RMT RMT RMT RMT RMT RMT RMT RMT RMT RMT RMT0 R LOE R RV _V_ FP_T UPT0/FP_LK VPWM VFE VFE VFE LE_PWM PL_PWM TRK_PWM REOUT VREF V RFN RFP F_ F INW IN_OUT_W FLK FP_T FP_LK RF VPLL R0.K % 00nF V VFE_YIN RF_F PL_EN RF_E PL_EN RF_ RF_ RMT0 V V RMT Q0 Q RMT VQ VQ RMT RMT Q Q RMT Q Q 0 RMT VQ VQ RMT RMT Q Q RMT Q Q RMT VQ VQ 0 RMT0 RMT Q Q0 RMT Q Q RMT VQ VQ RMT Q Q RMQM V V RMWE QML N 0 RMQM RM WE# QMH PLK RMR # LK RMKE RM R# KE RM # N 0 RM RM0 0 RM RM0 RM RM0 0 RM RM 0 RM RM RM RM 0 RM V V PV RM.V PVI RM RM RM RM0 RM0 RM RM0 RMR RM RMWE RMQM RMT RMT RMT RMT RMT RMT RM RM RM RM RM RM RMKE PLK RMQM RMT RMT RMT0 RMT RMT RMT PLK pf RM.V RMT RMT0 RMT RMT RF_ RF_ /R_INERT _TL IRRV PL_EN INW RV IN_OUT_W LOE EM usage 0 pf 0 pf 0 pf 0 pf 0 pf 0 pf 0 pf 0 pf remove c0, c pf pf lose to Vaddis! Important power supply! 0 0nF F0 F00 PV rystal Use it to connect the shell of the crystal with ground. R0 00K PH. Y0.000MHz pf 0 pf PV PV PV PVI _V RF PV PV VPWM.0V PV V GN PV PV PV RM.V RMKE RM.V PV UPT0/FP_LK UPR0/FP_OUT FP_T FP_LK L_V L_ M_V M_ PL_EN FOU_PWM TRK_PWM PL_PWM LE_PWM RF_ RF_ erial Flash pinout for reference /R_INERT R0 K R0 K R0 K Put close to the middle of the trace U0 nf R0 nf pf F0 F00 E0 <.m> 00uF/0V Note: For the signal of IRRV,FP_OUT,REET# can't across through under the chip ( ) 0nF 0nF nf F0 F00 <m> E0 00uF/0V lose to Vaddis! ownload Pin short XXm 00m for device P/.0 U 0 0nF 0nF 0nF F0 F00 dd: U0 [Mbit:KHU0] R 0K.V UPT0 UPR0 GN ownload & debug esign: MOEL: V P hecked: PRT NO.: WG NO.:VYL00 pprd: HEET: OF VER: HEN ZHEN MT O.,LT RM[0] RM[] RM[0] VP RM[] RM[]/GPO[] RM0# RM RM#/GPO[] RMR# RM# VP RMWE# RMQM GNPLK PLK VPLK RMT[] RMT[] RMT[] RMT[] RMT[0] RMT[] RMT[] RMT[] RMT[] RMT[] VIP RMT[] RMT[] V RMT[] RMT[] RMT[] RMT[0] VP GNPWM VPWM R R % R R % R R % R R % Gen_/GPIO[0] 0 Gen_ 0 VP 00 Gen_ Gen_ Gen_ Gen_ Gen_/VI0 V GPIO[]/PWMO[]/HYN GPIO[]/PWMO[]/FIEL GPIO[0]/PWMO[]/VLKx VPWM 0 GPIO[]/PWMO[0] V_L _L V_M _M VFE GNREF REOUT VREF V 0 GNFE VFE_YIN F K E J VFE 0 VFE RFN RFP GN 0 00nF E0 0uF/.V R R N0.K %.K % 00nF pf pf 0nF 0nF 0nF U0 Mbit: KT/L0 N0 P/ V 0 0/P R WE LQM VQ Q Q VQ Q Q VQ Q Q VQ Q Q0 V V 0 N KE LK UQM N VQ Q Q 0 VQ Q0 Q VQ Q Q VQ Q Q V 0 0nF 0nF R R 00nF 0nF R0 K R 0K R K R0 R 0nF 0nF F0 F00 <0.m> JP [Jumper]

5 线路图 PLF mh/0.0/x G0 P PE 0uF/00V PE 0uF/00V PR 00K/W PR 0//W P N00 P /KV PT P RG 00uF/V PE PL P 00nF 0uH00m 00uF/V PE TV PR ZYT000 Vsb PV PF PR K PE 0uF/V TL/0V PR PR Vsb PV TV Q0 0 R.K V TY NO TY L0 Q0 Q0 0 N0 F00 PON 000V INPUT POWER WITH Note: P 00nF PR 00K PE 0uF/V EN P N PU TNY P PR 0/KV P PL uh/ R0 P 00nF PE 000uF/V PON 00K PU P PR PR0.K PR 0K PR.K L0 [F00] R0 K PY 0/0V PU TL P 00nF PR.K Q N0 R.K TY R 0K TY Power supply board should cut off RFV, V, V when TY = LOW esign: MOEL: V TO hecked: PRT NO.: WG NO.:VYL00 pprd: HEET: OF VER: HEN ZHEN MT O.,LT

6 FLH /M RM *M/*M NYO V H0 or arima0 P V OUTPUT VIEO PORT V MOTORRIVER U0 ZRXE YUV OUTPUT VIEO PORT T ZYT000 U0 IN 000V PWM POWER TNYPN I0.V.V IGTL OXIL OUTPUT OXIL PORT U. INPUT U PORT R L V LE RIVER OPERTIONL MPLIFIER NJM U0/U0/U0.H UIO OUTPUT UIO PORT LE IPLY esign: MOEL: V TO hecked: PRT NO.: WG NO.:VYL00 pprd: HEET: OF VER: HEN ZHEN MT O.,LT

7 线路图 Zoran V Player esignvaddis XE/XF Project: V Version: OPU:H0 or rima 0 LE IPLY U. KROK.H/RT or(yuv/v) OUTPUT 合卡 esign: MOEL: V feature hecked: pprd: PRT NO.: HEET: HEN ZHEN MT O.,LT WG NO.:VYL00 VER:

tsumv39lu for mtc v _?

tsumv39lu for mtc v _? MP LOUT# ROUT# E 0uF/V R LOUT_SP E 0uF/V R ROUT_SP /0 /0 LOUT LOUT- ROUT- ROUT N0 P/.MM MP-UOUTL0 MP-UOUTR0 MP-UOUTL0 MP-UOUTR0 R 0 0 R 0 L R R0 /K E 00uF/V V L 0.uF LOUT# ROUT# MUTE R E 0.uF 0uF/V 0.uF