,.,, IP,. ( FPGA ) SoC,. Xilinx DSPTM System Genera2 tor [8] Altera DSP BuilderTM [9] Simulink, FPGA.,. FPGA,, FPGA,., ARM FPGA SoC., SoC. 1,

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1 ACTA ELECTRONICA SINICA Vol. 37 No. 2 Feb , 1, 1, 2, 1 (11, ;21, ) :, (SoC).. SoC,,. H1264. SoC,. : ; ; : TP368 : A : (2009) A Multiproce ssor Prototype and Its SoC De sign Methodology HUANG Kai 1,YIN Liao 1,LIN Feng2yi 1,GE Hai2tong 2,YAN Xiao2lang 1 (11 Institute of VLSI design, Zhejiang University, Hangzhou, Zhejiang , China ; 21 C2Sky Microsystems Company, Hangzhou, Zhejiang , China) Abstract : Fast development of embedded application drives the SoC design more complex. How to design multiprocessor SoC efficiently and reliably is becoming a challenge to the designers. To address this challenge,a new multiprocessor prototype and its SoC design methodology are proposed in this paper. It combines multi processors and their communication into one software2 hardware prototype in different abstraction levels. The method of seamless refinement from high level abstraction to low level VLSI implementation can design and verify the software/ hardware interface and improve designing software/ hardware architecture effi2 ciently. The experiment of H. 264 decoder shows the feasibility of multiprocessor prototype in both function and physical implemen2 tation. The seamless refinement method based on this prototype can ensure the correctness of SoC design and be helpful for its soft2 ware/ hardware architecture optimization. 1 Key words : multi2processor prototype ;System on Chip (SoC) ;software2hardware co2design, (SoC) IC., (MPSoC) [1]., MPSoC : (1) ; (2) ; (3) [2]., MPSoC, MPSoC [3]. SoC :,,. 2, SoC : (Virtual Prototype) ( Fast Prototype). ( SpecC System C ) SoC,, SoC [4]. SpecC [5],. CoWare ConvergenSC [6],Mentor Seamless CVE [7] SystemC,,, : ; :

2 ,.,, IP,. ( FPGA ) SoC,. Xilinx DSPTM System Genera2 tor [8] Altera DSP BuilderTM [9] Simulink, FPGA.,. FPGA,, FPGA,., ARM FPGA SoC., SoC. 1, SoC., : (1) SoC, ; (2), ; (3) ( ) ( ).. 3 SoC 311,,,,., : ( Simulink) (System C TLM) RTL (Verilog) FPGA(Xilinx) : (CPU SS) (Memory SS).,.., ( Multi2Core HAD Con2 troller) ( Performance Monitor Controller) (Cache OP. Snooper) (Power Management),.,,,, ;, ;,. 2( a), ( ),,. (Mail Box). 2( b),. (CPU SS Interface) AHB AHB, DMA. ( Cache Sync). ( SS Monitor),,. DMA. 2( b), DMA,,.., AHB

3 2 : 307., DMA. AHB ,. TAP..,.,. (AHB HPROT ).,. ( ),, ( a),,,. 3( b), : ( Hardware Dependent Software, HDS) ( Hardware Abstraction Layer, HAL).,, HDS API( 3 ( c) recv - data send - data).,. HDS,, ( GFIFO HWFIFO). uclinux Linux. HDS, HAL (Firmware), IO..,,. 312 SoC. SoC Simulink SoC [11], ( 1 2) Simulink

4 Simulink : Simulink Simulink. Simulink, ( S2function) Simulink. 1, ( C/ C + + ) Simulink,,. 2,Simulink Simulink ( CAAM),. CAAM,. CPU,.,Simulink CAAM XML Colif CAAM. Colif,, CAAM ( 3 4) Colif CAAM.,. : (Virtual Architecture,VA) (Transaction2Accurate,TA) (Virtu2 al Prototype,VP). : CPU.,. CPU.,.,,,., HDS. CPU., BFM CPU., HAL, HDS.,. ( ISS), HAL. 4, ( Hardware archi2 tecture Gen) (Multithread code Gen) Colif CAAM., ; Colif CAAM, CPU., Main Makefile ; ; HDS,.

5 2 : ( 5 6 7),., RTL. SoC Colif CAAM RTL, RTL. SoC (Config Parser) Colif CAAM, IP IP ( IP Integrator) ( Platform Gen). IP, IP,. IP,, (Regress).,RTL FPGA. 411 H1264 JM713, 30 QCIF Foreman. H1264 Simulink IF,5 FOR 101 Simulink. ( : GHz Intel Xeon) FPGA ( Virtex24 XC4VLX1602FF15) 2,VA (18 ),. TA, 30 %,. TA [13], 80 %,. VP ISS, 90 %,, CKCore,,,. 1, : CK510 Application VA TA VP FPGA CK520 ( ) CK560 (MMU) CK510E H frame 4s 18s 380s 4260s (DSP ) [11] QCIF Foreman (50M Hz). H1264 Timing Accuracy 0 % % 90 % 100 %, SoC H. 264 H1264 GNU GCC, 5 ( a) ( d)

6 H K, 300K,. VA, H , 1,3 4 Deblocking. 5 ( d), p2 p4 p1, MB 015K byte. TA VP HdS, HdS 17K: OS kernel OS C 118K 112K 318K, HAL DMA LCD H ( i) ( j), Cache 2K 4K 8K,H1264 Cache,8K Cache 9815 %, Cache (miss) (Refill),, Cache 8K Cache 90 %., 5 ( g),vp, Cache Cache.,,., CPU2, 70 % 16K 48K 32K, CPU2,. FPGA ( 8 256KB, DDR ) 5( i) Cache, (MO) ( 12 %)., H1264,. 5 ( h) ( xp x ),,. 5 ( j), : (comp, ), (idle, ) (comm, ). 2 P, 1 ( p1), 2( p2). p2, : Deblocking ( p2,4 P p3) ( p3,4 P p4). p1, : ( p1) ( p2). 4 P 1 P. 412 SMIC 0113 m, , AHB , CKCore 85 %. (Worst Case), 240MHz, 120MHz,, QCIF H SoC, SoC.,,. SoC,,. H1264. SoC,.,,. : [1] A A Jerraya,et al. Special Issue on MPSoC[J ]. IEEE Comput2 er,2005,38 (7) : [2 ] Grant Martin. Overview of the MPSoC Design Challenge [ A ]. 43th DAC[ C ]. New York :ACM, [ 3 ] Ahmed Jerraya, Wayne Wolf. Multiprocessor Systems2on2Chip [ M ]. San Francisco : Elsevier Morgan Kaufmann, [ 4 ] Keutzer K et al. System2level design :Orthogonalization of con2

7 2 : 311 cerns and platform2based design[j ]. IEEE Transaction On CAD of Integrated Circuits and Systems,2000,19 (12) : [5 ] D D Gajski,J Zhu, R Dgmer, A Gerstlauer, S Zhao. SpecC : Specification Language and Methodology [ M ]. Boston : Kluwer Academic Publishers, [ 6 ] CoWare,SoC platform2based design using Convergen SC/ Sys2 temc[ EB/ OL ],2002,http :/ / www. coware. com. [7] Mentor Graphics,Seamless CVE[ EB/ OL ],http :/ / www. men2 tor. com/ products/ fv/ hwsw - coverification/ seamless/. [ 8 ] Xilinx,System Generator for DSP Performing Hardware2in2the2 Loop With the Spartan? 23E Starter Kit [ DB/ OL ]. www. xil2 inx. com/ products/ boards/ s3 estarter/ files/ s3esk - sysgen - hw - in - loop. pdf. [9 ] Altera, DSP Builder [ DB/ OL ]. www. altera. com. cn/ prod2 ucts/ software/ products/ dsp/ dsp2builder. html. [ 10 ] ARM, ARM Integrator CP Baseboard [ DB/ OL ]. http :/ / www. arm. com/ documentation. [11 ],32 CPU CK2CORE [ EB/ OL ]. http :/ / www. c2sky. com/ product. p hp? id = 5. [12 ] Kai Huang,et al. Simulink Based MPSoC Design Flow : Cases study of Motion J PEG and H. 264 [ A ]. 44th DAC [ C ]. New York :ACM Press, [13 ] Yi, Y Kim, D, Ha, S. Virtual synchronization technique with OS modeling for fast and time2accurate cosimulation [ A ]. In Proceedings of the Design Automation and Test in Europe [ C ]. New York :ACM Press, :, ,, :MPSoC. E2mail zju. edu. cn,, :MPSoC.

计算机系统应用 http://www.c-s-a.org.cn 2016 年第 25 卷第 1 期的编程语言 Giotto [9] 编写控制程序, 可以方便的控制程序的逻辑执行时间, 从而使得任务时间的依赖关系

计算机系统应用 http://www.c-s-a.org.cn 2016 年第 25 卷第 1 期的编程语言 Giotto [9] 编写控制程序, 可以方便的控制程序的逻辑执行时间, 从而使得任务时间的依赖关系 1 基于 PRET 的编程模型李晓飞, 陈香兰 ( 中国科学技术大学计算机学院, 合肥 230039) 摘要 : 时间可预测性在信息物理系统设计领域正变得越来越重要, 目前时间可预测性系统的设计分为编程模型和体系结构两个层次, 编程模型的研