查询 ADS8405 供应商 捷多邦, 专业 PCB 打样工厂,24 小时加急出货 ADS8405 SLAS427 DECEMBER BIT, 1.25-MSPS, UNIPOLAR PSEUDO-DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANA

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1 查询 供应商 捷多邦, 专业 PCB 打样工厂,24 小时加急出货 16-BIT, 1.25-MSPS, UNIPOLAR PSEUDO-DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE FEATURES APPLICATIONS Unipolar Pseudo-Differential Input, 0 V to V ref DWDM 16-Bit NMC at 1.25 MSPS Instrumentation ±2 LSB INL Max, -1/+1.5 LSB DNL High-Speed, High-Resolution, Zero Latency Data Acquisition Systems 86 db SNR, -90 db THD at 100 khz Input Transducer Interface Zero Latency Medical Instruments Internal V Reference Communications High-Speed Parallel Interface Single 5-V Analog Supply DESCRIPTION Wide I/O Supply: 2.7 V to 5.25 V The is a 16-bit, 1.25-MHz A/D converter Low Power: 155 mw at 1.25 MHz Typ with an internal V reference. The device in- Pin Compatible With ADS8411/8401 cludes a 16-bit capacitor-based SAR A/D converter with inherent sample and hold. The offers a 48-Pin TQFP Package full 16-bit interface and an 8-bit option where data is read using two 8-bit read cycles if necessary. 18-Bit Pseudo-Diff High Speed SAR Converter Family The has a unipolar pseudo-differential input. It is available in a 48-lead TQFP package and is characterized over the industrial -40 C to 85 C temperature range. Type/Speed 500 khz ~600 khz 750 khz 1 MHz 1.25 MHz 2 MHz 3 MHz 4 MHz 18-Bit Pseudo-Bipolar, Fully Diff ADS8383 ADS8381 ADS8380 (S) ADS8382 (S) 16-Bit Pseudo-Diff ADS8371 ADS8401/05 ADS Bit Pseudo-Bipolar, Fully Diff ADS8402/06 ADS Bit Pseudo-Diff ADS7890 (S) ADS Bit Pseudo-Diff ADS7886 ADS7881 REFOUT +IN IN REFIN + _ V Internal Reference CDAC SAR Comparator Clock Output Latches and 3-State Drivers Conversion and Control Logic BYTE 16-/8-Bit Parallel DATA Output Bus RESET CONVST BUSY CS RD Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Copyright 2004, Texas Instruments Incorporated

2 ORDERING INFORMATION (1) MAXIMUM MAXIMUM NO MISSING INTEGRAL DIFFERENTIAL CODES PACKAGE PACKAGE TEMPERATURE ORDERING MODEL LINEARITY LINEARITY RESOLUTION TYPE DESIGNATOR RANGE INFORMATION (LSB) (LSB) (BIT) IPFBT I 4 to +4 2 to Pin TQFP PFB 40 C to 85 C IPFBR IBPFBT IB 2 to +2 1 to Pin TQFP PFB 40 C to 85 C IBPFBR TRANSPORT MEDIA QUANTITY Tape and reel 250 Tape and reel 1000 Tape and reel 250 Tape and reel 1000 (1) For the most current specifications and package information, refer to our website at. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) +IN to IN to UNIT 0.4 V to +VA V 0.4 V to 0.5 V Voltage +VA to 0.3 V to 7 V +VBD to BDGND +VA to +VBD Digital input voltage to BDGND Digital output voltage to BDGND 0.3 V to 7 V 0.3 V to 2.55 V 0.3 V to +VBD V 0.3 V to +VBD V T A Operating free-air temperature range 40 C to 85 C T stg Storage temperature range 65 C to 150 C Junction temperature (T J max) 150 C TQFP package Power dissipation Lead temperature, soldering θ JA thermal impedance (T J Max T A )/θ JA 86 C/W Vapor phase (60 sec) 215 C Infrared (15 sec) 220 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2

3 SPECIFICATIONS T A = 40 C to 85 C, +VBD = 3 V or 5 V, V ref = V, f SAMPLE = 1.25 MHz (unless otherwise noted) ANALOG INPUT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Full-scale input voltage (1) +IN ( IN) 0 V ref V Absolute input voltage +IN 0.2 V ref IN Input capacitance 25 pf Input leakage current 0.5 na SYSTEM PERFORMANCE Resolution 16 Bits No missing codes I 15 IB 16 I 4 ±2 4 INL Integral linearity (2)(3) LSB IB 2 ±1 2 I 2 ±1 2 DNL Differential linearity LSB IB 1 ± I 3 ±1 3 mv E O Offset error (4) IB 1.5 ± mv I E G Gain error (4)(5) %FS IB Noise 60 µv RMS At FFFFh output code, +VA = 4.75 V DC Power supply rejection ratio 2 LSB to 5.25 V, V ref = V (4) SAMPLING DYNAMICS Conversion time ns Acquisition time 150 ns Throughput rate 1.25 MHz Aperture delay 2 ns Aperture jitter 25 ps Step response 100 ns Overvoltage recovery 100 ns DYNAMIC CHARACTERISTICS VIN = 4 V p-p at 100 khz 90 db THD Total harmonic distortion (6) VIN = 4 V p-p at 500 khz 88.5 db SNR Signal-to-noise ratio VIN = 4 V p-p at 100 khz 86 db SINAD Signal-to-noise + distortion VIN = 4 V p-p at 100 khz 85 db SFDR Spurious free dynamic range VIN = 4 V p-p at 100 khz 90 db VIN = 4 V p-p at 500 khz 88 db -3dB Small signal bandwidth 5 MHz EXTERNAL VOLTAGE REFERENCE INPUT Reference voltage at REFIN, V ref V Reference resistance (7) 500 kω V Bits (1) Ideal input span, does not include gain or offset error. (2) LSB means least significant bit (3) This is endpoint INL, not best fit. (4) Measured relative to an ideal full-scale input (+IN ( IN)) of V. (5) This specification does not include the internal reference voltage error and drift. (6) Calculated on the first nine harmonics of the input frequency. (7) Can vary ±20% 3

4 SPECIFICATIONS (continued) T A = 40 C to 85 C, +VBD = 3 V or 5 V, V ref = V, f SAMPLE = 1.25 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INTERNAL REFERENCE OUTPUT From 95% (+VA), with 1-µF storage Internal reference start-up time 120 ms capacitor V ref range IOUT = V Source current Static load 10 µa Line regulation +VA = 4.75 V to 5.25 V 0.6 mv Drift IOUT = 0 36 PPM/C DIGITAL INPUT/OUTPUT Logic family - CMOS V IH High-level input voltage I IH = 5 µa +VBD 1 +VBD V IL Low-level input voltage I IL = 5 µa V OH High-level output voltage I OH = 2 TTL loads +VBD 0.6 +VBD V OL Low-level output voltage I OL = 2 TTL loads Data format - straight binary POWER SUPPLY REQUIREMENTS Power supply voltage +VBD V +VA V +VA Supply current (8) f s = 1.25 MHz ma Power dissipation (8) f s = 1.25 MHz mw TEMPERATURE RANGE Operating free-air C (8) This includes only VA+ current. +VBD current is typically 1 ma with 5-pF load capacitance on output pins. V 4

5 TIMING CHARACTERISTICS All specifications typical at 40 C to 85 C, +VA = +VBD = 5 V (1)(2)(3) PARAMETER MIN TYP MAX UNIT t CONV Conversion time ns t ACQ Acquisition time 150 ns t pd1 CONVST low to BUSY high 40 ns t pd2 Propagation delay time, end of conversion to BUSY low 5 ns t w1 Pulse duration, CONVST low 20 ns t su1 Setup time, CS low to CONVST low 0 ns t w2 Pulse duration, CONVST high 20 ns CONVST falling edge jitter 10 ps t w3 Pulse duration, BUSY signal low Min(t ACQ ) ns t w4 Pulse duration, BUSY signal high 610 ns Hold time, first data bus data transition (RD low, or CS low for read t h1 40 ns cycle, or BYTE input changes) after CONVST low t d1 Delay time, CS low to RD low (or BUSY low to RD low when CS = 0) 0 ns t su2 Setup time, RD high to CS high 0 ns t w5 Pulse duration, RD low 50 ns t en Enable time, RD low (or CS low for read cycle) to data valid 20 ns t d2 Delay time, data hold from RD high 0 ns t d3 Delay time, BYTE rising edge or falling edge to data valid 2 20 ns t w6 Pulse duration, RD high 20 ns t w7 Pulse duration, CS high 20 ns Hold time, last RD (or CS for read cycle ) rising edge to CONVST t h2 50 ns falling edge t su3 Setup time, BYTE transition to RD falling edge 0 ns t h3 Hold time, BYTE transition to RD falling edge 0 ns t dis Disable time, RD high (CS high for read cycle) to 3-stated data bus 20 ns t d5 Delay time, end of conversion to MSB data valid 10 ns Byte transition setup time, from BYTE transition to next BYTE t su4 50 ns transition t d6 Delay time, CS rising edge to BUSY falling edge 50 ns t d7 Delay time, BUSY falling edge to CS rising edge 50 ns Setup time, from the falling edge of CONVST (used to start the valid t su(ab) conversion) to the next falling edge of CONVST (when CS = 0 and CONVST used to abort) or to the next falling edge of CS (when CS is ns used to abort) Setup time, falling edge of CONVST to read valid data (MSB) from t su5 MAX(t CONV ) + MAX(t d5 ) ns current conversion Hold time, data (MSB) from previous conversion hold valid from t h4 MIN(t CONV ) ns falling edge of CONVST (1) All input signals are specified with t r = t f = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (V IL + V IH )/2. (2) See timing diagrams. (3) All timings are measured with 20-pF equivalent loads on all data bits and BUSY pins. 5

6 TIMING CHARACTERISTICS All specifications typical at 40 C to 85 C, +VBD = 3 V (1)(2)(3) PARAMETER MIN TYP MAX UNIT t CONV Conversion time ns t ACQ Acquisition time 150 ns t pd1 CONVST low to BUSY high 50 ns t pd2 Propagation delay time, end of conversion to BUSY low 10 ns t w1 Pulse duration, CONVST low 20 ns t su1 Setup time, CS low to CONVST low 0 ns t w2 Pulse duration, CONVST high 20 ns CONVST falling edge jitter 10 ps t w3 Pulse duration, BUSY signal low Min(t ACQ ) ns t w4 Pulse duration, BUSY signal high 610 ns Hold time, first data bus transition (RD low, or CS low for read cycle, t h1 40 ns or BYTE input changes) after CONVST low t d1 Delay time, CS low to RD low (or BUSY low to RD low when CS = 0) 0 ns t su2 Setup time, RD high to CS high 0 ns t w5 Pulse duration, RD low 50 ns t en Enable time, RD low (or CS low for read cycle) to data valid 30 ns t d2 Delay time, data hold from RD high 0 ns t d3 Delay time, BYTE rising edge or falling edge to data valid 2 30 ns t w6 Pulse duration, RD high 20 ns t w7 Pulse duration, CS high 20 ns Hold time, last RD (or CS for read cycle ) rising edge to CONVST t h2 50 ns falling edge t su3 Setup time, BYTE transition to RD falling edge 0 ns t h3 Hold time, BYTE transition to RD falling edge 0 ns t dis Disable time, RD high (CS high for read cycle) to 3-stated data bus 30 ns t d5 Delay time, end of conversion to MSB data valid 20 ns Byte transition setup time, from BYTE transition to next BYTE t su4 50 ns transition t d6 Delay time, CS rising edge to BUSY falling edge 50 ns t d7 Delay time, BUSY falling edge to CS rising edge 50 ns Setup time, from the falling edge of CONVST (used to start the valid t su(ab) conversion) to the next falling edge of CONVST (when CS = 0 and CONVST used to abort) or to the next falling edge of CS (when CS is ns used to abort) Setup time, falling edge of CONVST to read valid data (MSB) from t su5 MAX(t CONV ) + MAX(t d5 ) ns current conversion Hold time, data (MSB) from previous conversion hold valid from t h4 MIN(t CONV ) ns falling edge of CONVST (1) All input signals are specified with t r = t f = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (V IL + V IH )/2. (2) See timing diagrams. (3) All timings are measured with 10-pF equivalent loads on all data bits and BUSY pins. 6

7 PIN ASSIGNMENTS PFB PACKAGE (TOP VIEW) BUSY BDGND +VBD DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 BDGND +VBD RESET BYTE CONVST RD CS +VA +VA REFM REFM VBD DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 +VA REFIN REFOUT NC +VA +IN -IN +VA +VA NC - No connection 7

8 Terminal Functions NAME NO. I/O DESCRIPTION 5, 8, 11, 12, 14, Analog ground 15, 44, 45 BDGND 25, 35 Digital ground for bus interface digital supply BUSY 36 O Status output. High when a conversion is in progress. BYTE 39 I Byte select input. Used for 8-bit bus reading. 0: No fold back 1: Low byte D[7:0] of the 16 most significant bits is folded back to high byte of the 16 most significant pins DB[15:8]. CONVST 40 I Convert start. The falling edge of this input ends the acquisition period and starts the hold period. CS 42 I Chip select. The falling edge of this input starts the acquisition period. Data Bus 8-Bit Bus 16-Bit Bus BYTE = 0 BYTE = 1 BYTE = 0 DB15 16 O D15 (MSB) D7 D15 (MSB) DB14 17 O D14 D6 D14 DB13 18 O D13 D5 D13 DB12 19 O D12 D4 D12 DB11 20 O D11 D3 D11 DB10 21 O D10 D2 D10 DB9 22 O D9 D1 D9 DB8 23 O D8 D0 (LSB) D8 DB7 26 O D7 All ones D7 DB6 27 O D6 All ones D6 DB5 28 O D5 All ones D5 DB4 29 O D4 All ones D4 DB3 30 O D3 All ones D3 DB2 31 O D2 All ones D2 DB1 32 O D1 All ones D1 DB0 33 O D0 (LSB) All ones D0 (LSB) IN 7 I Inverting input channel +IN 6 I Noninverting input channel NC 3 No connection REFIN 1 I Reference input REFM 47, 48 I Reference ground REFOUT 2 O Reference output. Add 1-µF capacitor between the REFOUT pin and REFM pin when the internal reference is used. RESET 38 I Current conversion is aborted and output latches are cleared (set to zeros) when this pin is asserted low. RESET works independantly of CS. RD 41 I Synchronization pulse for the parallel output. When CS is low, this serves as the output enable and puts the previous conversion result on the bus. +VA 4, 9, 10, 13, 43, Analog power supplies, 5-V dc 46 +VBD 24, 34, 37 Digital power supply for bus 8

9 TIMING DIAGRAMS t w1 CONVST (used in normal conversion) t cycle t w2 CONVST (used in ABORT) t su(ab) t su(ab) t pd1 t w4 t pd2 t pd1 BUSY t w3 t su1 t d7 t w7 CS CONVERT t d6 t CONV t CONV SAMPLING (When CS Toggle) t ACQ BYTE t su4 t h1 t d1 t su2 RD t h2 Data to be read Previous Conversion Invalid Current Conversion Invalid DB[15:8] DB[7:0] t h4 t su5 t en D [15:8] D [7:0] D [7:0] t dis Signal internal to device Figure 1. Timing for Conversion and Acquisition Cycles With CS and RD Toggling 9

10 TIMING DIAGRAMS (continued) t w1 CONVST (used in normal conversion) t cycle t w2 CONVST (used in ABORT) t su(ab) tsu(ab) t pd1 t w4 t pd2 BUSY t w3 t su1 t d7 t w7 CS CONVERT t d6 t CONV t CONV SAMPLING (When CS Toggle) t ACQ BYTE t h1 t su4 t en t h2 RD = 0 t t en t dis Invalid dis Invalid Data to be read Previous Conversion Current Conversion t h4 t su5 Previous Repeated DB[15:8] D [15:8] D [7:0] D [15:8] D [15:8] DB[7:0] Previous D [7:0] D [7:0] Repeated D [7:0] Signal internal to device t en Figure 2. Timing for Conversion and Acquisition Cycles With CS Toggling, RD Tied to BDGND 10

11 TIMING DIAGRAMS (continued) t w1 CONVST (used in normal conversion) t cycle t w2 CONVST (used in ABORT) t su(ab) tsu(ab) t pd1 t w4 t pd2 t pd1 BUSY t w3 CS = 0 CONVERT t CONV t CONV SAMPLING (When CS = 0) t (ACQ) BYTE t h1 t su4 t h2 RD t en t dis Invalid Invalid Data to be read Previous Conversion Current Conversion t h4 t su5 DB[15:8] D [15:8] D [7:0] DB[7:0] D [7:0] Signal internal to device Figure 3. Timing for Conversion and Acquisition Cycles With CS Tied to BDGND, RD Toggling 11

12 TIMING DIAGRAMS (continued) t w1 CONVST (used in normal conversion) t cycle t w2 CONVST (used in ABORT) t su(ab) tsu(ab) BUSY t pd1 t w4 t pd2 t w3 t pd1 t pd2 CS = 0 CONVERT t CONV t CONV SAMPLING (When CS Toggle) t ACQ t h1 t h1 BYTE RD = 0 t d3 t d5 t d3 t d5 t su5 t h4 t su5 t d3 t h4 DB[15:8] Previous MSB Invalid MSB LSB MSB Invalid DB[7:0] Previous Previous LSB LSB Invalid MSB LSB MSB Invalid Signal internal to device Figure 4. Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND Auto Read CS RD BYTE t su4 t en t dis t en t d3 t dis DB[15:0] Valid Valid Valid Figure 5. Detailed Timing for Read Cycles 12

13 TYPICAL CHARACTERISTICS At 40 C to 85 C, +VBD = 5 V, REFIN = V (internal reference used) and f sample = 1.25 MHz (unless otherwise noted) HISTOGRAM (DC Code Spread) HALF SCALE CONVERSIONS VBD = 3.3 V, T A = 25 C, Code = SNR Signal-to-Noise Ratio db SIGNAL-TO-NOISE RATIO FREE-AIR TEMPERATURE 85.6 f i = 50 khz, Full Scale Input, VBD = 3 V, Int Ref = V T A Free-Air Temperature C Figure 6. Figure 7. SINAD Signal-to-Noise and Distortion db SIGNAL-TO-NOISE AND DISTORTION FREE-AIR TEMPERATURE f i = 50 khz, Full Scale Input, 82 +VBD = 3 V, Int Ref = V T A Free-Air Temperature C ENOB Effective Number of Bits Bits EFFECTIVE NUMBER OF BITS FREE-AIR TEMPERATURE f i = 50 khz, Full Scale Input, +VBD = 3 V, Int Ref = V T A Free-Air Temperature C Figure 8. Figure 9. 13

14 TYPICAL CHARACTERISTICS (continued) SPURIOUS FREE DYNAMIC RANGE FREE-AIR TEMPERATURE TOTAL HARMONIC DISTORTION FREE-AIR TEMPERATURE SFDR Spurious Free Dynamic Range db f i = 50 khz, Full Scale Input, +VBD = 3 V, Int Ref = V T A Free-Air Temperature C THD Total Harmonic Distortion db f i = 50 khz, Full Scale Input, +VBD = 3 V, Int Ref = V T A Free-Air Temperature C Figure 10. Figure 11. SNR Signal-to-Noise Ratio db SIGNAL-TO-NOISE RATIO INPUT FREQUENCY 86.3 f 86.2 i = 50 khz, Full Scale Input, VBD = 3 V, Int Ref = V f i Input Frequency khz ENOB Effective Number of Bits Bits EFFECTIVE NUMBER OF BITS INPUT FREQUENCY f i = 50 khz, Full Scale Input, +VBD = 3 V, Int Ref = V f i Input Frequency khz Figure 12. Figure 13. SINAD Signal-to-Noise and Distortion db SIGNAL-TO-NOISE AND DISTORTION INPUT FREQUENCY f i = 50 khz, Full Scale Input, +VBD = 3 V, Int Ref = V f i Input Frequency khz SFDR Spurious Free Dynamic Range db SPURIOUS FREE DYNAMIC RANGE INPUT FREQUENCY f i = 50 khz, Full Scale Input, +VBD = 3 V, Int Ref = V f i Input Frequency khz Figure 14. Figure

15 TYPICAL CHARACTERISTICS (continued) THD Total Harmonic Distortion db TOTAL HARMONIC DISTORTION INPUT FREQUENCY f i = 50 khz, Full Scale Input, +VBD = 3 V, Int Ref = V f i Input Frequency khz I CC Supply Current ma SUPPLY CURRENT SAMPLE RATE +VBD = 3.3 V, T A = 25 C, Int Ref = V Sample Rate KSPS Figure 16. Figure 17. GAIN ERROR SUPPLY VOLTAGE OFFSET ERROR SUPPLY VOLTAGE VBD = 3.3 V, T A = 25 C, Ext Ref = V VBD = 3.3 V, T A = 25 C, Ext Ref = V Gain Error mv Offset Voltage mv V CC Supply Voltage V V CC Supply Voltage V Figure 18. Figure 19. Internal Reference Output Voltage V INTERNAL VOLTAGE REFERENCE FREE-AIR TEMPERATURE +VA = 5 V +VBD = 3.3 V T A Free-Air Temperature C Gain Error mv GAIN ERROR FREE-AIR TEMPERATURE +VBD = 3.3 V, Ext Ref = V T A Free-Air Temperature C Figure 20. Figure

16 TYPICAL CHARACTERISTICS (continued) OFFSET ERROR FREE-AIR TEMPERATURE SUPPLY CURRENT FREE-AIR TEMPERATURE Offset Voltage mv VBD = 3.3 V, Ext Ref = V I CC Supply Current ma VBD = 3.3 V T A Free-Air Temperature C T A Free-Air Temperature C Figure 22. Figure 23. DNL Differential Nonlinearity Bits DIFFERENTIAL NONLINEARITY FREE-AIR TEMPERATURE Min Max +VBD = 3.3 V, Ext Ref = V T A Free-Air Temperature C INL Integral Nonlinearity Bits INTEGRAL NONLINEARITY FREE-AIR TEMPERATURE Max +VBD = 3.3 V, Ext Ref = V Min T A Free-Air Temperature C Figure 24. Figure DIFFERENTIAL NONLINEARITY REFERENCE VOLTAGE 2 INTEGRAL NONLINEARITY REFERENCE VOLTAGE DNL Differential Nonlinearity Bits VBD = 3.3 V, Ext Ref = Varied Min Max INL Integral Nonlinearity Bits Max +VBD = 3.3 V, Ext Ref = Varied Min V REF Reference Voltage V V REF Reference Voltage V Figure 26. Figure

17 TYPICAL CHARACTERISTICS (continued) DNL LSBs DNL +VBD = 5 V, T A = 25 C, Ext Ref = V Code Figure 28. INL LSBs INL +VBD = 5 V, T A = 25 C, Ext Ref = V Code Figure 29. Amplitude FFT +VBD = 3.3 V, REF Points, f i = 100 khz, f s = 1.25 MHz, T A = 25 C, Int Ref = V Frequency khz Figure

18 APPLICATION INFORMATION MICROCONTROLLER INTERFACING to 8-Bit Microcontroller Interface Figure 31 shows a parallel interface between the and a typical microcontroller using the 8-bit data bus. The BUSY signal is used as a falling-edge interrupt to the microcontroller. Analog 5 V 0.1 µf 1 µf 10 µf 0.1 µf Ext Ref Input Analog Input Micro Controller GPIO GPIO P[7:0] RD GPIO INT CS +VA REFIN BYTE DB[15:8] RD CONVST BUSY REFM +IN IN BDGND +VBD BDGND 0.1 µf Digital 3 V Figure 31. Application Circuitry (Using an External Reference) Analog 5 V 0.1 µf 10 µf 0.1 µf 1 µf +VA REFOUT REFIN REFM Figure 32. Using the Internal Reference PRINCIPLES OF OPERATION The is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The architecture is based on charge redistribution, which inherently includes a sample/hold function. See Figure 31 for the application circuit for the. The conversion clock is generated internally. The conversion time of 650 ns is capable of sustaining a 1.25-MHz throughput. 18

19 PRINCIPLES OF OPERATION (continued) REFERENCE ANALOG INPUT V 0.1 F The analog input is provided to two input pins: +IN and IN. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. The can operate with an external reference with a range from 2.5 V to 4.2 V. A V internal reference is included. When an internal reference is used, pin 2 (REFOUT) should be connected to pin 1 (REFIN) with a 0.1-µF decoupling capacitor and a 1-µF storage capacitor between pin 2 (REFOUT) and pins 47 and 48 (REFM) (see Figure 32). The internal reference of the converter is double buffered. If an external reference is used, the second buffer provides isolation between the external reference and the CDAC. This buffer is also used to recharge all of the capacitors of the CDAC during conversion. Pin 2 (REFOUT) can be left unconnected (floating) if an external reference is used. When the converter enters hold mode, the voltage difference between the +IN and -IN inputs is captured on the internal capacitor array. The voltage on the IN input is limited between 0.2 V and 0.2 V, allowing the input to reject small signals which are common to both the +IN and IN inputs. The +IN input has a range of 0.2 V to V ref V. The input span (+IN ( IN)) is limited to 0 V to V ref. The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and source impedance. Essentially, the current into the charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (25 pf) to an 16-bit settling level within the acquisition time (150 ns) of the device. When the converter goes into hold mode, the input impedance is greater than 1 GΩ. Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the +IN and IN inputs and the span (+IN ( IN)) should be within the limits specified. Outside of these ranges, the converter's linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass filters should be used. Care should be taken to ensure that the output impedance of the sources driving the +IN and IN inputs are matched. If this is not observed, the two inputs could have different setting times. This may result in offset error, gain error, and linearity error which varies with temperature and input voltage. A typical input circuit using TI's THS4031 is shown in Figure F G = V IN _ THS F pf +IN IN 0.1 F 15 V Figure 33. Using the THS4031 with the 19

20 PRINCIPLES OF OPERATION (continued) DIGITAL INTERFACE Timing And Control See the timing diagrams in the specifications section for detailed information on timing signals and their requirements. The uses an internal oscillator generated clock which controls the conversion rate and in turn the throughput of the converter. No external clock input is required. Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum requirement has been met, the CONVST pin can be brought high) while CS is low. The switches from the sample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of this signal is important to the performance of the converter. The BUSY output is brought high after CONVST goes low. BUSY stays high throughout the conversion process and returns low when the conversion has ended. Sampling starts as soon as the conversion is over when CS is tied low or starts with the falling edge of CS when BUSY is low. Both RD and CS can be high during and before a conversion with one exception (CS must be low when CONVST goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the parallel output bus with the conversion. Reading Data The outputs full parallel data in straight binary format as shown in Table 1. The parallel output is active when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of CONVST. This is 50 ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data read should be attempted within this zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTE is used for multiword read operations. BYTE is used whenever lower bits of the converter result are output on the higher byte of the bus. Refer to Table 1 for ideal output codes. Table 1. Ideal Input Voltages and Output Codes DESCRIPTION ANALOG VALUE DIGITAL OUTPUT Full scale range +V ref STRAIGHT BINARY Least significant bit (LSB) (+V ref )/65536 BINARY CODE HEX CODE Full scale (+V ref ) 1 LSB FFFF Midscale (+V ref )/ Midscale 1 LSB (+V ref )/2 1 LSB FFF Zero 0 V The output data is a full 16-bit word (D15 D0) on the DB15 DB0 pins (MSB-LSB) if BYTE is low. The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB15 DB8. In this case two reads are necessary: the first as before, leaving BYTE low and reading the 8 most significant bits on pins DB15 DB8, then bringing BYTE high. When BYTE is high, the low bits (D7 D0) appear on pins DB15 D8. These multiword read operations can be done with multiple active RD (toggling) or with RD tied low for simplicity. BYTE Conversion Data Readout DB15 DB8 Pins DATA READ OUT DB7 DB0 Pins High D7 D0 All one's Low D15 D8 D7-D0 20

21 RESET POWER-ON INITIALIZATION LAYOUT RESET is an asynchronous active low input signal (that works independently of CS). Minimum RESET low time is 25 ns. The current conversion is aborted no later than 50 ns after the converter is in reset mode. In addition, all output latches are cleared (set to zero's) after RESET. The converter goes back to normal operation mode no later than 20 ns after the RESET input is brought high. The converter starts the first sampling period 20 ns after the rising edge of RESET. Any sampling period except for the one immediately after a RESET is started with the falling edge of the previous BUSY signal or the falling edge of CS, whichever is later. Another way to reset the device is through the use of the combination of CS and CONVST. This is useful when the dedicated RESET pin is tied to the system reset but there is a need to abort only the conversion in a specific converter. Since the BUSY signal is held high during the conversion, either one of these conditions triggers an internal self-clear reset to the converter just the same as a reset via the dedicated RESET pin. The reset does not have to be cleared as for the dedicated RESET pin. A reset can be started with either of the two following steps. Issue a CONVST when CS is low and a conversion is in progress. The falling edge of CONVST must satisfy the timing as specified by the timing parameter t su(ab) specified in the timing characteristics table to ensure a reset. The falling edge of CONVST starts a reset. The timing is the same as a reset using the dedicated RESET pin except the instance of the falling edge is replaced by the falling edge of CONVST. Issue a CS while a conversion is in progress. The falling edge of CS must satisfy the timing as specified by the timing parameter t su(ab) specified in the timing characteristics table to ensure a reset. The falling edge of CS causes a reset. The timing is the same as a reset using the dedicated RESET pin except the instance of the falling edge is replaced by the falling edge of CS. RESET is not required after power on. An internal power-on reset circuit generates the reset. To ensure that all of the registers are cleared, the three conversion cycles must be given to the converter after power on. For optimum performance, care should be taken with the physical layout of the circuitry. As the offers single-supply operation, it is often used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to achieve good performance from the converter. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving any single conversion for an n-bit SAR converter, there are at least n windows in which large external transient voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, or high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. On average, the draws very little current from an external reference, as the reference voltage is internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypass capacitor or capacitors without oscillation. A 0.1-µF bypass capacitor and a 1-µF storage capacitor are recommended from pin 1 (REFIN) directly to pin 48 (REFM). REFM and should be shorted on the same ground plane under the device. The and BDGND pins should be connected to a clean ground point. In all cases, this should be the analog ground. Avoid connections which are close to the grounding point of a microcontroller or digital signal processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal layout consists of an analog ground plane dedicated to the converter and associated analog circuitry. 21

22 As with the connections, +VA should be connected to a 5-V power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. Power to the should be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the device as possible. See Table 2 for the placement of the capacitor. In addition, a 1-µF to 10-µF capacitor is recommended. In some situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors all designed to essentially low-pass filter the 5-V supply, removing the high frequency noise. Table 2. Power Supply Decoupling Capacitor Placement POWER SUPPLY PLANE SUPPLY PINS CONVERTER ANALOG SIDE CONVERTER DIGITAL SIDE (4,5), (8,9), (10,11), (13,15), Pin pairs that require shortest path to decoupling capacitors (24,25), (34, 35) (43,44), (45,46) Pins that require no decoupling 12,

23 PACKAGE OPTION ADDENDUM 10-Feb-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty IBPFBR ACTIVE TQFP PFB Green (RoHS & no Sb/Br) IBPFBRG4 ACTIVE TQFP PFB Green (RoHS & no Sb/Br) IBPFBT ACTIVE TQFP PFB Green (RoHS & no Sb/Br) IBPFBTG4 ACTIVE TQFP PFB Green (RoHS & no Sb/Br) IPFBR ACTIVE TQFP PFB Green (RoHS & no Sb/Br) IPFBRG4 ACTIVE TQFP PFB Green (RoHS & no Sb/Br) IPFBT ACTIVE TQFP PFB Green (RoHS & no Sb/Br) IPFBTG4 ACTIVE TQFP PFB Green (RoHS & no Sb/Br) Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

24 MECHANICAL DATA MTQF019A JANUARY 1995 REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,50 0,08 M 0, ,13 NOM 1,05 0,95 5,50 TYP 7,20 6,80 9,20 8,80 SQ SQ 0,05 MIN 0,25 Gage Plane 0 7 Seating Plane 0,75 0,45 1,20 MAX 0, / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

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