查询 SN65LVCP23 供应商捷多邦, 专业 PCB 打样工厂,24 小时加急出货 SLLS554B NOVEMBER 2002 REVISED JUNE 2003 FEATURES High Speed 2x2 LVPECL Crosspoint Switch LVDS

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查询 SN65LVCP23 供应商捷多邦, 专业 PCB 打样工厂,24 小时加急出货 FEATURES High Speed 2x2 LVPECL Crosspoint Switch LVDS Crosspoint Switch Available in SN65LVCP22 50 ps (Typ), of Peak-to-Peak Jitter With PRBS = 2 23 1

Transmission Paths HDTV Video Routing Base Stations Protection Switching for Serial Backplanes Network Switches/Routers Optical Networking Line Cards/Switches Clock Distribution DESCRIPTION The

1 查询 SN65LVCP23 供应商捷多邦, 专业 PCB 打样工厂,24 小时加急出货 FEATURES High Speed 2x2 LVPECL Crosspoint Switch LVDS Crosspoint Switch Available in SN65LVCP22 50 ps (Typ), of Peak-to-Peak Jitter With PRBS = Pattern Output (Channel-to-Channel) Skew Is ps (Typ), 50 ps (Max) Configurable as 2:1 Mux, 1:2 Demux, Repeater or 1:2 Signal Splitter Inputs Accept LVDS, LVPECL, and CML Signals Fast Switch Time of 1.7 ns (Typ) Fast Propagation Delay of 0.75 ns (Typ) 16 lead SOIC and TSSOP Packages Operating Temperature: 40 C to 85 C APPLICATIONS Gigabit Ethernet Redundant Transmission Paths Gigabit Interface Converters (GBICs) Fibre Channel Redundant Transmission Paths HDTV Video Routing Base Stations Protection Switching for Serial Backplanes Network Switches/Routers Optical Networking Line Cards/Switches Clock Distribution DESCRIPTION The SN65LVCP23 is a 2x2 LVPECL crosspoint switch. The dual channels incorporate wide common-mode (0 V to 4 V) receivers, allowing for the receipt of LVDS, LVPECL, and CML signals. The dual outputs are LVPECL drivers to provide high-speed operation. The SN65LVCP23 provides a single device supporting 2:2 buffering (repeating), 1:2 splitting, 2:1 multiplexing, 2x2 switching, and LVDS/CML to LVPECL level translation on each channel. The flexible operation of the SN65LVCP23 provides a single device to support the redundant serial bus transmission needs (working and protection switching cards) of fault-tolerant switch systems found in optical networking, wireless infrastructure, and data communications systems. TI offers an additional gigibit repeater/ translator in the SN65LVDS1. The SN65LVCP23 uses a fully differential data path to ensure low-noise generation, fast switching times, low pulse width distortion, and low jitter. Output channel-to-channel skew is less than ps (typ) and 50 ps (max) to ensure accurate alignment of outputs in all applications. Both SOIC and TSSOP package options are available. 1.3 Gbps PRBS VCC = 3.3 V VID = 0 mv, VIC = 1.2 V Vertical Scale=400mV/div OUTPUTS OPERATING SIMULTANEOUSLY 650 MHz OUTPUT 1 OUTPUT 2 Horizontal Scale = 0 ps Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 02 03, Texas Instruments Incorporated

2 2 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PACKAGE DESIGNATOR PART NUMBER(1) SYMBOLIZATION SOIC SN65LVCP23D LVCP23 TSSOP SN65LVCP23PW LVCP23 (1) Add the suffix R for taped and reeled carrier PACKAGE DISSIPATION RATINGS PACKAGE CIRCUIT BOARD MODEL TA 25 C POWER RATING DERATING FACTOR(1) ABOVE TA = 25 C TA = 85 C POWER RATING SOIC (D) High-K(2) 1361 mw 13.9 mw/ C 544 mw TSSOP (PW) High-K(2) 74 mw.7 mw/ C 430 mw (1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. (2) In accordance with the High-K thermal metric definitions of EIA/JESD51-7. THERMAL CHARACTERISTICS θjb θjc PD PARAMETER TEST CONDITIONS VALUE UNITS D 15.7 C/W Junction-to-board to thermal resistance PW 22.1 C/W D 26.1 C/W Junction-to-case to case thermal resistance PW 17.3 C/W Device power dissipation Typical VCC = 3.3 V, TA =25 C, 2 Gbps 165 mw Maximum VCC = 3.6 V, TA = 85 C, 2 Gbps 234 mw FUNCTION TABLE SEL0 SEL1 OUT0 OUT1 FUNCTION 0 0 IN0 IN0 1:2 Splitter 0 1 IN0 IN1 Repeater 1 0 IN1 IN0 Switch 1 1 IN1 IN1 1:2 Splitter FUNCTIONAL BLOCK DIAGRAM OUT 0 OUT 1 EN 0 EN 1 SEL 1 SEL IN 0 IN 1

3 3 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS IN + IN INPUTS VCC 400 Ω 7 V 7 V SEL, EN 300 kω 7 V OUTPUTS VCC R VCC VCC R R OUT + VCC 7 V OUT 7 V

4 4 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) Supply voltage(2) range, VCC CMOS/TTL input voltage (ENO, EN1, SEL0, SEL1) Receiver Input voltage (IN+, IN ) LVPECL driver output voltage (OUT+, OUT ) Output current Storage temperature range Continuous Surge UNITS 0.5 V to 4 V 0.5 V to 4 V 0.7 V to 4.3 V 0.5 V to 4 V 50 ma 0 ma 65 C to 125 C Lead temperature 1,6 mm (1/16 inch) from case for seconds 235 C Continuous power dissipation See Dissipation Rating Table Human body model(3) All pins ±5 kv Electrostatic t ti discharge Charged-device mode(4) All pins ±500 V (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminals. (3) Tested in accordance with JEDEC Standard 22, Test Method A114-A. (4) Tested in accordance with JEDEC Standard 22, Test Method C1. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Supply voltage, VCC V Receiver input voltage 0 4 V Junction temperature 125 C Operating free-air temperature, TA (1) C Magnitude of differential input voltage VID V (1) Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded.

5 5 INPUT ELECTRICAL CHARACTERISTICS over recommended operatingconditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT CMOS/TTL DC SPECIFICATIONS (EN0, EN1, SEL0, SEL1) VIH High-level input voltage 2 VCC V VIL Low-level input voltage GND 0.8 V IIH High-level input current VIN = 3.6 V or 2.0 V, Vcc= 3.6 V ±3 ± µa IIL Low-level input current VIN = 0.0 V or 0.8 V, Vcc= 3.6 V ±1 ± µa VCL Input clamp voltage ICL = 18 ma V LVPECL OUTPUT SPECIFICATIONS (OUT0, OUT1) VOH Output high voltage(2) See Figure mv VOL Output low voltage(2) See Figure mv V OD Differential output voltage RL = to VTT = VCC 2.0 V, mv See Figure 2 CO Differential output capacitance VI = 0.4 sin(4e6πt) V 3 pf RECEIVER DC SPECIFICATIONS (IN0, IN1) VTH Positive-going differential input voltage threshold See Figure 1 and Table 1 0 mv VTL Negative-going differential input voltage threshold See Figure 1 and Table 1 0 mv VID(HYS) Differential input voltage hysteresis 25 mv VCMR Common-mode voltage range VID = 0 mv, VCC = 3.0 V to 3.6 V V IIN Input current VIN = 4 V, VCC = 3.6 V or 0.0 ±1 ± VIN = 0V, VCC = 3.6V or 0.0 ±1 ± CIN Differential input capacitance VI = 0.4 sin (4E6πt) V 1 pf SUPPLY CURRENT ICCD DC supply current No load ma (1) All typical values are at 25 C and with a 3.3 V supply. (2) Outputs are terminated through a 50-Ω resistor to VCC 2 V; PECL level specifictions are refrenced to VCC and track 1:1 with variation of VCC. µaa

6 6 SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tset Input to SEL setup time Figure ns thold Input to SEL hold time Figure ns tswitch SEL to switched output Figure ns tphkl Disable time, high-level-to-known LOW Figure ns tpklh Enable time, known LOW-to-high-level output Figure ns tlht Differential output signal rise time (% 80%)(1) Figure ps thlt Differential output signal fall time (% 80%)(1) Figure ps VID = 0 mv, 50% duty cycle, VCM = 1.2 V, 650 MHz tjit LVDS data path peak to-peak jitter VID = 0 mv, PRBS = data pattern and K28.5 (001111), VCM = 1.2 V at 1.3 Gbps ps 50 0 ps tjrms Added random jitter (rms) VID = 0 mv, 50% duty cycle, VCM = 1.2 V, 650 MHz psrms tplhd Propagation delay time, low-to-high-level output(1) See Figure ps tphld Propagation delay time, high-to-low-level output(1) See Figure ps tskew Pulse skew ( tplhd tphld )(2) Figure 3 0 ps tccs Output channel-to-channel skew, splitter mode. Figure 3 50 ps f MAX Maximum operating frequency(3) 1 GHz (1) Input: VIC = 1.2 V, VID = 0 mv, 50% duty cycle, 1 MHz, tr/tf = 500 ps (2) tskew is the magnitude of the time difference between the tplhd and tphld of any output of a single device. (3) Signal generator conditions: 50% duty cycle, tr or tf 0 ps (% to 90%), transmitter output criteria: duty cycle = 45% to 55% V OD 300 mv. PIN ASSIGNMENTS D or PW PACKAGE (TOP VIEW) SEL1 SEL0 IN0+ IN0 VCC IN1+ IN1 VCC EN0 EN1 OUT0+ OUT0 GND OUT1+ OUT1 GND

7 7 PARAMETER MEASUREMENT INFORMATION IIN+ IN+ OUT + IN+ +IN 2 VIC VID VIN+ VIN IIN IN VOD OUT VOZ VOY VOUT++VOUT 2 Figure 1. Voltage and Current Definitions Driver Device Y Z VOD Receiver Device VTT = VCC 2 V Figure 2. Typical Termination for LVPECL Output Driver IN+ OUT+ VID VIN+ VIN IN OUT 1 pf VOUT VOUT+ V OD VTT VTT VIN+ 1.4 V VIN 1 V VID 0.4 V 0 V 0.4 V tphld tplhd +VOD VOD 80% % 0 V Vdiff = (OUT+) (OUT ) thlt tlht NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf 0.25 ns, pulse-repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± ns; CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. Figure 3. Timing Test Circuit and Waveforms

8 8 1 V or 1.4 V 1.2 V EN OUT+ OUT 1 pf VOUT+ VOUT VTT VTT EN 3 V 1.5 V 0 V +VOD 0 V VOD tphkl tpklh Vdiff = (OUT+) (OUT ) NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf 1 ns, pulse-repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. Figure 4. Enable and Disable Time Circuit and Definitions Table 1. Receiver Input Voltage Threshold Test APPLIED VOLTAGES RESULTING DIFFERENTIAL INPUT VOLTAGE RESULTING COMMON- MODE INPUT VOLTAGE OUTPUT VIA VIB VID VIC 1.25 V 1.15 V 0 mv 1.2 V H 1.15 V 1.25 V 0 mv 1.2 V L 4.0 V 3.9 V 0 mv 3.95 V H 3.9 V 4. 0 V 0 mv 3.95 V L 0.1 V 0.0 V 0 mv 0.05 V H 0.0 V 0.1 V 0 mv 0.05 V L 1.7 V 0.7 V 00 mv 1.2 V H 0.7 V 1.7 V 00 mv 1.2 V L 4.0 V 3.0 V 00 mv 3.5 V H 3.0 V 4.0 V 00 mv 3.5 V L 1.0 V 0.0 V 00 mv 0.5 V H 0.0 V 1.0 V 00 mv 0.5 V L H = high level, L = low level

9 9 IN0 IN1 SEL tset thold OUT IN0 IN1 tswitch EN IN0 IN1 SEL tset thold OUT IN1 IN0 tswitch EN NOTE: tset and thold times specify that data must be in a stable state before and after mux control switches. Figure 5. Input to Select for Both Rising and Falling Edge Setup and Hold Times

10 TYPICAL CHARACTERISTICS Supply Current ma I CC SUPPLY CURRENT FREQUENCY VIC = 1.2 V, VID = 0 mv Output = Loaded f Frequency MHz t pd Propagation Delay Time ps PROPAGATION DELAY TIME FREE-AIR TEMPERATURE VCc = V, VIC = 1.2 V, VID = 300 mv Input = 1 MHz tplh tphl TA Free-Air Temperature C Peak-to-Peak Jitter ps PEAK-TO-PEAK JITTER FREQUENCY VIC = 400 mv, Input = Clock 800 mv 500 mv 300 mv f Frequency MHz Figure 6 Figure 7 Figure 8 Peak-to-Peak Jitter ps PEAK-TO-PEAK JITTER DATA RATE VIC = 400 mv, Input = PRBS mv 800 mv 500 mv Data Rate Mbps Peak-to-Peak Jitter ps PEAK-TO-PEAK JITTER FREQUENCY VIC = 1.2 V, Input = Clock 500 mv 800 mv mv f Frequency MHz Peak-to-Peak Jitter ps PEAK-TO-PEAK JITTER DATA RATE VIC = 1.2 V Input = PRBS mv 300 mv 500 mv Data Rate Mbps Figure 9 Figure Figure 11 Peak-to-Peak Jitter ps PEAK-TO-PEAK JITTER FREQUENCY VIC = 3.3 V, Input = Clock 500 mv 800 mv 500 mv f Frequency MHz Peak-to-Peak Jitter ps PEAK-TO-PEAK JITTER DATA RATE 300 mv 500 mv 800 mv VIC = 3.3 V, Input = PRBS Data Rate Mbps Differential Output Voltage mv V OD DIFFERENTIAL OUTPUT VOLTAGE FREQUENCY VIC = 1.2 V, 40 VID = 0 mv Added Random Jitter f Frequency MHz 30 Period Jitter ps Figure 12 Figure 13 Figure 14

11 11 Peak-to-Peak Jitter ps PEAK-TO-PEAK JITTER DATA RATE VIC = 1.2 V, VID = 0 mv Input = PRBS Data Rate Mbps Figure 15

12 12 APPLICATION INFORMATION TYPICAL APPLICATION CIRCUITS (ECL, PECL, LVDS, ETC.) 3.3 V or 5 V ECL 3.3 V A B SN65LVCP23 VTT VTT = VCC 2 V Figure 16. Low-Voltage Positive Emitter-Coupled Logic (LVPECL) 3.3 V 3.3 V 3.3 V SN65LVCP23 A CML B 3.3 V Figure 17. Current-Mode Logic (CML) ECL 3.3 V 3.3 V A SN65LVCP kω 1.5 kω B VTT 3.3 V VTT = VCC 2 V Figure 18. Single-Ended (LVPECL) LVDS 3.3 V or 5 V 3.3 V A 0 Ω B SN65LVCP23 Figure 19. Low-Voltage Differential Signaling (LVDS)

13 13 IN0 + IN0 IN1 + IN1 OUT0 + OUT0 OUT1 + OUT1 Figure. 2 x 2 Crosspoint OUT0 + IN + (1 or 2) IN OUT0 OUT1 + OUT1 Figure 21. 1:2 Spitter IN0 + IN0 IN1 + IN1 OUT0 + OUT0 OUT1 + OUT1 Figure 22. Dual Repeater IN0 + IN0 IN1 + OUT + MUX (1 or 2) OUT IN1 Figure 23. 2:1 MUX

14 MECHANICAL DATA MSOI002B JANUARY 1995 REVISED SEPTEMBER 01 D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 8 PINS SHOWN (1,27) 0.0 (0,51) (0,35) 0.0 (0,25) (6,) (5,80) (0,) NOM (4,00) (3,81) Gage Plane 1 4 A (0,25) (1,12) (0,40) Seating Plane (1,75) MAX 0.0 (0,25) (0,) (0,) DIM PINS ** A MAX (5,00) (8,75) (,00) A MIN (4,80) (8,55) (9,80) /E 09/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed (0,15). D. Falls within JEDEC MS-012

15 MECHANICAL DATA MTSS001C JANUARY 1995 REVISED FEBRUARY 1999 PW (R-PDSO-G**) 14 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,65 0, M 0, ,50 4,30 6,60 6, 0,15 NOM Gage Plane 1 A ,25 0,75 0,50 1, MAX 0,15 0,05 Seating Plane 0, DIM PINS ** A MAX 3, 5, 5, 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9, /F 01/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

16 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products & application solutions: Products Applications Amplifiers amplifier.ti.com Audio /audio Data Converters dataconverter.ti.com Automotive /automotive DSP dsp.ti.com Broadband /broadband Interface interface.ti.com Digital Control /digitalcontrol Logic logic.ti.com Military /military Power Mgmt power.ti.com Optical Networking /opticalnetwork Microcontrollers microcontroller.ti.com Security /security Telephony /telephony Video & Imaging /video Wireless /wireless Mailing Address: Texas Instruments Post Office Box Dallas, Texas Copyright 03, Texas Instruments Incorporated

Pin Configurations Figure2. Pin Configuration of FS2012 (Top View) Table 1 Pin Description Pin Number Pin Name Description 1 GND 2 FB 3 SW Ground Pin.

Pin Configurations Figure2. Pin Configuration of FS2012 (Top View) Table 1 Pin Description Pin Number Pin Name Description 1 GND 2 FB 3 SW Ground Pin. Features Wide 3.6V to 32V Input Voltage Range Output Adjustable from 0.8V to 30V Maximum Duty Cycle 100% Minimum Drop Out 0.6V Fixed 300KHz Switching Frequency 12A Constant Output Current Capability Internal

查询 SN65LVCP23 供应商 捷多邦, 专业 PCB 打样工厂,24 小时加急出货 SLLS554B NOVEMBER 2002 REVISED JUNE 2003 FEATURES High Speed 2x2 LVPECL Crosspoint Switch LVDS

查询 SN65LVCP23 供应商捷多邦, 专业 PCB 打样工厂,24 小时加急出货 SLLS554B NOVEMBER 2002 REVISED JUNE 2003 FEATURES High Speed 2x2 LVPECL Crosspoint Switch LVDS