Modelsim中文教程

Transcription

1 ModelSim SOC

2 ModelSim Model Verilog VHDL OEM Verilog VHDL

3 ModelSim ModelSim/VHDL ModelSim/Verilog OEM ModelSim/LNL Verilog VHDL ModelSim/PLUS Verilog VHDL ModelSim/SE PLUS 3

4 Debussy Verilog\VHDL VHDL Debussy Verilog\VHDL IP bug Debussy 1 ntrace 2 nschema 3 nwave 4 nstate 5 ncompare 4

5 5

6 Modesim GUI Modelsim 1) 2) 3)vcd 4) 5)PLI debussy Debussy

7 Model ModelSim main : source structure process : Wave&list Signal&variable dataflow 7

8 a) RTL b) 8

9 ModelSim (Cmd), (GUI) DOS UNIX 9

10 GUI

11 1 ModelSim GUI) : flie ->new -> project 11

12 ModelSim Working ( work) working Resource 12

13 Library browser GUI) : design ->library browser 13

14 2 GUI) project -> add file to project 14

15 compile GUI) project -> compile order GUI) project -> compile all workspace project 15

16 3 load design) GUI) design -> load design 16

17 4 GUI) view -> structure module GUI) view -> signals GUI) view -> wave 17

18 5 run run GUI) run -> run all wave wave 18

19 Wave wave 19

20 Modelsim 20

21 21

22 .do test3.do vlog -work work F:/test3/black_stretch.v vlog -work work F:/test3/test.v vsim work.test view signals view structure view wave add wave sim:/test/red_out_w add wave sim:/test/green_out_w add wave sim:/test/blue_out_w run -all 22

23 [Library] std = $MODEL_TECH/../std ieee = $MODEL_TECH/../ieee verilog = $MODEL_TECH/../verilog test.mpf std_developerskit = $MODEL_TECH/../std_developerskit synopsys = $MODEL_TECH/../synopsys modelsim_lib = $MODEL_TECH/../modelsim_lib alter_lpm = D:/installed/quartus/eda/sim_lib/modelsim/alter_lpm work = work [vcom] ; Turn on VHDL-1993 as the default. Default is off (VHDL- 1987). ; VHDL93 = 1. ; RangeCheck = 1 [vlog] ; Turn off inclusion of debugging info within design units. [vsim] Veriuser = novas.dll ; Default run length RunLength = 100 1) modelsim mpf ModelSim 2)modelsim modelsim.ini [Library] [vcom] [vlog] [vsim] [lmc] modelsim.ini 3) modelsim.ini modelsim 4)modelsim.ini a) b) c)modelsim 23

24 test.mpf mpf ; Maximum iterations that can be run without advancing simulation time IterationLimit = 5000 License = license.dat ; VSIM Startup command ; Startup = do startup.do ; File for saving command transcript TranscriptFile = transcript ; File for saving command history CommandHistory = cmdhist.do. [lmc] ; ModelSim's interface to Logic Modeling's SmartModel SWIFT software libsm = $MODEL_TECH/libsm.sl [project] Project_Version = 1 Cur_Top_DUs = work.test 24

25 Modelsim 1) 2) 3)vcd 4) 5)PLI debussy 25

26 Command-line mode This an operational mode that has only an interactive command line; no interactive windows are opened. To run vsim in this manner, invoke it with the -c option as the first argument from either the UNIX prompt or the DOS prompt in Windows 95/98/2000/NT. modelsim 26

27 Allcode.txt 1 test.v 2 black_stretch.v 27

28 DOS 28

29 Vlib Vmap The vlib command creates a design library. You must use vlib rather than operating system commands to create a library directory or index file. The vmap command defines a mapping between a logical library name and a directory by modifying the modelsim.ini file. With no arguments, vmap reads the appropriate modelsim.ini file(s) and prints the current logical library to physical directory mappings. Returns nothing. 29

30 Vlib Vmap _info <library_name> _lock any_verilog_module _primary.dat _primary.vhd verilog.asm any_vhdl_unit _primary.dat <arch_name>.dat <arch_name>.asm Vlib work _info Vmap modelsim modelsim.ini [Library] work = work 30

31 Vlog vlog The vlog command is used to invoke VLOG, the Model Technology Verilog compiler. Syntax vlog [-93] [-help] [-compat] [- [+define+<macro_name>[=<macro_text>]] [+delay_mode_path] [+delay_mode_unit] [-fast[=<secondary_name>] [-hazards] [+incdir+<directory>] [-incr] [-line <number>] [-lint] [+mindelays] [+maxdelays] [+nocheckclup] [+nocheckdnet] [+nocheckoprd] [-nodebug[=ports =pli]] [-noincr] [+nolibcell] [- [+nowarn<code>] [-O0 -O1 -O4 -O5] [-quiet] [-R [-source] [+typdelays] [-u] [-v <library_file>] [-version] [-work <library_name>] [-y 31

32 Vlog Work Work Where _primary.dat - Verilog module VHDL entity _primary.vhd - Verilog VHDL entity verilog.asm <arch_name>.asm 32

33 Vsim The vsim command is used to invoke the VSIM simulator, or to view the results of a previous simulation run (when invoked with the -view switch). Syntax vsim [-c] [-coverage] [-do <command_string> [-f <filename>] [-g<name>=<value>...] [- [-help] [-i] [-installcolormap] [-keeploaded] [- [-keepstdout] [-l <filename>] [-lib [-multisource_delay min max latest] [- [+no_tchk_msg] [+notimingchecks] [-quiet] [-restore <filename>] [-sdfmin -sdftyp -sdfmax [-sdfnoerror] [-sdfnowarn] [+sdf_verbose] [-t [-tag <string>] [-title <title>] [-trace_foreign [-view [<dataset_name>=]<wlf_filename>] [-wlf <size>] 33

34 Vsim [-wlftlim <duration>] [-wlfnocompress] [-absentisempty] [-foreign <attribute>] [- [-noglitch] [+no_glitch_msg] [-std_input [-std_output <filename>] [-strictvital] [-vcdread <filename>] [-vital2.2b] [+alt_path_delays] [-hazards] [-L [-Lf <library_name>...] [+maxdelays] [+mindelays] [+multisource_int_delays] [+no_neg_tchk] [+nosdfwarn] [+nosdferror] [+nowarn<code>] [-pli "<object list>"] [+<plusarg>] [+pulse_e_style_ondetect] [+pulse_e_style_onevent] [+pulse_int_e/<percent>] [+pulse_int_r/<percent>] [+sdf_nocheck_celltype] [+transport_int_delays] [+typdelays] [<library_name>.<design_unit>] 34

35 Batch mode Batch mode Batch mode is an operational mode that provides neither an interactive command line, nor interactive windows. modelsim runallcode.bat( ) runallcode.do modelsim runallcode.bat vsim -c -do runallcode.do runallcode.do vlib work vmap work work vlog -work work -f allcode.txt vsim work.test run quit -f 35

36 runallcode.bat modelsim runallcode.do modelsim VCD FSDB off-line 36

37 Alter LPM Alter LPM MegaWizard FPGA quartus\eda\sim_lib 220model.v alter_mf.v LPM 220model.v 220model.v module alter_lpm D:/installed/quartus/eda/sim_lib/modelsim/alter_lpm 220model.v module modelsim modelsim.ini [Library] alter_lpm = D:/installed/quartus/eda/sim_lib/modelsim/alter_lpm alter_lpm library 37

38 D:/installed/ D:/installed/quartus/eda/sim_lib/ _lib/modelsim/ alter_lpm lpm D:/installed/quartus/eda/sim_lib/modelsim GUI) design -> create a new library 38

39 alter_ alter_lpm model220.v GUI) design -> compile library alter_lpm 220model.v alter_lpm modele 39

40 modlesim modlesim.ini alter_lpm lpm [Library] std = $MODEL_TECH/../std ieee = $MODEL_TECH/../ieee verilog = $MODEL_TECH/../verilog std_developerskit = $MODEL_TECH/../std_developerskit synopsys = $MODEL_TECH/../synopsys modelsim_lib = $MODEL_TECH/../modelsim_lib alter_lpm = D:/installed/quartus/eda/sim_lib/modelsim/alter_lpm [vcom] ; Turn on VHDL-1993 as the default. Default is off (VHDL-1987). ; VHDL93 = 1 40

41 Value Change Dump (VCD) Files The VCD file format is specified in the IEEE 1364 standard. It is an ASCII file containing header information, variable definitions, and variable value changes. VCD is in common use for Verilog designs, and is controlled by VCD system task calls in the Verilog source code. initial begin $Dumpfile("./test.fsdb"); $Dumpvars(0,test); # $finish; end modelsim vcd add (CR-200) $dumpvars vcd file (CR-210) $dumpfile vcd off (CR-216) $dumpoff vcd on (CR-217) $dumpon 41

42 SDF (Standard Delay Format) timing annotation. $sdf_annotate initial begin $sdf_annotate( black_stretch.sdf", black_stretch1); end vsim vsim -sdfmax GUI GUI) design -> load design load design sdf sdf 42

43 GUI SDF 43

44 Debussy a) Modelsim a b c b) Modelsim verilog $dumpxxx c) EDA Debussy RTL IC Debussy 3 44

45 Debussy Debussy FSDB(Fast Signal DataBase) VCD vcd 5-50 Debussy PLI for Verilog FLI for VHDL FSDB Verilog initial begin $fsdbdumpfile("test.fsdb"); $fsdbdumpvars (0,test); end 45

46 PLI PLI = VerilogProgram Language Interface Verilog PLI PLI C C++ verilog verilog PLI 1 PLI system task system function PLI verilog system task function task/function PLI 2 PLI verilog wire reg cell delay PLI verilog task/function verilog 3 always PLI wire/reg PLI C C system task 46

47 Linking Debussy PLI routines with MTI ModelSim (5.2 or later) 1. Locate pli.lib and veriuser.c, which Debussy provides in the following directory: <install_dir>/share/pli/modelsim_pli/winnt/pli.lib <install_dir>/share/pli/modelsim_pli/winnt/veriuser.c 2. If you are using PLI applications with your ModelSim, you need to combine your existing veriuser.c and the Debussy-provided veriuser.c into a single file. If you are not using PLI applications with your ModelSim you can use the Debussy-provided veriuser.c file. 3. Generate PLI dynamic link library (novas.dll) with the following steps: >cl -c -I/<modelsim_install_dir>/modeltech/include veriuser.c >link -dll -out:novas.dll -nodefaultlib:libcmt -export:init_usertfs veriuser.obj pli.lib shell32.lib <modelsim_install_dir>\modeltech\winnt\mtipli.lib Debussy also provides a batch file "make.bat" for user to make a.dll file. You can modify it to fit your file directory. The file is under: <install_dir>\share\pli\modelsim\winnt 4. Set the dynamic link library path to the directory containing the library produced. For instance, you have novas.dll under <user>/novas/pli, add <user>/ novas/pli to your LD_LIBRARY_PATH in your windows environment. 5. Edit your modelsim.ini file to instruct ModelSim to load the shared object produced. *Add this Veriuser entry to the [VSIM] section: [VSIM]. 47 Veriuser = novas.dll

48 Copy MODESIM debussy X:\Novas\Debussy\share\PLI\modelsim_pli\WINNT\novas.dll to X:\modelsim\win32\ Edit X:\modelsim\modelsim.ini and add block box text 48

49 (UI) Compile 49