Hardware Implementation and Performance Measure of Viterbi Decoder for Adaptive BICOFDM System

Size: px

Start display at page:

Download "Hardware Implementation and Performance Measure of Viterbi Decoder for Adaptive BICOFDM System"

仙沈
4 years ago
Views:

1 Hadwae Implementation and Pefomance Measue of Vitebi Decode fo Adaptive BICOFDM System

5 BICOFDM Vitebi IEEE 82.a BICOFDM MATLAB IEEE 82.a VHDL (scamble) (convolutional encode) (inteleave) (mape) (deinteleave) (demape) (Vitebi decode) Altea Quatus II Altea APEX EP2K5EBC652-X (FPGA) R&S (AMIQ) I

6 ABSTRACT A new achitectue of Vitebi decode fo adaptive BICOFDM system is poposed in this pape. By using 82.a standad as a sample of BICOFDM system, a MATLAB simulation envionment of 82.a baseband tansceive is completed and is used to simulate the system pefomance. Tansmitte and eceive ae designed with VHDL language, and the FPGA implementation of scamble, convolutional encode, inteleave and mappe of the tansmitte, and deinteleave, demappe and Vitebi decode of eceive is pefomed. Finally, a pefomance testbench is set up by the R&S AMIQ signal geneato and the Altea family APEX EP2K5 EBC652-X FPGA development boad. II

7 I ABSTRACT II III IV V (Scamble / Descamble) (Punctued Convolutional Coding) / (Inteleaving / Deinteleaving) / (Mapping / Demapping) / (OFDM modulation) (demapping) (quantization) (tuncation length) / (scamble/descamble) 33 III

8 4.3 (convolutional encode) (Vitebi decode) / (punctue / ZIU) / (inteleave / deinteleave) / (mappe / demappe) A 6 B IV

9 2. IEEE 8.a scamble /3 6 3/4 6 BPSK QPSK 6QAM 64QAM IEEE 82.a IFFT 3 (cyclic pefix) 4 5 EDRF 7 8 BICOFDM QAM 9 mode3 2 mode4 22 mode5 22 mode6 23 mode mode mode mode mode mode AWGN AWGN 29 V

10 3.7 EDRF EDRF scamble 33 scamble 34 convolutional encode 34 convolutional encode 35 Vitebi decode 36 BMU 37 ce 37 ACSU PMMU stack stack pack SMU Vitebi decode punctue punctue ZIU punctue ZIU deinteleave inteleave deinteleave 5 VI

11 mappe demappe mappe demappeu VII

12 BPSK QPSK 6QAM 64QAM scamble I/O 33 convolutional encode I/O 35 Vitebi decode I/O 43 punctue I/O 45 ZIU I/O inteleave I/O 5 deinteleave I/O mappe I/O demappe I/O A. A.2 B VIII

13 B.2 B IX

14 . (Wieless LAN) (Othogonal Fequency Division Multiplexing, OFDM) (eo-coect coding) (bit inteleaving) BICOFDM (Bit Inteleaved Coded OFDM) (adaptive) BICOFDM Vitebi IEEE 82.a WLAN [] BICFODM BICOFDM Vitebi MATLAB VHDL (scamble) (convolutional encode) (punctue) (inteleave) (mape) (ZIU) (deinteleave) (demape) (Vitebi decode) (FPGA)

15 .2 82.a MATLAB VHDL (FPGA) (scamble) (convolutional encode) (punctue) (inteleave) (mape) (ZIU) (deinteleave) (demape) (Vitebi decode) 2

16 82.a 2. IEEE 82.a 2. 5GHz 2.4GHz ( HomeRF Bluetooth IEEE 82.b [2] ) ( ) 5GHz OFDM BPSK QPSK 6QAM 64QAM /2 2/3 3/ Mbps 54 Mbps IEEE 82.a Binay Data Convolutional Encoding Bit Inteleaving Subcaie Mapping OFDM Modulation RF Tx. Channel Binay Data Vitebi Decoding Bit Deinteleaving Subcaie Demapping OFDM Demodulation RF Rx. 2. IEEE 8.a 3

17 2. Mode Data ate(mbits/s) / (Scamble / Descamble) (scamble) (pseudo andom sequences) IEEE 82.a 7 (geneato polynomial) 7 4 S ( x) = x + x + (2.) (exclusive o) 4

18 input eg eg eg eg eg eg eg output 2.2 scamble 2.3 (Punctued Convolutional Coding) IEEE 82.a (convolutional code) (punctue code) 2.3 IEEE 82.a (2,, 6) 2 6 = 64 (geneato polynomial) g = 33 8 () g = 7 8 () output_a input eg eg eg eg eg eg output_b 2.3 5

19 /2 2/3 3/4 /2 (mothe code) ( 2.4, 2.5) 2/3 3/4 /2 Souce Data X X X 2 X 3 X 4 X 5 Input 6 bits Encoded Data A A A 2 A 3 A 4 A 5 B B B 2 B 3 B 4 B 5 Stolen bit Bit Stolen Data A B A A 2 B 2 A 3 A 4 B 4 A 5 9 bits emain Code Rate 2/ /3 Souce Data X X X 2 X 3 X 4 X 5 X 6 X 7 X 8 Input 9 bits Encoded Data A A A 2 A 3 A 4 A 5 A 6 A 7 A 8 B B B 2 B 3 B 4 B 5 B 6 B 7 B 8 Stolen bit Bit Stolen Data A B A B 2 A 3 B 3 A 4 B 5 A 6 B 6 A 7 B 8 2 bits emain Code Rate 3/ /4 6

20 2.4 / (Inteleaving / Deinteleaving) (bust eo) [3] IEEE 82.a OFDM (symbol) (subcaie symbol) (soft subcaie modulation demapping) (cyclic shift) (confidence) IEEE 82.a i = ( NCBPS /6) ( k mod 6) + floo( k /6) k,, K, N (2.3) = CBPS NCBPS (OFDM symbol) k i 7

21 j = s floo( i / s) + ( i + N floo(6 i / N ( N / 2,) CBPS CBPS )) mod s i,, K, N (2.4) = CBPS s = max (2.5) BPSC N BPSC i j (deinteleaving) i = s floo( j / s) + ( j + N floo(6 j / N ( N / 2,) CBPS CBPS )) mod s j,, K, N (2.6) = CBPS s = max (2.7) BPSC j i k = i ( N ) floo(6 i / N ) k,, K, N (2.8) 6 CBPS CBPS = CBPS 8

22 i k 2.5 / (Mapping / Demapping) IEEE 82. BPSK QPSK 6QAM 64QAM (Gay code) (constellation) (mapping) (complex numbe) 2.6 (mapping symbol) (nomalization facto) [4-8] (Vitebi decode) BICOFDM QAM [9] 2.2 Modulation Nomalization facto BPSK QPSK / 2 6QAM / 64QAM / 42 9

23 2.6 BPSK QPSK 6QAM 64QAM

24 2.3 BPSK Input bit (b ) I-out Q-out QPSK Input bit (b ) I-out Input bit (b ) Q-out QAM Input bits (b b ) I-out Input bits (b 2 b 3 ) Q-out QAM Input bits (b b b 2 ) I-out Input bits (b 3 b 4 b 5 ) Q-out

25 2.6 / (OFDM modulation) IEEE 82.a 64 (Invese Fast Fouie Tansfom, IFFT) IEEE82.a IFFT 64 (subcaie) 4 (pilot) P ={,,,, -,-,-,, -,-,-,-,,,-,, -,,,-,,,,,,,-,,,,-,,,-,-,,,,-,, -,-,-,, -,,-,-,,-,-,,,,,, -,-,,, -,-,,-,,-,,, -,-,-,,,-,-,-, -,,-,-,,-,,,,,-,, -,,-,, -,-,-,-, -,,-,,,-,,-,,,,-, -,,-,-, -,,,, -,-,-,-, -,-,-} - SIGNAL DATA 2.7 OFDM (Fast Fouie Tansfom, FFT) 64 (Inte-Caie Intefeence, ICI) IEEE 82.a OFDM (cyclic pefix) 2

26 OFDM /4 OFDM [] 2.8 (synchonization) [] (FFT) 2 Fequency domain input IFFT Time domain output #-2 # IEEE 82.a IFFT 3

27 2.7 I OFDM Element Pilot Pilot Pilot Pilot symbol of P i at #-2 at #-7 at #7 at #2 SIGNAL.+ j.+ j.+ j -.+ j DATA.+ j.+ j.+ j -.+ j 2 DATA2.+ j.+ j.+ j -.+ j 3 DATA3.+ j.+ j.+ j -.+ j 4 DATA j -.+ j -.+ j.+ j 5 DATA j -.+ j -.+ j.+ j 6 DATA j -.+ j -.+ j.+ j Tg T OFDM OFDM OFDM 2.8 (cyclic pefix) 4

28 82.a IEEE 82.a MathWoks MATLAB (Signal Noise Ratio, SNR) (Bit Eo Pobability) Data Rate(Mbits/s) R-R4 Modulation Coding ate 6 BPSK /2 9 BPSK 3/4 2 QPSK /2 8 QPSK 3/4 24 6QAM /2 36 6QAM 3/ QAM 2/ QAM 3/4 3. 5

29 3. IEEE 82.a 997 5GHz [2] 3.2 (Exponentially Decaying Rayleigh Fading Channel, EDRF Channel ) (impulse esponse) hk h k 2 2 = N(, σ ) + jn(, σ ) (3.) 2 k 2 k 2 k 2 -kt s / T RMS σ = σ e (3.2) 2 - -T s / T RMS σ = e (3.3) TRMS (oot mean squae delay spead) T 5~25 (ns) RMS EDRF (multipath) (AWGN) 6

30 magnitude T s 2T s 3T s 4T s 5T s 6T s 7T s 8T s 9T s T s time 3.2 EDRF 3.2 OFDM (Eo-Coecting Codes) (pefomance) (bit inteleaving) (bust eos) BICOFDM (Bit Inteleaved Coded OFDM) [3-4] IEEE 82.a BICOFDM BICOFDM QAM [9] (confidence) Vitebi (bit metic) (distance metic) 3.3 7

31 BPSK QPSK distance metic distance metic Input value Input value b b (o b) 6QAM 64QAM distance metic distance metic Input value Input value b (o b2) b (o b3) b (o b3) b (o b4) b2 (o b5) 3.3 8

32 3.3 2/3 QPSK 6-QAM 64-QAM mode4 mode6 mode8 EDRF (Exponential Decay Rayleigh Fading) dB (coding gain) 3.4 BICOFDM QAM 9

33 3.3 (mothe code) (puctue patten) (tellis diagam) Vitebi (banch metic) Vitebi (Zeo Inset Unit, ZIU) Vitebi (banch) (infomation bit) Vitebi ( Odd ) ( Even ) 3 bits 4 bits 5 bits QAM 2

34 3 bits 4 bits 5bits [5-6] 4 bits 3.5 mode3 2

35 3.6 mode4 3.7 mode5 22

36 3.8 mode6 3.9 mode7 23

37 3. mode8 3.4 SMU (tace back) SMU (decision bit) SMU Foney (tuncation length) 5.8 [7-8] IEEE 82.a (2,, 6)

38 SMU IEEE 82.a 4 bits db mode4 25

39 3.2 mode6 3.3 mode7 26

40 3.4 mode8 27

41 AWGN 28

42 3.6 AWGN 3.7 EDRF 29

43 3.8 EDRF 3

44 Vitebi VHDL (scamble) (convolutional encode) (punctue) (inteleave) (mape) (ZIU) (deinteleave) (demape) (Vitebi decode) Synplify Po Altea Quatus II Altea APEX EP2K5EBC652-X (FPGA) 4. ( ) ( 4. (6, 9, 2, 8, 24, 36, 48, 54, 72 MHz) 54MHz PLL 72Mhz 48MHz 54MHz 4. 3

45 4. ( MHz) Tansmitte pat Data Modulation Coding Rate Type Rate Encode Punctue Inteleave Modulato 6 BPSK /2 6 6 => => 2 9 BPSK 3/4 9 9 => => 2 2 QPSK /2 2 2 => => 2 8 QPSK 3/4 8 8 => => QAM / => => QAM 3/ => => QAM 2/ => => QAM 3/ => => 2 Receive pat Data Modulation Coding De- De- De- Decode Rate Type Rate punctue inteleave modulato 6 BPSK /2 6 6 <= <= 2 9 BPSK 3/4 9 9 <= <= 2 2 QPSK /2 2 2 <= <= 2 8 QPSK 3/4 8 8 <= <= QAM / <= <= QAM 3/ <= <= QAM 2/ <= <= QAM 3/ <= <= 2 PLL_ 72MHz 36MHz 8MHz 9MHz PLL_ 48MHz 24MHz 2MHz 6MHz PLL_2 54MHz 4. 32

46 4.2 / LEs (Logic Element) 27 input eg eg eg eg eg eg eg output 9 LEs 4.2 scamble 4.2 scamble I/O Pin Name Numbe of bit I/O Statement clk input clock pin en input enable pin input input data input esult output data output 33

47 4.3 scamble 4.3 IEEE 82.a (2,, 6) = 64 (geneato polynomial) g = 33 8 () g = 7 8 () 4.4 LEs output_a input eg eg eg eg eg eg output_b LEs 4.4 convolutional encode 34

48 4.3 convolutional encode I/O Pin Name Numbe of bit I/O Statement clk input clock pin en input enable pin data input data input esult_a output encoded output esult_b output encoded output 4.5 convolutional encode 35

49 4.4. BMU (Banch Metic Unit) 2. ACSU (Add Compae Select Unit) (SMU) (PMMU) 3. PMMU (Path Metic Memoy Unit) ACSU 4. SMU (Suvivo Memoy Unit) ACSU 4.6 PMMU Input ZIU BMU ACSU SMU Output 4.6 Vitebi decode BICOFDM QAM BMU 4 4 ( ) 4 ( )

50 BMU bit_m_ 4 sube Bitm_w Bitm_w 4bit_adde with cay 4bit_adde with cay 5 5 bm_ bm_ bit_m_ 4 sube Bitm_w Bitm_w 4bit_adde with cay 4bit_adde with cay 5 5 bm_ bm_ LE BMU 64 ACSU 64 ce (calculate element) 4.8 PMMU (path metic) BMU (banch metic) PMMU (suvivo path) (decision bit) SMU 4.9 clk CE banch_metic_ 8 path_metic_ 8 adde 8 compaeto decision banch_metic_ 8 path_metic_ adde 8 mux 8 ce_out 8 43 LEs 4.8 ce 37

51 ACSU acsu_clk acsu_enable acsu_pm_s acsu_pm_s acsu_bm_ acsu_bm_ ce_ 8 acsu_out_s decision_s 5 acsu_pm_s2 acsu_pm_s3 acsu_bm_ acsu_bm_ ce_ 8 acsu_out_s decision_s 5 acsu_pm_s62 acsu_pm_s63 acsu_bm_ acsu_bm_ ce_63 8 acsu_out_s63 decision_s ACSU 38

52 ce PMMU ce [9-2] ce 8 PMMU PMMU pmmu pmmu_out_s(7) sel pmmu_out_s(6:) 7 mux_ 8 pmmu_in_s pmmu_clk pmmu_enable pmmu_out_s(7) pmmu_out_s(6:) 7 mux_ 8 pmmu_in_s pmmu_out_s63(7) pmmu_out_s63(6:) 7 mux_63 8 pmmu_in_s63 4. PMMU 39

53 SMU 3-pointe even algoithm (tace back) (smu bank) [22-25] ACSU smu_bank en smu_bank clk waddess daddess wen tben dcen 5 5 contol smu_bank_am Ram bits 64 mux tb_out deci_in state_in 64 shift egiste ( 6 bits ) 6 6 state_out LEs 248 memoy bits 3-pointe even algoithm SMU 6 (wite) (tace back) (decode) (idle) ACSU 4

54 (stack) SMU 4.3 stack stack_en stack_clk stack_load pointe data_in 5 egiste ( 5 bits ) esult 2 LEs 32 Memoy bits switch stack_pack_en stack_pack_clk data_in stack_pack contol Stack_ mux esult Stack_ 24 LEs 64 Memoy bits 4.2 stack stack pack 4

55 SMU en smu_ctl clk deci_in smu bank_ smu bank_ smu bank_2 smu bank_3 smu bank_4 smu bank_5 smu_mux stack pack de_out 423 LEs 2352 Memoy bits 4.3 SMU BMU ACSU PMMU SMU 4.4 I/O Vitebi Decode PMMU data_a data_b BMU ACSU SMU de_out 336 LEs 2352 Memoy bits 4.4 Vitebi decode 42

56 4.4 Vitebi decode I/O Pin Name Numbe of bit I/O Statement clk input clock pin en input enable pin data_a input data input data_b input data input esult output decoded output

57 4.5 / 2.5 ( 2.5, 2.6) 4.6 IEEE 82.a MAC R R2 R3 R /4 4 enable clk_in clk_out 4 punctue wite/ead contol input_a input_b egiste 2 2 bits esult 7 LE 4.6 punctue 44

58 4.5 punctue I/O Pin Name Numbe of bit I/O Statement clk_in input clock pin clk_out input clock pin en input enable pin 4 4 input function select input_a input data input input_b input data input esult output decoded output 4.7 punctue BICOFDM QAM 4 bits

59 ZIU 4 enable clk_in clk_out 4 wite/ead contol data 4 egiste 2 2 4bits 4 esult_a esult_a 4 25 LE 4.8 ZIU 4.6 ZIU I/O Pin Name Numbe of bit I/O Statement clk_in input clock pin clk_out input clock pin en input enable pin 4 4 input function select data input data input input_b input data input esult output decoded output 46

60 4.9 punctue ZIU 4.6 / 2.6 / OFDM 48 OFDM 6 47

61 4.7 OFDM 4.2 I-channel Q-channel I-channel Q-channel BPSK QPSK 6QAM 64QAM 4.7 OFDM BPSK QPSK QAM QAM

62 I-channel Q-channel I-channel Q-channel BPSK QPSK 6QAM 64QAM / 2 49

63 inteleave 2 inte_clk inte_en 4 inte_input inte_w_addess inte_d_addess w_d_switch inte_am_ 8 6 bit inte mux inte_output inte_am_ 8 6 bit 289 LEs 576 Memoy bits 4.22 inteleave deinteleave 2 deinte_clk deinte_en 4 deinte_w_addess deinte_d_addess w_d_switch deinte_input 4 deinte_am_ 8 6 4bits 4 deinte mux 4 deinte_output deinte_am_ 8 6 4bits LEs 234 Memoy bits 4.23 deinteleave 5

4.8 inteleave I/O Pin Name Numbe of bit I/O Statement clk input clock pin en input enable pin 2 2 input function select input input data input output output data output 4.

64 4.8 inteleave I/O Pin Name Numbe of bit I/O Statement clk input clock pin en input enable pin 2 2 input function select input input data input output output data output 4.9 deinteleave I/O Pin Name Numbe of bit I/O Statement clk input clock pin en input enable pin 2 2 input function select input 4 input data input output 4 output data output 4.24 inteleave deinteleave 5

65 / (nomalization facto) A A. FFT/IFFT [26] I Q 3 A. (decode) A b m b m b m b b b b b m b b m m GND m b b b b m b b m b m b b b m b b m b signbit = = + = = + = = = = + + = + = + + = + = =

66 (Read Only Memoy, ROM) 2 bits ROM +bits MULT +9bits 2bits (addess) ROM +8bits value +/ BPSK /2 QPSK 2 /2 6QAM /4 64QAM 42 /8 53

67 BICOFDM QAM 4 bits 4 bits ( 3.3) B B. B.2 B.3 3 bits 4 bits bits 4 6 bits 4 bits mappe 2 en clk input 2 3 map_coe_ 3 input_mux 3 map_coe_ 3 map_im map_im 73 LEs 4.26 mappe 54

68 4. mappe I/O Pin Name Numbe of bit I/O Statement clk input clock pin en input enable pin 2 2 input function select input input data input map_im 3 output mapped output map_qm 3 output mapped output demappe 2 en clk input_i input_q demap_ 2 6 coe_ 4 3 denomalize 6 demap_ coe_ 4 Output mux 4 esult 3 53 LEs 32 Memoy bits 4.27 demappe 4.2 demappe I/O Pin Name Numbe of bit I/O Statement clk_in input clock pin clk_out input clock pin en input enable pin 2 2 input function select input_i 3 input data input input_q 3 input data input esult 4 output demapped output 55

69 4.28 mappe demappeu (signal geneato) (clock geneato) (PLL) Altea Quatus II MegaFunction ( 2 3 4) (XOR) 56

70 FPGA IEEE 82.a 54M/bps 4.3 mode6 (6QAM, code ate 3/4) Altea APEX EP2K5EBC625-X5 (FPGA) FPGA Quatus II SignalTap LTP (eal time) Signal geneato Convolutional encode punctue inteleave mappe clk_2 clk_ clock geneato clk_3 Eo check Vitebe decode punctue deinteleave demappe

71 4.3 58

72 VHDL IEEE 82.a MATLAB 4 bits BICOFDM QAM 5. (Logic Elements) (Memoy bits) (gate count) [27] Altea APEX EP2K5EBC652-X (FPGA) (scamble) (convolutional encode) (punctue) (inteleave) (mape) (ZIU) (deinteleave) (demape) (Vitebi decode) 5. Pat Name LEs Memoy Bits Gate Counts signal_gen 9 8 conv_encode 2 punctue 7 44 inteleave mappe demappe deinteleave ZIU Vitebi decode total

73 A Modulation type QPSK 6QAM 64QAM Voltage level A. Nomalized Signed value Appoached value

74 6 64QAM() x x x 6QAM() x xx QPSK() xx xx BPSK() xx b2~b Sign bit m m m9 m8 m7 m6 m5 m4 m3 m2 m m A.2

75 B B. Sign B b b9 b8 b7 b6 b5 b4 b3 b2 b b > <- 62

76 B.2 Sign B b b9 b8 b7 b6 b5 b4 b3 b2 b b > <- 63

77 B.3 Sign B b b9 b8 b7 b6 b5 b4 b3 b2 b b > <- 64

78 [] IEEE Std. 82.a-999, Pat : Wieless LAN Medium Contol (MAC) and Physical Laye (PHY) specifications: High-speed Physical Laye in the 5GHz Band. LAN/MAN Standads Committee of the IEEE compute society, Sep. 6, 999. [2] IEEE Std.82.b, Wieless LAN Medium Access Contol (MAC) and Physical Laye (PHY) specifications Highe-Speed Physical Laye Extension in the 2.4GHz Band, Septembe 999. [3] S. Lin and D.J. Costello, Eo contol coding: fundamentals and applications, Pentice Hall. N. J, 983. [4] Q. Wang and L.Y. Onotea, Coded QAM using a binay convolutional code, IEEE Tans Commun, Vol. 43, No. 6, June 995. [5] Filippo Tosato and Paola Bisaglia, Simplified Soft-output Demappe fo Binay Inteleaved COFDM with Application to HIPERLAN/2, Hewlett-Packad Laboatoies, Octobe 2. [6] Chales Lee and H. L, Convolution coding fundamentals and applications, London Atech House, 997. [7] Thomas May, Hemann Rohling, and Volke Engels, Pefomance analysis of Vitebi decoding fo 64-DAPSK and 64-QAM modulated OFDM signals, IEEE Tans Commun, Vol. 46 No. 2, pp. 82-9, Feb [8] Jachyeong kim and Gegoy J. Pottie, On punctued Tellis-Coded Modulation, IEEE Tans Commun, Vol. 42, No. 2, pp , Mach [9] T.C. Chen, A Geneal Achitectue of Vitebi decode fo Adaptive Bit Inteleaved Coded OFDM Systems, Chung Hua Univesity eseach, May 25. [] Richad van Nee and Ramjee Pasad, OFDM fo wieless multimedia communications, Atech House, 2. [] R. Moison, L.J. J. Cimini, and S.K. Wilson, On the use of a Cyclic Extension in OFDM, IEEE Tans. Infomation Theoy, Vol. 2, pp , Oct. 2. [2] Naftali Chayat, Updated submission template fo TGa evision 2, IEEE P82. Wieless LANs, Mach 998. [3] Xiaodong Li, Aik Chindapol, and James A. Ritcey, Bit-inteleaved coded modulation with iteative decoding and 8PSK signaling, IEEE Tans. on Communications, Vol. 5, No. 8, pp , Aug

79 [4] Filippo Tosato and Paola Bisaglia, Simplified soft-output demappe fo binay inteleaved COFDM with application to HIPERLAN/2, IEEE Intenational Confeence on Communications (ICC 22), Vol. 2, pp , 28 Apil - 2 May 22. [5] 24 [6] 82.a Vitebi 24 [7] G.D. Foney, Convolutional Codes II : Maximum likelihood decoding, Inf. Contol, 25, pp , July 974. [8] G.D. Foney, The Vitevi algoithm, Poc. IEEE, vol. 6, pp , Ma [9] Byonghyo Shim, Sungmin Cho and Jung Chul Suh, An impoved VLSI achitectue fo Vitebi decode, TENCON 99. Poceedings of the IEEE Region Confeence, vol., pp , Sept [2] A.P. Heksta, An altenative to metic escaling in Vitebi decodes, IEEE Tansactions on Communications, vol. 37, pp , Nov [2].B. Shung, P.H. Siegel, G. Ungeboeck, and H.K. Thapa, VLSI achitectues fo metic nomalization in the Vitebi algoithm, IEEE Intenational Confeence on SUPERCOMM/ICC '9, pp , 99. [22] H.L. Lou, Implementing the Vitebi algoithm, IEEE Signal Pocessing Magazine, vol. 2,pp , Sept [23] M.H. Chan, IC design of an adaptive Vitebi decode, IEEE Tansactions on Consume Electonics, vol. 42, pp. 52-6, Feb [24] C.M. Rade, Memoy management in a Vitebi decode, IEEE Tansactions on Communications, vol. 29, pp , Sept. 98. [25] T.K. Tuong et al. A VLSI design fo a tace-back Vitebi decode, IEEE Tansactions on Communications, vol. 4, pp , Ma [26] [27] Altea Copoation, AN : gate counting methodology fo APEX 2K devices, Application note, ve.., Sep

MAN- Metropolitan Area Network Resilient Packet Ring a : 5GHz 54Mbps b : 2.4GHz 11Mbps c : MAC Bridge 802.1D 80

MAN- Metropolitan Area Network Resilient Packet Ring a : 5GHz 54Mbps b : 2.4GHz 11Mbps c : MAC Bridge 802.1D 80 IEEE 802.11a s0323516@ncnu.edu.tw 1 (WLAN) [1] 1963 IEEE Institute Of Electrical and Electronics Engineers LAN MAN-Metropolitan Area Network IEEE 802 IEEE 802 Working Group 802.11 IEEE 802 802.1 LAN MAN