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1 影像顯示科技導論薄膜電晶體特性與製程技術國立中興大學電機工程系暨光電工程所劉漢文 1

2 Contents TFT-LCD introduction Characteristics of TFT devices Array process technology 5-mask IS-type TFT process 5-mask BCE-type TFT process 2

3 TFT-LCD introduction 3

4 What is TFT-LCD? TFT---- 薄膜電晶體 Thin Film Transistor LCD---- 液晶顯示器 Liquid Crystal Display 4

5 液晶顯示器主要優缺點優點低電壓驅動低消耗電流體積薄, 重量輕可實現大面積化彩色化容易缺點視角限制外加背光源或投射光源溫度操作範圍限制應答時間 5

6 TFT-LCD System 6

7 TFT LCD Operation Concepts Electrical potential Water level TFT Water faucet Interconnections Water pipes Capacitors Water tanks 7

8 Transistors G G S D S D S D G a-si p-si c-si 8

9 TFT LCD Operation Concept Charging Fill each tank to its own water level 1 tank at a time 1 row of tanks at a time Refresh faster than eyes can sense Frame rate ~ 60Hz 9

10 TFT LCD Operation Concept Holding Keep the level until next refresh Leakage Increase tank size Storage capacitor 10

11 TN 型 LCDs 顯示原理 Field OFF Field ON Twist 90 o 液晶分子利用液晶的旋光特性調變穿透光線液晶的旋光特性消失 11

12 STN LCDs 顯示原理 Twist 270 o 利用液晶的雙折射特性調變穿透光線液晶分子 Field OFF Field ON 12

13 LC T-V Curve 13

14 Polarizer Introduction Polarizer 偏光板穿透吸收 14

15 Normally White Mode Front Polarizer Electric Field E<Eth ε= ε Electric Field E>>Eth ε= ε Rear Polarizer 15

16 Normally Black Mode Front Polarizer Electric Field E<Eth ε= ε Electric Field E>>Eth ε= ε Rear Polarizer 16

17 TFT LCD Design Concepts Opto-electrical: Voltage-transmittance dependence transmittance Electrical voltage Charge LC to the desired voltage within a finite period Hold the charge until next refresh Decrease signal delay Minimize driving load Suppress signal coupling Optical: Shield out the area where V-T dependence is not valid 17

18 TFT LCD Design Concepts Optical aspect Aperture Electrical aspect TFT off current low enough to hold voltage across LC TFT on current large enough to charge LC Parasitic capacitance low enough to override signal coupling and decrease loading Parasitic resistance low enough to signal delay Data line Gate line C GD C LC C S V COM 18

19 Characteristics of TFT devices 19

20 Various Silicon silicon atom Single Crystal Silicon (perfect atom arrangement) Transistor mobility : > 600 cm 2 /Vs CPU, ASIC, memories Poly Crystal Silicon (perfect atom arrangement within each grain ) Transistor mobility : 50 ~ 500 cm 2 /Vs Good for circuit operated at mid-level frequencies. Amorphous Silicon (random atom arrangement) Transistor mobility : 0.5 ~ 1.5 cm 2 /Vs Only good for pixel switching 20

21 Qualitative Comparisons Drain current [A] Vds = 5 V Gate-source voltage [V] Drain current Vds = 5 V Gate-source voltage [V] Drain current Vds = 5 V Gate-source voltage [V] Crystalline Si Poly-Si Amorphous Si

22 Inverted Staggered Structure Etching stop (Ion stop, IS) type α-si:h and n + must be deposited in separate PECVD runs. Thin α-si:h layer(~40nm), photo sensitivity reduced Drain n+ SiNx SiNx SiNx α-si:h Source Gate

23 Inverted Staggered Structure Back channel etching (BCE) type Relatively simple fabrication procedure Relatively thick(~0.2um) α-si:h layer, photo sensitivity n+ α-si:h Drain SiNx SiNx Source Gate

24 Design of TFT Device 24

25 IV of TFT Device (1) 25

26 IV of TFT Device (2) 26

27 TFT driving curve TFT Operation: Id-Vd curve Linear region Id (ma) Vd (V) Vg=4V Vg=6V Vg=8V Vg=10V Idsat W Id = Ciμ L 1 W Id = μci 2 L 1 Vd 2 ( Vg Vt ) Vd 2 Saturation region: Vg Vg --Vt Vt = Vd Vd ( Vg Vt) 2 27

28 TFT Device s W/L Id BCE (Back channel etching) Id I-stopper Source electrode Semiconductor ti ta Gate electrode X=0 X=L L Drain electrode Gate insulator W 28

29 Parasitic Capacitance to TFT 29

30 Effect of C gd 30

31 Self alignment to Min. C gd 31

32 Limitations in Larger- & Higher- Resolution 32

33 5 PEP I/S TFT Array Process Flow 33

34 IS-TFT structure Passivation N + -α-si M2-Signal line I Stop (SiN x ) Pixel(ITO) G-SiNx Signal Line Channel (α-si) TFT Pixel Area SiON Cs M1-Gate line 34

35 TFT Process Flow Clean / Stripper Thin film Deposition Wet / Dry Etching Photo Process 35

36 Thin Film Deposition Without consuming the substrate (compared to thin film growth, eq. thermal oxide) Classification PVD (Physical vapor deposition) Target or evaporation source CVD (Chemical vapor deposition) Reactant 36

37 5mask process fabrication structure GL IS SL + n+cut TH PX Signal Line TFT Pixel Area Cs Pad-Gate Pad-Signal X-Over 37

38 PEP1 - Gate Line(GL) TFT Cs Pad X-Over Metal I Sputtering Pre Treat (Brush+O 3 water+ms+spin) Metal I Sputtering, Rs=0.3±10%Ω/ GL Photo (U<5% ) GL ICP dry etch(o 2,SF 6,BCl 3,Cl 2 ) or Wet Al etcher( 混酸 ) Taper = 30±15 38

39 Thin Film Cleaner Process Glass out Spin exit Spin table Spin Entrance MS CJ Glass in Air knife Wet conveyor Neutral room Detergent Brush Rinse1 Etching Rinse 2 LAL50 39

40 Cleaning ability Particle remove ability : Brush ( 99% ) > MS + H2 ( 95% ) > MS or CJ ( < 90% ) Organic remove Detergent and O3 water Remove Native Oxide LAL50 (BHF) 40

41 Sputter (PVD) Loadlock x2 Transfer chamber x1 Heat chamber x1 Process chamber x3 41

42 PVD-Sputtering Cooling Water Floating Mask Heater 基板 Mask 水冷板 M e- Target (-) Ground shield(+) Cooling water C 磁鐵磁鐵 Backing Plate - Power - TM space - Deposition Temperature - Scan Pass - Pressure - Deposition Time 42

43 Taper Issue Profile : Taper. The PEP#1 taper will affect the following film, SiON, step coverage.if taper NG, then SiON will have bad step coverage, leading to leaky path. As a consequence, GT leak type defects occur. Worse yet, X short. Hence, the control of pep#1 taper would become very significant, essential. SPEC for up-to-date PEP#1 TAPER:Ideally,30±15 o.if higher taper, higher risk of GT mode defects. 43

44 Photo Process Flow Photo process Thin film Coater Stepper Developer Etching 44

45 Coater Process Pre-Bake Spin Coating Soft-Bake PR Coating PR Thin Film Glass Substrate 45

46 Influence PR Thick Parameter 1.Coater Max Rpm : 10rpm 100Å 2. 光阻 Cp : 0.1Cp 200Å 3.Coater Exhaust : Volume 邊緣膜厚 4. 光阻用量 & Thinner(NBA) 用量 5.Pre-Bake 溫度 6. 環境溫溼度 (influence PR Cp) 46

47 Stepper Process Align & Exposure U.V. Cr Pattern MASK PR PR Thin Film Glass Substrate 47

48 Exposure Simulation 48 D C B A A B C D A B C D A B C D A B C D A B C D A B C D

49 Developer Process Develop Hard-Bake PR PR Thin Film Glass Substrate 49

50 Influence CD Developer Parameter 1. 顯影液的濃度值 2. Post-Bake 的溫度 3. Stepper 到 Developer 間的 Q-Time 50

51 Positive Resists Chemical Reaction O N 2 g + h light O C OH Glass Inhibitor R I I I I I I I I I I Exposure I I I I I R I Acid Coater I I I I I I A A A A A A I I I I I I Stepper I I I I I I I I I I I Developer 51

52 Dry Etch Process PE Films RIE ICP 52

53 PE Machine PE mode : chemical (radical F*) PC-L LL1 PC-R RF VAC- Robot LL2 F* F* F* plasma Cassette Port 1 ATM- Robot Cassette Port 2 PE mode 53

54 RIE Machine RIE mode : chemical + physical ( ion) Process Chamber 2 (PM2) Load lock Chamber 2 Process Chamber 1 (PM1) VAC- Robot Process Chamber 3 (PM3) SF 5+ F* plasma Load Lock Chamber 1 RF Cassette Port 1 ATM- Robot Cassette Port 2 RIE mode 54

55 Plasma Potential & DC Bias Plasma Potential Volt DC Bias Time RF potential 55

56 DC biases and RF powers Plasma potential Plasma potential 0 DC bias time DC bias 0 time RF potentials Lower RF power Smaller DC bias Higher RF power Larger DC bias 56

57 ICP mode : chemical(source) + physical(bias) 57

58 Etching Profile The chamber structure for RIE mode RF gas inlet exhaust PR Al The chamber structure for PE mode gas inlet RF exhaust PR AS 58

59 Recipe Parameter Gas Pressure Temperature RF Power EPD ( Time ) mode 59

60 End Point detection (EPD) Optical Emission Spectroscopy (OES) Monitor the changed emission intensity of optical radiation from Either a reactant or product in plasma. Ground Amplifier Plasma Monochromator Match Power Electrode Wafer Detector 60

61 Wet Etch Process Rorze DNS Cross Passage Conveyer Outlet Conveyer Dryer Rinse 2 Indexer Air knife Wet Shuttle Entrance Conveyer Etch 1 Etch 2 (Etch3) Rinse 1 Main Controller 61

62 Strip Machine Rorze DNS Cross Passage Conveyer O 3 (Ozone) Dryer Dryer Rinse 2 Indexer Air knife Wet Shuttle Entrance Conveyer Strip 1 Strip 2 IPA Rinse 1 Main Controller 62

63 Etching Wet Etching Chemical Isotropic Good selectivity Low EQ cost high running cost Dry Etching Physical and chemical Anisotropic Bad selectivity High EQ cost low running cost 63

PEP2 I Stop I/S SiNx a-si SiON TFT Cs Pad g-sin X-Over SiON CVD Pre Treat(Brush+MS+Spin) SiON CVD (SiH 4 +N 2 O+N 2 ) 4 Layer CVD Pre Treat(Brush+MS+Spin) 4 Layer CVD (SiON /

64 PEP2 I Stop I/S SiNx a-si SiON TFT Cs Pad g-sin X-Over SiON CVD Pre Treat(Brush+MS+Spin) SiON CVD (SiH 4 +N 2 O+N 2 ) 4 Layer CVD Pre Treat(Brush+MS+Spin) 4 Layer CVD (SiON / g-sinx (SiH 4 +NH 3 +N 2 )/a-si(sih 4 +H 2 )/ IS SiNx) N 2 O plasma treat(n 2 O gas) enhance PR/SiNx adhesion IS Photo(Back Side exposure + Exposure) SiNx Wet etching(dhf, HF 0.6%) 64

65 I-Stop (SiNx) function To prevent channel from N + -Si etching Define the channel length IS IS Region I/S SiNx 4 Layer 65

66 PECVD System 66

67 RF Generator and Matching System ~ RF generator Matching controller Matching box Process chamber 67

68 Film Deposition - CVD (e) Main Stream (a) (c) (b) (d) Interface Boundary Layer 沈積步驟 : (a) 反應物藉由擴散通過介面邊界層 (Interface Boundary Layer) (b) 反應物吸附在玻璃表面 (c) 化學沉積反應發生 (d) 反應副產品與未反應氣體藉由擴散通過介面邊界層 (e) 生成物與未參與反應的反應物進入主流層 (main stream), 並離開系統 68

69 Characteristic of PECVD Low temperature Reduce process thermal budget Substrate or process consideration Worse stoichiometry Contain a large amount of H2 Low internal stress tuned by RF power 69

70 PEP3 Signal Line & n + α-si Cutting TFT Cs Pad X-Over n + α-si Pre Treat(LAL50+O 3 +MS+Spin) n + α-si CVD (SiH 4 +PH 3 +H 2 ) Metal II Sputtering Pre Treat(Brush+LAL50+O 3 +MS+Spin) Metal II Sputtering SL Photo Wet etching, Taper = 30±15 n + α-si Plasma Etching Photo Resist Strip 70

71 PEP4 Through Hole(TH) TFT Cs Pad X-Over P-SiNx CVD Pre Treat (Rinse, MS, Spin dry) P-SiNx CVD (PECVD:SiH 4,NH 3,N 2 ) TH photo TH wet Etching (BHF: 6%HF ) 71

72 PEP5 Pixel(PX) TFT Cs Pad ITO Sputtering Pre Treat ITO Sputtering PX Photo ITO wet etching(3.4% oxalic acid with Surfactant) ITO PR Strip Anneal Pre-clean TFT Anneal X-Over TEG Test Array Test 1 Laser Repair Array Test-2 Visual inspection 72

73 Anneal Process Why we need anneal? 1. 利用熱能, 使材料中的原子進行晶格位置的重排, 降低材料中的缺陷密度阻值水氣及應力, 以改善電晶體的電性 2. 將 α-ito 轉變為 poly-ito a) 阻值變低 b) 穿透率變高 73

74 5 PEP BCE TFT Array Process Flow 74

75 5 PEP BCE TFT GE AS SD BP ITO 75

76 PEP2 AS Layer AS layer Pre-treat TFT Pre-dep. clean Cs Brush+CJ+Spin g-sin/α-si/n+α-si AS island layout PECVD. AS-Photo AS-Etch AS-Flush AS-Strip N 2,NH 3,SiH 4 / H 2,SiH 4 / H 2,PH 3,SiH 4 UV treatment RIE Dry etch SF 6,Cl 2 1% HF 76

77 PEP3 SD Layer TFT Cs Ti/Al/Ti film Pre-treat Rs<0.2Ω/ Pre-dep. clean Sputter CJ+B+Spin SD layer layout SD-Photo Taper Angle<60 o SD-Etch/N+ RIE Dry etch BCl 3,Cl 2 PR Strip SD-Strip 77

78 IS and BCE channel process compare IS structure might have better electric characteristic (I off / μ n ) than BCE process. IS structure might have lower photo current effect. IS structure is easily to control channel length. Use BCE process can gain CVD capacity. If we want to use 4 PEP, we need to use BCE process. 78

LED Mu-Tao Chu Copyright 2012 ITRI

LED Mu-Tao Chu Copyright 2012 ITRI LED Mu-Tao Chu 1 LED LED LED 2 LED LED LED LED100 lm/w LED 2015LED~30% 400LEDLED DOE LED Source: Solid-State Lighting Research and Development: Multi-Year Program Plan, March 2011, DOE LED LED LED OEMODM