, Testbch for Lane Detection Demo in System Gerator Frame Rate Display.8 RGB Ref I Out Hough, (, ), (input stimulus), DA, ( )DA,,,,, System Gerator HD

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利用赛灵思 FPGA 平台构建汽车驾驶辅助系统算法 System Gerator for DSP 是一款具有高抽象层的设计工具, 为算法开发人员和系统架构师从 Simulink 算法参考模型过渡到 FPGA 硬件实施技术提供了一种高效的途径, 且无需任何 HDL 编码工作作者 :Daniele Bagni, 赛灵思公司 DSP 专家联系方式 :daniele.bagni@xilinx.

1 利用赛灵思 FPGA 平台构建汽车驾驶辅助系统算法 System Gerator for DSP 是一款具有高抽象层的设计工具, 为算法开发人员和系统架构师从 Simulink 算法参考模型过渡到 FPGA 硬件实施技术提供了一种高效的途径, 且无需任何 HDL 编码工作作者 :Daniele Bagni, 赛灵思公司 DSP 专家联系方式 Roberto Marzotto,Embedded Vision Systems (evs) S.r.l. 设计工程师联系方式 : roberto.marzotto@evsys.net Paul Zoratti, 赛灵思公司汽车高级系统架构师联系方式 :paul.zoratti@xilinx.com,, FPGA, FPGA PC FPGA System Gerator for DSP, Simulink PC FPGA evs System Gerator for DSP Xilinx FPGA,,, 驾驶辅助系统开发面临的挑战 (DA) PC, PC,,,

2 , Testbch for Lane Detection Demo in System Gerator Frame Rate Display.8 RGB Ref I Out Hough, (, ), (input stimulus), DA, ( )DA,,,,, System Gerator HDL Input ROI RGB EOF frame _in hst_th eth _th 0.0 perctage of pixels to be saturated (HST ) 0.9 perctage of not edge pixels (ETH ) u T Transpose -K- Gain frame _in hst_th eth_th Lane Detection frame_in hst_th eth_th 车道偏离警告模型简介 (LDW) DSP, Spartan - FPGA Input Image Lane Marking Candidates VLIW DSP L D W ROI Cropping Morphological ( Xcell Journal Operators Gaussian Noise : Reduction Lane Marking, Pattern Search publications/xcellonline/xcell_/xc_ Histogram Adaptive Threshold Stretching pdf/p-9_-block.pdf ), + Thinning Simulink H/V Gradits Magnitude and Phase FPGA Extraction Calculation VHDL,,, LDW,FPGA, Simulink System Gerator for DSP FPGA,, FPGA frame_ FPGA Processing EOF Boolean Lane Tracking Repository Count u T Transpose Departure Warning System Gerator 中车道检测演示测试基准 MATLAB Simulink,(pipeline) -D Simulink x (GNR);,, BW Repository Count Ref I Hough Theta Transform Hough Transform Matrix Viewer Hough Rho Pattern Search Pts Hough Theta_list Rho_list Peak Detection LDW Simulink RGB Pts Output 008

3 (HST),, ; / (HVG), -D x ( D ), HVG (ETH), I/O ( ) (LMPS),, x (MRP),, Simulink,, Simulink MATLAB FPGA,,LDW Simulink FPGA,FPGA, 0,, XA Spartan-A DSP 00, A DSP 800 E 00 Simulink DSP MATLAB DSP System Gerator 概述 System Gerator for DSP System Gerator for DSP Simulink FPGA Simulink DSP, (), CORE Gerator PC, DSP DSP 90,, FIR FET FEC (bit-wise block) Gateway-In Gateway-Out FPGA Simulink Gateway-In,, Simulink MATLAB, System Gerator M AT L A B Simulink Source and Sink From-Workspace To-Workspace MATLAB (From- Workspace), MATLAB (To- Workspace), MATLAB System Gerator, MATLAB ( MATLAB,, ), PC FPGA,, PC,, Simulink,, System Gerator for DSP,, GNR, System Gerator 实施 GNR 功能 ( ), ( CMOS ),,, (FIR) G N R S y s t e m G e n e r a t o r, MATLAB,, ( ),

4 : n_mask = fspecial('gaussian',, 0.8); _img = conv(in_img, n_mask, 'same'); data_in data_ x, [I(u,v-); I(u,v-);I(u,v-);I(u,v-);I(u,v)],,,,, (line buffer), RAM( FPGA ) System Gerator for DSP, MATLAB GNR (, MATLAB,,System Gerator System Gerator System Gerator, ) HDL,,System Gerator -D GNR ( ( ), ), x DSP, HDL System Gerator I (u,v), eth _th phase _in phase _ hst _th delay _phase data _ offset _in data _ hg_ vg _ grad _h_in grad _v _in edge _ edge lmc clean_ edge _ gain _in offset _ magn magn cutoff _ phase erode_ threshold gain _ ArcTan cutoff _in th _not _edges dilate _ GNR HVG HST ETH LMPS MRP Delay rts_g rst rst vs_ Delay hs_ Delay Delay ctrl _sig_buffer Delay L L Y_in Y_in vs_in hs_in and Logical L L L Y_in Y_in Y_in filtered data _ Five Buffer (latcy =) sync _inp not Inverter and Logical z - Delay x FIR (latcy =) 008

5 d0 d d d The latcy of this block is ( x z - Delay L FIR, ) Out z - Delay L, Out ValidOut Dual Buffer Latcy z - Delay Out Out L L L, 900 (9 MSPS), ValidOut ( Dual Buffer Terminator FPGA DSP8 The latcy of this block is ) or Logical datain Constant rst cnt Counter a b a=b Relational 0 Constant Constant Delay Delay hi lo Concat hi lo Concat addra dina wea addrb dinb web A B Dual Port RAM latcy= z - Delay Delay Out Out, 9 ( System Gerator ) ROM, ROM RAM(FPGA ), z - Delay ValidOut, System Gerator,, addr z - ROM A sync _inp sync counter _ addr z - ROM B addr z - synch counter and ROM C z - Delay z - Delay (: A0 coeff _from _rom, Y_in Y_in Y_in Y_in In In In In tapsdelay 0 tapsdelay tapsdelay tapsdelay Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out A A A A A A A A8 B0 B B B B B B B B8 C0 C C Out A Out B mux _ Sel DSP 8 Macro (latcy =) A coeff _from _rom mux _ Sel DSP 8 Macro (latcy =) B coeff _from _rom P P d d Register Register q q 9 Down Sample 9 Down Sample a b a + b AddSub a b a + b AddSub cast Convert filtered, x x FPGE,, ) Y_in In tapsdelay Out Out Out Out C C C C Out C mux _ Sel DSP 8 Macro (latcy =) C P d Register q 9 Down Sample Delay System Gerator mux 9 (latcy =) [a:b] Slice Delay A0 A A A A A 8 A 9 A 0 A8 in in in in in in in mux9 A (latcy =) Out A B0 B B B B B B 8 B 9 B8 in in in in in in in mux9 B (latcy =) Out B 0 C0 C C C C C C in in in in in in in mux9 C latcy = Out C [a:b] Slice in in in in in 8 in 9 in 0 d0 d d d Mux d0 d d d Mux Delay Mux MATLAB System Gerator (, FIR ), System Gerator FIR

6 ,, Stop MATLAB,,, System Gerator FPGA 综合结果 FPGA,, XA Spartan-A DSP 00,,, 8. MHz,. MSPS,,, XA Spartan-E XA Spartan-A DSP 00, XA Spartan-A 00 GNR 00A, VGA 0-Hz ( 9. MSPS),GNR 8. MHz, 8. MSPS : 结果及未来工作 LDW, FPGA, FPGA LDW, LDW,,,,, Kalman FPGA, AccelDSP,, LDW DSP,, AccelDSP Kalman AccelDSP MATLAB, System 008

7 Gerator for DSP, AccelDSP MATLAB, MATLAB FPGA DSP, DSP, FPGA System Gerator for DSP ( ), PC,, System Gerator for DSP LDW System Gerator for DSP, ( GNR -D FIR ), ( )XA Spartan- A DSP 00 DSP8 BRAM,9 (slice) 8. MHz,. MSPS, VGA 0% FPGA, VHDL : AccelDSP,, ( (Verona University) Vittorio Murino, ) 8

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