Lecture 04 Modeling, Anlysis nd Simultion in Logic Design 逻辑设计中的建模 分析与仿真 Dr.
Engineering Design Process 工程设计过程 定义问题研究勾画可能的解答 Identify nd define prolem reserch sketch possile solutions 建模 Modeling 分析 Anlysis 仿真 Simultion 原型 Prototyping ALU 最终选择 Finl Selection 实现和测试 Implementtion nd testing 2 19 Septemer 2017
Contents 内容 1 2 3 4 5 Logic Design nd Modeling in Truth Tle 逻辑设计与用真值表的建模 Building Blocks of Digitl Systems 数字系统的构建块 Memory Design 存贮器设计 Arithmetic / Logic Unit (ALU) Design & Testing 算术 / 逻辑部件 ALU 的设计与测试 Simulte ALU Design in VIPLE 用 VIPLE 仿真 ALU 设计 3
Logic Design: Anlogue versus Digitl 逻辑设计 : 模拟与数字 tnk dil empty Tnk 水箱 full infinite rnge of vlues 4 Tnk 水箱 light : on / off finite set of vlues Tnk 水箱
Propositionl Logic nd its Elements 命题逻辑及其构成要素 5 Propositionl logic is lnguge for modeling nd specifiction 命题逻辑是一种建模和规范语言 Proposition: A sttement tht cn either e true or flse: 命题 : 一个语句, 它的的值可以是真, 或是假 One plus two is three There re two Noel prize winners t Arizon Stte University The sky is lue How old re you? You must ride ike to school! Logic connectives AND ( ), OR ( ), NOT ( ), IMPLIES ( ) light is on tnk is full (Light is off) (ul is not roken) tnk is empty Truth nd flsity vlues Truth Tle 真值表
真值表是逻辑规范 / 电路模型 Truth Tle is Logic Specifiction/Model for Circuits NOT propositionl vrile P flse true sttement P true flse 0 1 1 0 AND P Q P Q flse flse flse flse true flse true flse flse true true true 0 0 0 0 1 0 1 0 0 1 1 1 6
Truth Tle 真值表 (Contd.) OR P Q P Q flse flse flse flse true true true flse true true true true 0 0 0 0 1 1 1 0 1 1 1 1 7
Building Blocks of Digitl Circuits 数字线路的基本构件 Building Blocks Truth Tles AND gte c = c OR gte c = c NOT c = c 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 0 NAND gte c = c NOR gte c = c c XOR gte c = 0 0 1 1 0 0 1 1 0 1 1 0 1 0 1 1 1 0 0 0 8 2-1 Multiplexor 0 1 e0 If (e0=0) (f=) else (f=); f 4-1 Multiplexor c d e1 0 1 2 3 e0 f e1 e0 f 0 0 0 1 1 0 c 1 1 d
1-it 1-it 1-it 1-it 1-it 1-it 1-it 1-it Memory Design 存储器设计 : it nd Byte set Q' output reset Q 01 input One it cn store 1 or 0 One-it memory design output 9 8 its = 1 Byte Cn store chrcter Or short integer Most significnt it input Lest significnt it
Memory: Word, Long Word 存储器 : 字, 长字 In 32-it computer: 4 Bytes = 1 word nd 8 ytes = 1 doule word Word 字 31 30 29 8 7 2 1 0 1 Byte 1 Byte 1 Byte 1 Byte Cn store: int nd flot doule word 双字 63 62 61 1 Byte 1 Byte 1 Byte 1 Byte 8 7 2 1 0 1 Byte 1 Byte 1 Byte 1 Byte Cn store: long int nd doule flot 10
The Entire Memory, with 32-it ddress spce nd yte-ddressle 整个内存,32 位地址空间和字节可寻址 Hex ddress 00000000h 00000004h 00000008h 0000000Ch 00000010h 00000014h 00000018h 0000001Ch 00000020h 00000024h 00000028h 0000002Ch 00000030h 31 30 29 2 1 0............... FFFFFFF0h FFFFFFF4h FFFFFFF8h FFFFFFFCh 11
Five Component Model of Computer -- A Conceptul Model 计算机的 5- 部件概念模型 Processor 处理器 Control Unit 控制器 Memory 存储器 Peripherls 外设 Input 输入 ALU Output 输出 12 Bus 总线
Arithmetic/Logic Unit (ALU) 算术 / 逻辑单元 Opertion code (3) ALU 操作码 Opertion code 功能 function 0 0 0 AND 0 0 1 OR 0 1 0 ADD 1 1 0 SUB Adder 13
Truth Tle nd Design of One-Bit Adder 真值表和 1- 位加法器的设计 input Truth Tle output = = c = crryin crryout Sum 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 sum crryin crryout 14 One-it dder
One-Bit ALU Design 1 位 -ALU 的设计 Inputs crryout r 15 CrryIn opertion 1-it ALU opertion function 0 0 0 AND 0 0 1 OR 0 1 0 ADD 1 1 0 SUB r crryout Six inputs nd two outputs Prtil Truth Tle crryin 000001 d 0 000010 d 0 000011 d 1 000100 d 0 000101 d 0 000110 d 0 000111 d 1 001000 d 0 001001 d 1 001010 d 1 001011 d 1 001100 d 0 001101 d 1 001110 d 1 001111 d 1 010000 0 0 010001 0 1 010010 0 1 010011 1 0 010100 0 1 010101 1 0 010110 1 0 010111 1 + 1 011000 011001 011010 011011 011100 011101 011110 011111 100000 AND Component-sed design opertion 0 1 0 1 2 3 OR r ADD SUB crryout
32-Bit ALU with 96 Inputs 32-ALU, 有 96 条输入线 opertion function 0 0 0 AND 0 0 CrryIn 0 1-it ALU opertion r 0 0 0 1 OR 0 1 0 ADD 1 1 0 SUB 1 1 1-it ALU r 1 Opertion (3). ALU 31 31 1-it ALU r 31 16 crryout
Simultion of 1-it Adder 1- 位计算器仿真 One-it dder logic design sum crryin crryout VIPLE Implementtion 17 Define Before Using: Define the input whenever you see wrning sign
Testing the One-Bit Adder 测试 1- 位加法器
Converting Deciml to Binry Pttern for Automted Test Cse Genertion 为自动测试输入生成, 把二进制转换成十进制 19 CountTo7 crryin 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 if CountTo7 = 0, 1, 2, 3, then = 0, else = 1; if CountTo7 = 0, 1, 4, 5, then = 0, else = 1; if CountTo7 = 0, 2, 4, 6, then crryin = 0, else crryin = 1; 19
Automted Test Cse Genertion 自动测试输入生成 Count from 0 to 7 Test Cses Count from 0 to 63 for 1-it ALU 20
One-Bit ALU 1- 位算逻部件的设计 opertion CrryIn 0 CrryIn opertion 0 1 + 1 2 3 r 1-it ALU r crryout 21 2-to-1 multiplexer 1-it dder crryout 4-to-1 multiplexer
One-Bit ALU VIPLE Implementtion 1- 位算逻部件的实现 Yinong Define ChenBefore Using: Define the input whenever you see wrning sign
Testing the One-Bit ALU 测试 1- 位算逻部件的
Automted Test Cse Genertion 自动测试输入生成 Count from Count from 0 to 63 for 0 to 7 1-it ALU Test Cses 63 24