IP Deliverables (course topics)

FPGA Synthesis & Prototyping 國立雲林科技大學電子系許明華 sheumh@cad.el.yuntech.edu.tw

本單元在 DIP 設計中的角色 Write function spec. Write technical spec. Develop area/timing/power constraints Write RTL Run lint Develop testbench FPGA Synthesize Simulate Measure verification coverage Not enough Digital IP Prototyping

IP Prototyping System Digital Data GPIO Instrument Key Board RAM, ROM LED, LCD Analog Sensor A/D FPGA D/A Analog Device Printer Port RS232

IP Deliverables 在 DIP 設計中的角色作為 DIP 之 FPGA 合成與實現評估 DIP 雛型電路之功能驗証完整度評估 DIP 雛型電路之效能 (Speed, Cost) 評估 DIP 雛型電路之介面完整度之查核點評估 DIP 雛型電路在系統中之整合度

Course Contents FPGA Device Altera, Xilinx (pp. 5~39) FPGA Design Flow & Synthesis ISE, Quartus II (pp. 40~83) DIP Rapid Prototyping Platform (pp. 84~104) DIP Prototype System Measurement (pp.105~141) Design Example (pp.142~167)

FPGA Device FPGA Design Flow & Synthesis DIP Rapid Prototyping Platform DIP Prototype System Measurement Design Example

Increasing PLD Complexity PLD Complexity Drives Design Methodology Changes Increasing Time-to-Market Pressures Drive Change Glue Logic Control Logic Equations Schematics Complex Control Synthesis Macrofunctions SOPC Design Block-Based Design Second-Generation Synthesis IP Megafunctions 1985 1990 1995 2000 Time

Altera Device Families Programmable Logic Families High & Medium Density FPGAs Stratix, APEX II, APEX 20K, & FLEX 10K Low-Cost FPGAs Cyclone & ACEX 1K FPGAs With Clock Data Recovery Mercury & Stratix GX CPLDs MAX 7000 & MAX 3000 Embedded Processor Solutions NiosTM, ExcaliburTM Configuration Devices EPC

APEX 20K Family Industry s first MultiCore Architecture Look-up table (LUT) logic Product-term logic Embedded memory Fabricated on SRAM Process 2.5-V, 0.25/0.22-Micron Process 1.8-V, 0.18-Micron Process

APEX MultiCore Architecture MultiCore Makes Million-Gate PLD Design Possible Facilitates Efficient IP Integration Look-up Table Core Product-Term Core Memory Core

Enhanced FastTrack Interconnect 4-Level FastTrack Interconnect Continuous Routing Fast, Predictable Timing

APEX 20K Device Features

The Stratix Device Family Process Density Feature Performance Embedded Memory Digital Signal Processing (DSP) Functionality Clock Management I/O Capabilities Description 0.13-µm Technology 10,570 to 114,140 Logic Elements (LEs) Average 40% Increase TriMatrix Memory Incorporating 3 Block Sizes for Maximum Bandwidth & Capacity Embedded DSP Blocks for Complex Arithmetic Functions Advanced System Clock Control for On- & Off-Chip Clock Needs 840-Mbps Differential I/O Signaling, High-Speed Interface Support, External Memory Interfaces & On-Chip Termination Technology

Stratix Architecture Overview Logic Array Blocks (LABs) Phase-Locked Loops (PLLs) DSP Blocks MegaRAM Blocks I/O Elements (IOEs) M512 RAM Blocks M4K RAM Blocks

Advanced I/O Capabilities Differential & Single- Ended I/O Standards LVDS, LVPECL, HyperTransport, PCML HSTL, SSTL PCI, PCI-X, Compact PCI PCI High-Speed Interface Protocols 10-Gigabit Ethernet XSBI POS-PHY Level 4 HyperTransport RapidIO (Parallel) External Memory Device Interfaces DDR SDRAM & SRAM SDR SDRAM QDR & QDRII SRAM ZBT SRAM DDR FCRAM Terminator Technology On-Chip Differential Termination On-Chip Series & Parallel Termination Driver Impedance Matching

TriMatrix Memory Structure

DirectDrive Technology Each Interconnect Line Driven by Single Source Consistent Access to Routing Eliminates Congestion Uniform Routing Resources Across Device Ensures Blocks Can be Moved within or between Designs

DSP Block

DSP Block Modes

The Stratix Device Family Device Logic Elements 32x18 M512 Blocks 128x36 M4K Blocks 4,096x144 MegaRAM Blocks Total RAM Bits DSP Blocks Sample Availability EP1S10 10,570 94 60 1 920,448 6 July EP1S20 18,460 194 82 2 1,669,248 10 Q3 EP1S25 25,660 224 138 2 1,944,576 10 June EP1S30 32,470 295 171 4 3,317,184 12 Q4 EP1S40 41,250 384 183 4 3,423,744 14 Q3 EP1S60 57,120 574 292 6 5,215,104 18 Q4 EP1S80 79,040 767 364 9 7,427,520 22 July EP1S120 114,140 1,118 520 12 10,118,016 28 2003

Package Offerings & User I/O Device 672-Pin BGA Wire-Bond 1.27 mm 35 x 35 mm 956-Pin BGA Flip-Chip 1.27 mm 40 x 40 mm 672-Pin FBGA Wire-Bond 1.0 mm 27 x 27 mm 780-Pin FBGA Flip-Chip 1.0 mm 29 x 29 mm 1020-Pin FBGA Flip-Chip 1.0 mm 33 x 33 mm 1508-Pin FBGA Flip-Chip 1.0 mm 40 x 40 mm 1923-Pin FBGA Flip-Chip 1.0 mm 45 x 45 mm EP1S10 341 341 422 EP1S20 422 422 582 EP1S25 469 469 593 702 EP1S30 679 593 726 EP1S40 679 769 818 EP1S60 679 769 1,018 EP1S80 679 1,199 1,234 EP1S120 1,310 Vertical Migration Supported

Nios Flexibility & Scalability Network Processor System High-Performance Low-Cost Custom DSP Embedded Processor DSP Excalibur ARM922T + Memory ESB ESB ESB ESB ESB ESB ESB ESB 75K Gates Available 150K Gates Available ESB ESB ESB ESB ACEX EP1K100 APEX EP20K200E 500K Gates Available Excalibur EPXA10

Nios System Architecture Nios CPU On-Chip Debug Core Off-Chip Software Trace Memory Instr. Data Address Decoder Interrupt Controller Wait State Generation Data in Multiplexer Master Arbitration Avalon Master/ Slave Port Interfaces UART 0 Timer 0 SPI 0 GPIO 0 DMA 0 Memory Interface UART n Timer n SPI n GPIO n DMA n Dynamic Bus Sizing Avalon Bus Module User-Defined Interface

ARM-Based Excalibur Embedded Processor 200-MHz ARM922T Processor Up to 3.3 Mbits of Memory Up to 1M Gates of Programmable Logic Dual-Port RAM Single-Port RAM PLD Area for Customer Design ARM922T Core

Embedded Processor PLD Architecture JTAG PLL Timer UART Watchdog Timer External Memory Interfaces Processor & Interfaces I-CACHE D-CACHE Interrupt Controller ARM 8 Kbytes 8 Kbytes Trace Module ARM922T SRAM SRAM SRAM DPRAM DPRAM DPRAM Embedded Stripe EPXA1 LEs 4,160 ESB (Bytes) 6.5K 32 Kbytes SRAM 16 Kbytes DPRAM PLD LEs 16,400 ESB (Bytes) 26K EPXA4 128 Kbytes SRAM 64 Kbytes DPRAM LEs 38,400 ESB (Bytes) 40K EPXA10 256 Kbytes SRAM 128 Kbytes DPRAM

Introduction to Xilinx Product FPGA : Spartan/XL, Spartan II,Spartan-IIE, Virtex, VirtexE,Virtex II,Virtex-II Pro CPLD : XC9500/XL, CoolRunner Software :Foundation4.2i, ISE Alliance4.2i, ISE 4.2 Core : IP, LogiCore, Alliance Core Technical Support : support.xilinx.com, FAEs

Xilinx has a solution for every design Density (gates) ASICs 200K 10M High end FPGAs <200K Spartan Mid <5K CPLD Low Serves Density, Performance, Cores & Memory PAL Designs

Spartan-II Architecture Delay Lock Loop (DLL) Configurable Logic Block (CLB) Clock management Multiply clock Divide clock De-skew clock Block Memory True Dual-Port TM 4K bit RAM 4Kx1 2Kx2 1Kx4 512x8 256x16 CL DLL I O B I O B CL DLL R A M... R A M IOB CLB CLB IOB...... IOB I/O Routing Ring CLB... CLB I/O Routing Ring IOB R A M R A M DLL DLL CL I O B I O B CL Logic and Distributed RAM SelectI/O TM Technology Chip to Backplane PCI 33MHz 3.3V PCI 33MHz 5.0V PCI 66MHz 3.3V GTL, GTL+, AGP Chip to Memory HSTL-I, HSTL-III HSTL-IV SSTL3-I, SSTL3-II SSTL2-I, SSTL2-II CTT Chip to Chip LVTTL, LVCMOS

Simplified CLB Structure

3 Level Memory Hierarchy

Virtex-II Pro Platform FPGA 3.125 Gbps Multi-Gigabit Transceivers (MGTs) Supports 10 Gbps standards Up to 24 per device PowerPC 405 Core 300+ MHz / 450+ DMIPS Performance Up to 4 per device MGT MGT MGT MGT Fabric IP-Immersion Fabric ActiveInterconnect 18Kb Dual-Port RAM Xtreme Multipliers 16 Global Clock Domains

PowerPC 405 Processor Local Bus (PLB) I-Side On-Chip Memory (OCM) I-Cache (16KB) D-Cache (16KB) MMU (64 Entry TLB) Fetch & Decode Execution Unit (32x32 GPR, ALU, MAC) Timers and Debug Logic JTAG Instruction Trace 5-stage data path pipeline 16KB D and I Caches Embedded Memory Management Unit Execution Unit Multiply / divide unit 32 x 32-bit GPR Dedicated on-chip memory interfaces Timers: PIT, FIT, Watchdog Debug and trace support Performance: 450 DMIPS at 300 MHz 0.9mW/MHz Typical Power D-Side On-Chip Memory (OCM)

Virtex -II Family 12 Devices, 10 Packages, 37 combinations Virtex-II XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V Part Number 40 80 250 500 1000 1500 2000 3000 4000 6000 8000 10000 LUTs + FFs 512 1,024 3,072 6,144 10,240 15,360 21,504 28,672 46,080 67,584 93,184 122,880 BRAM (Kb) 72 144 432 576 720 864 1,008 1,728 2,160 2,592 1,024 3,456 Multipliers 4 8 24 32 40 48 56 96 120 144 168 192 DCM Units 4 4 8 8 8 8 8 12 12 12 12 12 CS144 88 92 92 FG256 88 120 172 172 172 FG456 200 264 324 FG676 392 456 484 FF896 432 528 624 FF1152 720 824 824 824 824 FF1517 912 1,104 1,108 1,108 BG575 328 392 408 BG728 456 516 BF957 624 684 684 684 684 684

XC9500XL Overview Superset of XC9500 CPLD Optimized for 3.3V systems compatible levels with 5.0/2.5V High f MAX = 200 MHz Fast t PD = 4 nsec Best ISP/JTAG support Best pin-locking Advanced packaging

Technology Optimized for high speed 3.3V systems Leading-edge FLASH technology 0.35um feature-size (0.25um Leff) 4 layers of metal Superior reliability Reprogramming endurance = 10,000 Charge retention = 20 years Fast programming characteristics

High Level Architecture

XC9500XL Family 9536XL 9572XL 95144XL 95288XL Macrocells 36 72 144 288 Usable Gates 800 1600 3200 6400 t PD (ns) 4 5 5 6 f MAX (MHz) 200 178 178 151 Packages 44PC 44PC QFP 64VQ 64VQ 100TQ 100TQ 144TQ 144TQ 208PQ CSP/BGA 48CS 48CS 144CS 352BG

Higher Density Enables New Applications Spartan-IIE 250K System Gates 30K FIFOs PALs HDLC UARTs 32-bit, 33-MHz PCI Spartan-XL 40K PCI- MIPS Bridge 64 Bit PCI Spartan-II 100K ATM Reed IMA Solomon Encoder Ethernet MAC Video Line Buffer 250k unit Cable Modem Graphics Card Office Networking Set-Top Box Embedded µpapps 1998 1999 2000 2001

Spartan-II Family Overview Device XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200 Logic Cells 432 972 1728 2700 3888 5292 Block RAM Bits 16,384 24,576 32,768 40,960 49,152 57,344 Block RAM Qty. 4 6 8 10 12 14 Max. User I/Os 86 132 176 196 260 284 Package VQ100 VQ100 CS144 CS144 TQ144 TQ144 TQ144 TQ144 PQ208 PQ208 PQ208 PQ208 PQ208 FG256 FG256 FG256 FG256 FG456 FG456 FG456

FPGA Device FPGA Design Flow & Synthesis DIP Rapid Prototyping Platform DIP Prototype System Measurement Design Example

FPGA Design Flow and Synthesis Specification System-Level Sim SystemC Model C/C++ Matlab / Simulink Device Selection Xilinx Altera Design Entry CoreGen LogiBox IP Verilog/VHDL Schematic FSM Verilog/VHDL/AHDL Schematic Waveform LPM MegaCore Design Entry Function Sim Simulation Model & TestBench Cadence Verilog-XL Synopsys VCSi Debussy ModelSim Synthesis Synthesis Constraints FPGA Compiler II FPGA Express Synplify LeonardoSpectrum FPGA Express FAE Synplify Synthesis Constraints Synthesis

FPGA Design Flow and Synthesis P&R P&R Constraints, Floorplaning Placement & Routing Back Annotate Routing Delay Fitting Back Annotate Routing Delay Fitting Constraints Fitting Timing Sim Timing Model & TestBench Cadence Verilog-XL Debussy Synopsys VCSi ModelSim Prototyping Third Party Prototyping Prototyping Development Programming & Debug Hardware Debugger Programmer Programming & Debug JTAG Programmer ChipScope ILA SignalTap

Xilinx ISE

ISE Design Flows

Project Navigator

Creating New Projects

Adding Source Files

Creating HDL Source

HDL Wizard

HDL Wizard Confirm information

Setting Implementation Option

Setting Synthesis Options

Accessing Advanced Options

Initiating a Design Flow

Accessing Reports

Static Timing Report

Proactive Timing Closure

Xilinx Synthesis Technology

HDL Bencher

HDL In, Test Bench Out

Simulating with Testbench Waveforms

ModelSim HDL Simulator

Using I/O Buffers

Configuration Download

Altera Quartus II

Design Methodologies Quartus supports three common design methodologies: Top-down Create a top-level of the design first, and then break down the design into lower-level design blocks. Bottom-up Begin by creating the lower-level design blocks first and then stitch together the design at the top-level. Middle-out Start in-between Top-down and Bottom-up design methodologies

PLD Design Flow(1)

PLD Design Flow(2)

Design Entry Multiple design entry methods Quartus Block/Schematic Editor Text Editor AHDL, VHDL, Verilog Memory Editor Hex, Mif Third party EDA tools EDIF HDL VQM Add flexibility and optimization to the design entry process by: Mixing and matching design files Using LPM and Megafunctions to accelerate design entry

Design Entry Files Quartus Block Editor Quartus Text Editor Quartus Memory Editor Verilog VHDL AHDL Schematic MegaWizard Manager Top- Level File Top-level design files can be.bdf,.tdf,.vhd,.vhdl,.v,.vlg,.edif or.edf Exemplar, Synopsys, Synplicity, etc... Schematic.bdf.gdf.bsf.tdf.vhd.v.edf.edif.v,.vlg,.vhd,.vhdl, vqm Block File Symbol File Text File Text File Text File Text File Text File Generated within Quartus Imported from third-party EDA tools

Main Toolbar and Modes

New Project Wizard What is the working directory for this project What is the name of this project What is the name of the top-level design entitiy in your project

New Project Wizard

Set Chips & Devices Device Select

Set User Libraries

Compiler Click this button to execute compiler Show the section of compiler summary When compilation was successful will appear this message Compiler Message

Timing Analysis Features Quartus II has built in static timing analysis Single clock timing analysis fmax (maximum clock frequency) Tsu, Th, Tco (setup time, hold time, clock-to-out time) Optional system fmax reporting Multi-clock analysis Allows analysis of multiple synchronous clocks Slack analysis is used

Timing Analysis

fmax The worst fmax is listed on the top. Select fmax

Locate Delay Path in Floorplan

Download Click this button to open programmer Make sure Type is ByteBlasterMV Make sure is JTAG Select.sof file to programmer

Download When it show 100% meaning download finished Enable this field

FPGA Device FPGA Design Flow & Synthesis DIP Rapid Prototyping Platform DIP Prototype System Measurement Design Example

IP Rapid Prototype Platform Altera Demo Board Xilinx Demo Board FPGA+µp Demo Board Application Specific Demo Board ARM SoC Development Platform

Nios Board (Altera) PIO_buttons Flash Configuration Controller SRAM seven_segment JTAG Header uart

EPXA10 Development Board (Altera) POWER BOOT_FLASH JP40 RS 232 Flash Mem UART JTAG Ethernet PCI Connector

EPXA10 Development Board Features Platform for Device Evaluation & Application Development Memory Support 1. SDR SDRAM: 256 Mbytes 2. Flash: 16 Mbytes Flexible Clocking 50-MHz Embedded Stripe Clock External Clock Generator Can Be Used Dedicated Stripe PLLs for Frequency Synthesis PLD Clocks Dedicated Crystals for Each of Four PLD PLLs Application Support Two UARTs ByteBlasterMV JTAG Connector Multi-ICE & Trace Port Connectors Ethernet PHY

EPXA10 Development Board Features PCI Two 3.3-V 33-MHz PCI Connectors Provided for Off-the-Shelf Applications User Interface 1. Eight LEDs 2. Four Push-Buttons 3. Nine-Position DIP Switch Power Supply 3.3-Volt DC Supply 1.8-V Generated 1.25-V Generated for V REF & V TT ATX Power Supply Required for PCI Same Voltage Regulation as 3.3-V DC Supply

Altera IP Development Kits APEX DSP Development Kit APLEX 20KE PCI Development Kit SOPC Development Board DIGILAB 10K*240 Development Board PROC20K Prototyping Board Bluetooth Prototype Board Constellation 20K Prototype Board PCISYS Data Acquistition and Processing PCI Board Megalogic 2A15 Development Board XT1000 Device Emulation Kit

MicroBlaze Kits with Boards (Xilinx)

MicroBlaze IP Peripherals Development Kit MicroBlaze CPU OPB Arbiter Watchdog Timer/Timebase Timer/Counter Block Interrupt Controller SRAM Controller Flash Memory Controller ZBT Memory Controller BRAM UART Lite GPIO SPI Master and Slave Additional Peripherals UART 16550 UART 16450 IIC Master & Slave Ethernet 10/100 MAC Future Peripherals ATM Utopia Level 2 SDRAM DDR

The FPGA + µp Demo Board DRAM Module µp 8051 or AVR A/D, D/A Module SRAM Module

The Hardware Module of FPGA+µp Demo Board 8051 or AVR

Application Specific Demo Board (Natl. Yunlin Univ.) ADC IC Image Sensor Input Power LED FPGA I/O Pin DIP Sw. UART JTAG FPGA I/O Pin E 2 PROM FPGA I/O Pin

ARM SoC Development Platform ARM Integrator ARM 720T Core module AP ASIC Development Platform Xilinx XCV2000E Logic module

ARM Integrator/AP System controller (FPGA) Clock generator Flash Memory(32MB) Boot Rom SRAM(512k) System expansion(cm,lm) PCI Interface, EBI Interface FPGA

System Architecture Peripheral input/output Core Module connectors Logic Module connectors HDR EXP System bus GPIO System controller FPGA PCI Host Bridge Standard PCI Slots PCI PCI bridge Flash SRAM Boot ROM EBI CompactPCI

System controller FPGA System Extrnal PCI bridge bus System bus (AHB) PCI bridge PCI Host Bridge System bus Local bus controller Interface Interface Arbiter Static memory controller External Bus Interface Flash,SSRAM and ROM I AHB/APB bridge Peripheral bus (APB) Counter/ timers Real time clock GPIO UART *2 KMI LED/ switch Interrupt controller status and Control register Peripheral input/output Interrupts System resources

Core Module(CM720T) 256KB to 1MB Synchronous SRAM SDRAM DIMM socket (up to 256MB) AMBA system bus interface to platform board Clock generators Reset controller JTAG interface to Multi-ICE ARM FPGA SDRAM (DIMM)

CM System Architecture SSRAM Clock generator Status / Control register Reset controller Memory bus SSRAM Controller (PLD) ARM core System bus bridge SDRAM controller FPGA SDRAM System bus Multi-ICE System bus connectors HDRA/HDRB

Logic Module(LM-XCV600E+) 1MB ZBT SRAM 9 General-purpose LEDs 8 General-purpose switches Clock generators Push button FPGA programming via Multi-ICE (JTAG) Flash-1 Flash-0 XCV2000E

LM System Architecture ZBT SSRAM OSC1 OSC2 Multi-ICE Trace Module/motherboard connectors FPGA Interface module connector LA connector Push button Switches LEDs Prototyping grid

System Architecture Core Module SSRAM Status/ Control register SDRAM ASB/PCI Bridge PCI Slot PCI Slot PCI Slot PCI/CPCI Bridge SSRAM Cntl ARM720T Sys Bus Bridge SDRAM Cntl AHB Arbiter AHB Bus Static memory cntl AHB/APB Bridge ROM Flash(32MB) SSRAM(512k) RTC UART AP Module Status/ control register Logic Module FLASH SSRAM FPGA APB Bus Counter/ Timers Keypad controller Interrupt Controller