IC芯片自主创新设计实验

IC 芯片自主创新设计实验 设计报告 设计题目 : 格雷码计数器芯片设计 设计学生 : 吴东生 ( 集成电路 ) 景国新 ( 固体电子 ) 林道明 ( 集成电路 ) 连维重 ( 集成电路 ) 施望 ( 集成电路 ) 刘锦秀 ( 集成电路 ) 刘中伟 ( 集成电路 ) 李梦宁 ( 集成电路 ) 指导教师 : 阮爱武 杜涛 指导单位 : 电子设计自动化技术 课程组

一 格雷码计数器芯片设计概述 功能描述 : 当使能有效 复位端无效, 时钟上升沿来临时, 以格雷码方式计数, 输出为四位 ( 满量程 16). 重复计数. 复位端有效, 清零 格雷码计数器引脚分布如下图 : RST EN CLK GND Core OUT0 VDD OUT1 OUT2 OUT3 引脚描述 : EN : 使能信号. 使芯片开始计数, 可以实现暂停功能 RST : 复位, 清零 CLK : 时钟信号 VDD_PAD :PAD 地 VSS_PAD: PAD 电源

VDD_CORE: CORE 地 VSS_CORE: CROE 电源 OUT[3:0] 输出四位计数值 二 格雷码计数器系统结构 En Rst 计数器 二进制转格雷码 数据寄存器 输出 Clk 三 格雷码计数器设计 1: 顶层 : 源代码如下 : library IEEE; use IEEE.std_logic_1164.all; entity gray_cunt is port( clk : in STD_LOGIC; en : in STD_LOGIC; rst : in STD_LOGIC; outdata : out STD_LOGIC_VECTOR(3 downto 0) end gray_cunt;

architecture rtl_top of gray_cunt is ---- Component declarations ----- component b2g port ( cunt : in STD_LOGIC_VECTOR(3 downto 0 gray : out STD_LOGIC_VECTOR(3 downto 0) end component; component cunt port ( clk : in STD_LOGIC; en : in STD_LOGIC; rst : in STD_LOGIC; outdata : out STD_LOGIC_VECTOR(3 downto 0) end component; component reg port ( clk : in STD_LOGIC; en : in STD_LOGIC; gray : in STD_LOGIC_VECTOR(3 downto 0 rst : in STD_LOGIC; outdata : out STD_LOGIC_VECTOR(3 downto 0) end component; ---- Signal declarations used on the diagram ---- signal BUS60 : STD_LOGIC_VECTOR (3 downto 0 signal BUS64 : STD_LOGIC_VECTOR (3 downto 0 ---- Component instantiations ---- U1 : b2g port map( cunt => BUS64, gray => BUS60 U2 : cunt port map( clk => clk, en => en,

outdata => BUS64, rst => rst U3 : reg port map( clk => clk, en => en, gray => BUS60, outdata => outdata, rst => rst end rtl_top; 2: 计数器部分 library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity cunt is port( en : in STD_LOGIC; rst : in STD_LOGIC; clk : in STD_LOGIC; outdata : out STD_LOGIC_VECTOR(3 downto 0) end cunt; --}} End of automatically maintained section architecture cunt of cunt is signal cout:std_logic_vector(3 downto 0 -- enter your statements here -- process (rst,clk) if(rst='0') then cout<="0000"; elsif (clk'event and clk='1') if(en='1') then then

if (cout="1111") then cout<="0000" ; else cout<=cout+'1' ; end if; end if; end if; end process ; outdata<=cout; end cunt; 3: 二进制转格雷码部分 library IEEE; use IEEE.STD_LOGIC_1164.all; entity b2g is port( cunt : in STD_LOGIC_VECTOR(3 downto 0 gray : out STD_LOGIC_VECTOR(3 downto 0) end b2g; --}} End of automatically maintained section architecture b2g of b2g is -- enter your statements here -- gray(0) <= cunt(0) xor cunt (1 gray(1) <= cunt(1) xor cunt (2 gray(2) <= cunt(2) xor cunt (3 gray(3) <= cunt(3) xor '0'; end b2g; 4: 寄存器部分 library IEEE; use IEEE.STD_LOGIC_1164.all; entity reg is port( en: in std_logic; clk : in STD_LOGIC;

rst : in STD_LOGIC; gray : in STD_LOGIC_VECTOR(3 downto 0 outdata : out STD_LOGIC_VECTOR(3 downto 0) end reg; --}} End of automatically maintained section architecture reg of reg is -- enter your statements here -- process(clk,rst) if(clk'event and clk='1')then if(en='1' and rst='1')then outdata<=gray; elsif(en='0')then null; elsif(rst='0')then outdata<="0000"; end if; else null; end if; end process; end reg; 四 功能仿真 仿真工具为 :ACTIVE-HDL6.1 格雷码计数器仿真波形如下 :

五 DC 综合 : 1: 网表文件 (gray_cunt_dc.v): module b2g ( cunt, gray input [3:0] cunt; output [3:0] gray; wire \cunt[3]; assign \cunt[3] = cunt[3]; assign gray[3] = \cunt[3] ; XO02D1 U7 (.A(cunt[2]),.B(\cunt[3] ),.Y(gray[2]) XO02D1 U8 (.A(cunt[0]),.B(cunt[1]),.Y(gray[0]) XO02D1 U9 (.A(cunt[1]),.B(cunt[2]),.Y(gray[1]) endmodule module cunt ( en, rst, clk, outdata output [3:0] outdata; input en, rst, clk; n168, n179; wire n181, n180, n158, n159, n160, n161, n162, n164, n166, n167, n169, n170, n171, n172, n173, n174, n175, n176, n177, n178, IN01D1 U41 (.A(en),.YN(n170) IN01D1 U42 (.A(n172),.YN(n174) XN02D1 U43 (.A(en),.B(outdata[0]),.YN(n159) IN01D2 U44 (.A(n159),.YN(n160)

IN01D1 U45 (.A(n168),.YN(n176) IN01D1 U46 (.A(n167),.YN(n171) OA04D1 U47 (.A1(n167),.A2(n173),.B(outdata[3]),.YN(n169) DFCTNH\cout_reg[3] (.CK(clk),.Q(outdata[3]),.QN(n158),.CDN(rst),.D( n177) DFCTNH\cout_reg[0] (.CK(clk),.Q(outdata[0]),.QN(n161),.CDN(rst),.D( n160) IN01D2 U48 (.A(n162),.YN(outdata[2]) MX21D2 U49 (.A0(n175),.A1(n173),.S(outdata[2]),.Y(n178) IN01D2 U50 (.A(n164),.YN(outdata[1]) MX21D2 U51 (.A0(n176),.A1(n172),.S(n181),.Y(n179) ND02D1 U52 (.A(n174),.B(outdata[1]),.YN(n173) AN02D1 U53 (.A(n176),.B(outdata[1]),.Y(n175) IN01D1 U54 (.A(n181),.YN(n166) OR03D1 U55 (.A(n162),.B(n158),.C(n166),.Y(n167) OR03D1 U56 (.A(n170),.B(n161),.C(n171),.Y(n168) ND02D2 U57 (.A(en),.B(outdata[0]),.YN(n172) OA16D2 (.A1(n180),.A2(n168),.A3(n166),.B(n169),.YN(n177) DFCTNB (.CK(clk),.Q(n180),.QN(n162),.CDN(rst),.D(n178) U58 \cout_reg[2] DFCTNB (.CK(clk),.Q(n181),.QN(n164),.CDN(rst),.D(n179) \cout_reg[1]

endmodule module \reg ( en, clk, rst, gray, outdata output [3:0] outdata; input [3:0] gray; input en, clk, rst; wire n22, net22, net23, net24, net25, n23, n24, n25, n26; OA09D2 (.A1(gray[0]),.A2(n22),.B1(en),.B2(net25),.YN(n26) OA09D2 (.A1(gray[1]),.A2(n22),.B1(en),.B2(net24),.YN(n25) OA09D2 (.A1(gray[2]),.A2(n22),.B1(en),.B2(net23),.YN(n24) OA09D2 (.A1(gray[3]),.A2(n22),.B1(en),.B2(net22),.YN(n23) U17 U18 U19 U20 ND02D2 U21 (.A(en),.B(rst),.YN(n22) DFNTNB (.CK(clk),.Q(outdata[3]),.QN(net22),.D(n23) DFNTNB (.CK(clk),.Q(outdata[2]),.QN(net23),.D(n24) DFNTNB (.CK(clk),.Q(outdata[1]),.QN(net24),.D(n25) DFNTNB (.CK(clk),.Q(outdata[0]),.QN(net25),.D(n26) \outdata_reg[3] \outdata_reg[2] \outdata_reg[1] \outdata_reg[0] endmodule

module gray_cunt ( clk, en, rst, outdata output [3:0] outdata; input clk, en, rst; wire \BUS64[3], \BUS64[2], \BUS64[1], \BUS64[0], \BUS60[3], \BUS60[1], \BUS60[2], \BUS60[0] ; b2g U1 (.cunt({\bus64[3], \BUS64[2], \BUS64[1], \BUS64[0] }),.gray({ \BUS60[3], \BUS60[2], \BUS60[1], \BUS60[0] }) cunt U2 (.en(en),.rst(rst),.clk(clk),.outdata({\bus64[3], \BUS64[2], \BUS64[1], \BUS64[0] }) \reg U3 (.en(en),.clk(clk),.rst(rst),.gray({\bus60[3], \BUS60[2], Endmodule 六 : 综合后仿真 : \BUS60[1], \BUS60[0] }),.outdata(outdata) 1:testbench 文件如下 : `timescale 1ns/10ps module gray_cunt_tb; //Internal signals declarations: reg clk; reg en; reg rst; wire [3:0]outdata; // Unit Under Test port map gray_cunt UUT (

.clk(clk),.en(en),.rst(rst),.outdata(outdata) initial $sdf_annotate("gray_cunt_dc.sdf",uut $shm_open ("shm.db" $shm_probe ("AC" clk =0; en=0; rst=1; end always #20 clk = ~clk; initial #2 rst = 1'b1; #53 en = 1'b0; #153 en = 1'b1; #153 rst = 1'b0; #153 rst = 1'b1; #2300 en = 1'b0; #153 rst = 1'b0; #100 $stop; end endmodule 2: 波形图 :

七 自动布局布线 core 自动布局布线后的仿真波形图如下 : 加 PAD 后的自动布局布线结果 :

八 MPW 加工 本项目选择 CSMC 0.5um 工艺, 采用 MPW 模式加工 芯片加 工后的实物照片如下图所示