台灣新竹 交通大學 電機與控制工程研究所 808 實驗室電力電子系統晶片 數位電源 DSP 控制 馬達與伺服控制 Lab-808: Power Electronic Systems & Chips Lab., NCTU, Taiwan http://pemclab.cn.nctu.edu.tw/ 數位電源控制應用的考量因素 鄒應嶼 教授 2007 年 12 月 1 日 國立交通大學電機與控制工程研究所 LAB808 NCTU Lab808: 電力電子系統與晶片實驗室 Power Electronic Systems & Chips, NCTU, TAIWAN 台灣新竹 交通大學 電機與控制工程研究所 1/33
Power Electronics Systems & Chips Lab., NCTU, Taiwan Why Digital Control for Power Electronics? 電力電子系統與晶片實驗室 Power Electronic Systems & Chips Lab. 交通大學 電機控制工程研究所 2/33
Why Digital Control for Power Electronics? 1. To achieve higher efficiency 2. Fast & Flexible: To achieve fast & programmable response dynamic power management & voltage regulation 3. To lower the cost (depends on applications & Manufactures) 4. To provide universal, robust, and green power adaptability 5. To provide efficient portable power management, Monitoring, and Control 6. To reduce design time time-to-market 7. To realize number of components by using programmable EEPROM based digital controller 8. To achieve self commissioning digital power supply without external compensation 9. To achieve better & effective system integration 10. To provide system solution for complicated power converting systems 3/33
1. To Achieve Higher Efficiency CRM Buck Inductor @ Standby Operation B B sat B B sat B B sat H c H H H i L 1 i 2 L i L ( AVG) 0 t 4/33
Digital Control Squeezes 40 A from Buck Converter Digital Control Squeezes 40 A from Buck Converter, Benoit Herve, Product Manager, Zilker 台灣新竹 交通大學 Labs, Austin, 電機與控制工程研究所 Texas, Power Electronics 電力電子實驗室 Technology, pp. ~ 32-37, 鄒應嶼 August 教授 2007 5/33
Efficiency as a Function of Control Scheme XC9217A18C (V OUT = 1.8V, 1.2 MHz) = 83% PMOS L V OUT Mode Change V IN C IN D C OUT NMOS Specification: V IN : 3.6V V OUT : 1.8V F OSC = 1.2MHz C IN : 4.7μF (Ceramic) L : 3.3μH (CDRH3D16 SUMIDA) C OUT : 10μF (Ceramic) PMOS R DS(ON) : 600m NMOS R DS(ON) : 700m 6/33
Efficiency as a Competition! (NXP1750) EPRI: Top 15 Average Efficiency (20%, 50%, 100%) NXP improves efficiency by: MOSFET switches replace rectifier diodes lower losses in output stage Adaptive mode-of-operation adjustment over the power range Efficiency Source: NXP Power 7/33
Green Mode PWM Control Strategy I IN 100% Load 50% Load 20% Load No Load t V PWM Minimum off-time t I L Maximum on-time SKIP CYCLE t 8/33
Typical Operating Modes of a Green Mode Controller IC Switching frequency f sw f ss (40kHz) SS mode (fixed f sw ) QR mode (valley switching) f MAX =Oscillator freq. (130kHz) f QR_MIN (internally limited to 40kHz) DCM (max f s ) Constant volt-sec f grmode_mx (40kHz) Burst operation (hard switching) This mode applies bursts of 40kHz soft-start pulses to the power MOSFET gate. The MOSFET gate. The average fsw is shown in this operating mode. t Load power P out P OUT,MAX load shown is slightly less than over current threshold IC off Soft start Resonant operation Fixed frequency Frequency foldback Burst operation t V status Status, pulled up to VDD Green mode, PFC bias OFF t 9/33
Output Characteristic and Auto-Restart 10 output voltage (V) 9 8 7 6 5 4 3 115 VAC 230 VAC limits auto-restart 2 1 0 0 100 200 300 400 500 600 700 output current (ma) Typical Output Characteristic for LinkSwitch Based 5.5 V, 0.5 A Charger with Specification Limits. (PI) 10/33
To Achieve Higher Efficiency Variable-Frequency Variable-Duty Control Lower Switching Higher Efficiency Random PWM Lower EMI Q 1 i o1 PWM 1 C 1 V dc 1 i L Q 2 i o2 V s PWM 2 C 2 V dc 2 1 Kv R s PWM 1 PWM 2 A D A D Kr K'vd D c (z) K pc + DIGITAL Vx PFC CONTROLLER Vc sinusoidal reference - current loop compensator Y=AB B A multiplier K pv ZOH D c (z) + voltage loop compensator PWM Modulator + - V ref _ K D D A A 1 Ko 1 Ko V dc1 V dc2 11/33
2. Fast & Flexible Si8250 Digital Power Controller High DSP Controller Microcontroller Digital PWM Controller Flexibility Microcontroller Analog PWM Analog PWM Low Low Response speed High 12/33
To Achieve Fast & Programmable Response Intel Pentium IV VRM Pentium IV 55,000,000 Tz 0.13 m 3.2GHz 1.7V Rated Power: 92W Peak Power: 110W 13/33
To Achieve Fast & Programmable Response Digital Controller V in L1 L2 I L I O V O ADC Control law DPWM L3 R ESR C O L4 14/33
To Achieve Fast & Programmable Response V ref e 4 3 2 1 0 1 2 3 4 V q e[n] e[n 1] T s T s Table A Table B T s d[n 1] d[n] Vref V o e[n 2] Table C (ΔV o ) max V sense SENSE A/D converter Table-Lookup Digital Controller Digital PWM Generator To Achieve One-Cycle Dead-Beat Response 15/33
To Achieve Fast & Programmable Response Adaptive voltage positioning offset V OFFSET (40mV) Nominal set point voltage V SET (2.0V) Dynamic voltage tolerance, V DYN- (100mV for 2 s) Output voltage V OUT (50mV/Div) Steady state voltage at high current is approximately V SET V OFFSET I OUT R SENSE Initial voltage drop is mainly due to the product of the load current step and ESR of the capacitors. V = I ESR. (ESL effects are ignored) L 2.5 H; C OUT 6 1500 F Sanyo MV - GX; RSENSE Output current transient step, I = 0 to 14A (5A/Div) 2.5m Intel: VRM (Voltage Regulator Module) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines, Nov. 2006. 16/33
3. To Lower the Cost (Simple Hardware) F 1 K 1 J 1 L s Q 1 Q 3 C 1 AC Input CT 1 D 1 D 3 K CT L 2 2 o CT 3 Q 2 C 2 Q 4 C o R o Load D 2 D 4 T 1 F 2 D 5 D 7 Q 5 Q 6 C 3 D 6 D 8 Battery 17/33
3. To Lower the Cost (Simple Hardware) Higher integration Smaller size Enables complex, non-linear control algorithms Higher efficiency Faster control response Tighter regulation Firmware-programmable Faster time-to-market Easily customized Lower cost Fewer components Easier to test More reliable 台灣新竹 Source: 交通大學 Silicon Laboratory 電機與控制工程研究所 電力電子實驗室 ~ 鄒應嶼教授 18/33
Digital Solution for Performance/Cost Improvement V out R 3 R 1 R 2 C 1 C 2 C 3 Reference V comp GUI GUI PC USB OR PMBus PMBus power supply power supply V IN V OUT V IN V OUT Digital Filter Equivalent 13K Gates 0.25um CMOS 0.22 mm 2 No external components Digital Power Solution! Take advantage of VLSI process VLSI performance superior than analog Provides more functions than analog Programmable via PMBus protocol Programmable (sequencing, Vo) Monitoring (fault) Performance superior tha analog Efficiency optimization for multi-mode operation Smart power Higher efficiency & faster response Power OS: self-tuning/diagnosis Performance/functions beyond analog power 19/33
Control Techniques Cuts Flyback Input Capacitance No PFC for low power applications Hold-up time requirement for critical applications Reduction of input capacitance for desired hold-up time DCM with Fixed-Frequency or Duty-Cycle Extension Rahul Joshi, "Control Technique Cuts Flyback Input Capacitance," Power Electronics Technology, April 2007. 20/33
4. To Provide Universal and Green Power Adaptability Universal input Reliable Efficient Standby Power System solutions 21/33
5. To Provide Efficient Portable Power Management Power Management DC/DC Battery Charger Power Drive Logic Accelerators (bit level) phone RTOS book Keypad, Display Control ARQ A D FSM FFT Filters C core (ARM) analog digital Dedicated Logic Coders DSP cores Analog Baseband and RF Circuits Communication Algorithms Protocols 22/33
6. To Meet the Voltage Scaling Requirement V DD a a P D α 1 2 CV 2 dd f c N C 5 factors of dynamic power dissipation and low power design strategies Supply voltage (voltage scaling) Switching activity (scheduling) Total no. of transistors (circuit minimization) Operating frequency (IC layout, process innovation) Physical capacitance (process innovation) These parameters are not completely orthogonal and cannot be optimized independently. 23/33
7. To Speedup Design Process Analog Controller 10 3 magnitude response 12V 10 2 V OUT 10 1 10 0 10 1 10 2 10 3 10 4 10 5 frequency(rad/sec) 50 phase response V REF Gate Drive 0-50 10 0 10 1 10 2 10 3 10 4 10 5 frequency(rad/sec) (a) Digital controller 12V V OUT V REF Digital compensator Digital modulator Gate Drive (b) 24/33
7. To Speedup Design Process Gain Bode plot Analog Controller 12V V OUT F Z1 F P0 F Z2 F P1 F P2 Freq. V REF Gate Drive Digital controller (a) 12V V OUT V REF Digital compensator Digital modulator Gate Drive (b) 25/33
Comprehensive, Low-Cost Development Kit Complete development kit to simplify design: Real-time firmware kernel Greatly reduces firmware design Automated development tools Compensation Designer/Simulator Timing Designer/Simulator System and MCU Configuration Wizards Si8250-based half-bridge DC/DC target board All necessary cables and a country specific power supply Full Development Kit for only $199 Source: Silicon Laboratory 26/33
8. To Realize Complex Control Algorithm AC load 110/220V 50/60 Hz Rectifier Charger Inverter T 1 C 1 Motor/ Generator Flywheel EMI 3-phase load + Battery T 2 C 2 _ Power Factor Control Regenerative Braking Control DC-Link Voltage Regulation DC-Link Cap. Minimization ε u u d PWM Control Vector Control Current Control Voltage Control Power Flow Control Auto-Tuning 27/33
8. To Realize Complex Control Algorithm AC load 110/220V 50/60 Hz Rectifier Charger Inverter T 1 C 1 Motor/ Generator Flywheel EMI 3-phase load + Battery T 2 C 2 _ Current, Voltage & Temp Sensor Taxi Transmitter ADC DSP FPGA Gate Driver & Fault Sensing Gate Driver & Fault Sensing Gate Driver & Fault Sensing Taxi Receiver Isolated Power Supplies Gate Driver & Fault Sensing 28/33
8. To Realize Complex Control Algorithm AC load 110/220V 50/60 Hz Rectifier Charger Inverter T 1 C 1 Motor/ Generator Flywheel EMI 3-phase load + Battery T 2 C 2 _ 29/33
9. To Achieve Self-Compensation Digital Power Supply 台灣新竹 交通大學 電機與控制工程研究所 電力電子實驗室~鄒應嶼 教授 30/33
10. To Achieve Better & Effective System Integration Boost Converter Inverter Grid connected L Diode L SB S1 S3 Grid S2 S4 Current sensor Power Transformer Monitoring Software RS-232 USB SNMP TCP/IP Vpv Ipv Adaptive Fuzzy Logic PWM Vdc bus Vdc reference + Gate Drive Predicted Current Control Voltage Regulator Current Regulator Multiplier Reference signal 31/33
External passive components: Analog Control is Inflexible and Bulky Fixed control response and timing Change with age & temperature Consume space/increase cost Vin RFI filter and surge suppression IC bias supply Vout Other feed-forward signals IPK Leading-edge Blank timing components Input Rectifiers And filters temp Temp IPK Control Interface circuits Loop Compensation components Soft-start components Threshold Setting components Threshold Setting components Input overvoltage protection circuitry Over temp protection circuitry OVP Temp sensor IPK sensor Error amp VREF ILIM comparator Under Voltage lockout Control logic VIN Feedforward components Power Stages Controller modulator Modulator Timing components Specialized timing circuitry Gate timing signals Output filters Output overvoltage protection circuitry OVP (to controller logic) Vout Crowbar circuitry External protection circuits: Fixed protection settings Consume space/increase cost Other external circuits: Supplement controller function Fixed functions Consume space/increase cost 32/33
Digital Control is Adaptive and Compact Vin RFI filter and surge suppression IC bias supply Temp Input Rectifiers And filters IPK Other feed-forward signals Vout IPK Temp sensor IPK sensor Power Stages Si8250 System management processor OSC & CUP support 12 bit ADC CUP memory Control processor 100MHz ADC & VREF IPK Limiter & OCP Filter DSP engine Digital peripheral I/O DPWM Gate timing signals Entire control function: Power control + power management Minimizes space, reduces BOM - Significant component reduction - Built-in temperature sensor Output filters Vout Crowbar circuitry Programmable operation: Fault protection and recovery Adaptive control response Timing optimization Feed forward algorithms Programmable soft-start ramp System power mgmt tasks Dynamic control response: Nonlinear control response - Faster transient response Dead time control - Higher Efficiency 33/33