8088/8086 MICROPROCESSOR PROGRAMMING INTEGER INSTRUCTIONS AND COMPUTATIONS 8088/8086 MICROPROCESSOR PROGRAMMING INTEGER INSTRUCTIONS AND COMPUTATIONS 5.1 Data-Transfer Instructions 5.2 Arithmetic Instructions 5.3 Logic Instructions 5.4 Shift Instructions 5.5 Rotate Instructions 611 37100 微處理機原理與應用 Lecture 05-2 1
5.1 Data-Transfer Instructions The data-transfer functions provide the ability to move data either between its internal registers or between an internal register and a storage location in memory. The data-transfer functions include MOV (Move byte or word) XCHG (Exchange byte or word) XLAT (Translate byte) LEA (Load effective address) LDS (Load data segment) LES (Load extra segment) 611 37100 微處理機原理與應用 Lecture 05-3 5.1 Data-Transfer Instructions The MOVE Instruction The move (MOV) instruction is used to transfer a byte or a word of data from a source operand to a destination operand. Mnemonic Meaning Format Operation Flags affected MOV Move MOV D, S (S) (D) None e.g. MOV DX, CS MOV [SUM], AX 611 37100 微處理機原理與應用 Lecture 05-4 2
5.1 Data-Transfer Instructions The MOVE Instruction Note that the MOV instruction cannot transfer data directly between external memory. Destination Accumulator Seg-reg Seg-reg Reg16 Source Accumulator Immediate Immediate Reg16 Mem16 Seg-reg Seg-reg Allowed operands for MOV instruction 611 37100 微處理機原理與應用 Lecture 05-5 5.1 Data-Transfer Instructions The MOVE Instruction MOV DX, CS 0100 IP 0100 CS 0200 DS SS ES Address 01100 01101 01102 Content 8C CA Instruction MOV DX, CS Next instruction AX BX CX DX 02000 02001 SP BP SI DI 8088/8086 MPU Before execution 611 37100 微處理機原理與應用 Lecture 05-6 3
5.1 Data-Transfer Instructions The MOVE Instruction MOV DX, CS 0102 IP 0100 CS 0200 DS SS ES Address 01100 01101 01102 Content 8C CA Instruction MOV DX, CS Next instruction AX BX CX 0100 DX 02000 02001 SP BP SI DI 8088/8086 MPU After execution 611 37100 微處理機原理與應用 Lecture 05-7 5.1 Data-Transfer Instructions What is the effect of executing the instruction MOV CX, [SOURCE_MEM] Where SOURCE_MEM equal to 20 16 is a memory location offset relative to the current data segment starting at 1A000 16. ((DS)0+20 16 ) (CL) ((DS)0+20 16 +1 16 ) (CH) Therefore CL is loaded with the contents held at memory address 1A000 16 + 20 16 = 1A020 16 and CH is loaded with the contents of memory address 1A000 16 + 20 16 +1 16 = 1A021 16 611 37100 微處理機原理與應用 Lecture 05-8 4
5.1 Data-Transfer Instructions Use the DEBUG the verify the previous example. 611 37100 微處理機原理與應用 Lecture 05-9 5.1 Data-Transfer Instructions The XCHG Instruction The exchange (XCHG) instruction can be used to swap data between two general-purpose registers or between a generalpurpose register and a storage location in memory. Mnemonic Meaning Format Operation Flags affected XCHG Exchange XCHG D, S (D) (S) None e.g. XCHG AX, DX Destination Accumulator Source Reg16 611 37100 微處理機原理與應用 Lecture 05-10 Allowed operands for XCHG instruction 5
5.1 Data-Transfer Instructions What is the result of executing the following instruction? XCHG [SUM], BX Where SUM = 1234 16, (DS)=1200 16 ((DS)0+SUM) (BX) PA = 12000 16 + 1234 16 =13234 16 Execution of the instruction performs the following 16-bit swap: (13234 16 ) (BL) (13235 16 ) (BH) So we get (BX) = 00FF 16 (SUM) = 11AA 16 611 37100 微處理機原理與應用 Lecture 05-11 5.1 Data-Transfer Instructions The XCHG Instruction XCHG [SUM], BX 0101 IP 1100 CS 1200 DS SS ES Address 11101 11102 11103 11104 11105 Content 87 1E 34 12 Instruction XCHG [SUM],BX Next instruction AX 11 AA BX CX DX SP BP SI DI 8088/8086 MPU 12000 12001.... 13234 13235 FF 00 Variable SUM Before execution 611 37100 微處理機原理與應用 Lecture 05-12 6
5.1 Data-Transfer Instructions The XCHG Instruction XCHG [SUM], BX 0105 IP 1100 CS 1200 DS SS ES Address 11101 11102 11103 11104 11105 Content 87 1E 34 12 Instruction XCHG [SUM],BX Next instruction AX 00 FF BX CX DX SP BP SI DI 8088/8086 MPU 12000 12001.... 13234 13235 AA 11 Variable SUM After execution 611 37100 微處理機原理與應用 Lecture 05-13 5.1 Data-Transfer Instructions Use the DEBUG program to verify the previous example. 611 37100 微處理機原理與應用 Lecture 05-14 7
5.1 Data-Transfer Instructions Use the DEBUG program to verify the previous example. 611 37100 微處理機原理與應用 Lecture 05-15 5.1 Data-Transfer Instructions The XLAT Instruction The translate (XLAT) instruction is used to simplify implementation of the lookup-table operation. Execution of the XLAT replaces the contents of AL by the contents of the accessed lookup-table location. Mnemonic Meaning Format Operation Flags affected XLAT Translate XLAT ((AL)+(BX)+(DS)0) (AL) None e.g. PA = (DS)0 + (BX) + (AL) = 03000 16 + 0100 16 + 0D 16 = 0310D 16 (0310D 16 ) (AL) 611 37100 微處理機原理與應用 Lecture 05-16 8
5.1 Data-Transfer Instructions The LEA, LDS, and LES Instructions The LEA, LDS, LES instructions provide the ability to manipulate memory addresses by loading either a 16-bit offset address into a general-purpose register or a register together with a segment address into either DS or ES. Mnemonic Meaning Format Operation Flags affected LEA Load effective address LEA Reg16, EA EA (Reg16) None LDS Load register and DS LDS Reg16, Mem32 (Mem32) (Reg16) (Mem32+2) (DS) None LES Load register and ES LES Reg16,Mem32 (Mem32) (Reg16) (Mem32+2) (ES) None e.g. LEA SI, [DI+BX+5H] 611 37100 微處理機原理與應用 Lecture 05-17 5.1 Data-Transfer Instructions The LEA, LDS, and LES Instructions LDS SI, [200H] 0100 IP 1100 CS 1200 DS SS ES Address 11100 11101 11102 11103 11104 Content C5 36 00 02 Instruction LDS SI, [200H] Next instruction AX BX CX DX SP BP SI DI 12000 12001.. 12200 12201 12202 12203 20 00 00 13 8088/8086 MPU Before execution 611 37100 微處理機原理與應用 Lecture 05-18 9
5.1 Data-Transfer Instructions The LEA, LDS, and LES Instructions LDS SI, [200H] 0104 IP 1100 CS 1300 DS SS ES Address 11100 11101 11102 11103 11104 Content C5 36 00 02 Instruction LDS SI, [200H] Next instruction AX BX CX DX SP BP 0020 SI DI 8088/8086 MPU After execution 611 37100 微處理機原理與應用 Lecture 05-19 12000 12001.. 12200 12201 12202 12203.. 13000 13001 20 00 00 13 New data segment 5.1 Data-Transfer Instructions Verify the following instruction using DEBUG program. LDS SI, [200H] 611 37100 微處理機原理與應用 Lecture 05-20 10
5.1 Data-Transfer Instructions Initializing the internal registers of the 8088 from a table in memory. MOV AX, [INIT_TABLE] MOV SS, AX LDS SI, [INIT_TABLE+02H] LES DI, [INIT_TABLE+06H] MOV AX, [INIT_TABLE+0AH] MOV BX, [INIT_TABLE+0CH] MOV CX, [INIT_TABLE+0EH] MOV DX, [INIT_TABLE+10H] 611 37100 微處理機原理與應用 Lecture 05-21 5.2 Arithmetic Instructions The arithmetic instructions include Addition Subtraction Multiplication Division Data formats Unsigned binary bytes Signed binary bytes Unsigned binary words Signed binary words Unpacked decimal bytes Packed decimal bytes ASCII numbers 611 37100 微處理機原理與應用 Lecture 05-22 11
5.2 Arithmetic Instructions ADDITION ADD Add byte or word ADC Add byte or word with carry INC Increment byte or word by 1 AAA ASCII adjust for addition DAA Decimal adjust for addition SUBTRACTION SUB Subtract byte or word SBB Subtract byte or word with borrow DEC Decrement byte or word by 1 NEG Negate byte or word AAS ASCII adjust for subtraction DAS Decimal adjust for subtraction MULTIPLICATION MUL Multiply byte or word unsigned IMUL Integer multiply byte or word AAM ASCII adjust for multiply DIVISION DIV Divide byte or word unsigned IDIV Integer divide byte or word AAD ASCII adjust for division CBW Convert byte to word CWD Convert word to doubleword 611 37100 微處理機原理與應用 Lecture 05-23 5.2 Arithmetic Instructions Addition Instructions: ADD, ADC, INC, AAA, DAA Mnemonic Meaning Format Operation Flags affected ADD Addition ADD D, S (S) +(D) (D) Carry (CF) OF, SF, ZF, AF, PF, CF ADC Add with carry ADC D, S (S) +(D)+(CF) (D) Carry (CF) OF, SF, ZF, AF, PF, CF INC Increment by 1 INC D (D) +1 (D) OF, SF, ZF, AF, PF AAA ASCII adjust for addition AAA AF, CF OF, SF, ZF, PF undefined DAA Decimal adjust for addition DAA SF, ZF, AF, PF, CF, OF undefined 611 37100 微處理機原理與應用 Lecture 05-24 12
5.2 Arithmetic Instructions Addition Instructions: ADD, ADC, INC, AAA, DAA Destination Accumulator Source Immediate Immediate Immediate Destination Reg16 Reg8 Allowed operands for ADD and ADC instructions Allowed operands for INC instruction 611 37100 微處理機原理與應用 Lecture 05-25 5.2 Arithmetic Instructions Assume that the AX and BX registers contain 1100 16 and 0ABC 16, respectively. What is the result of executing the instruction ADD AX, BX? (BX)+(AX)= 0ABC 16 + 1100 16 =1BBC 16 The sum ends up in destination register AX. That is (AX) = 1BBC 16 611 37100 微處理機原理與應用 Lecture 05-26 13
5.2 Arithmetic Instructions Addition Instructions: ADD, ADC, INC, AAA, DAA ADD AX, BX 0100 IP 1100 CS 1200 DS SS ES Address 11100 11101 11102 Content 03 C3 Instruction ADD AX, BX Next instruction 1100 AX 0ABC BX CX DX 12000 12001 SP BP SI DI 8088/8086 MPU Before execution 611 37100 微處理機原理與應用 Lecture 05-27 5.2 Arithmetic Instructions Addition Instructions: ADD, ADC, INC, AAA, DAA ADD AX, BX 0102 IP 1100 CS 1200 DS SS ES 1BBC AX 0ABC BX CX DX SP BP SI DI 8088/8086 MPU After execution 611 37100 微處理機原理與應用 Lecture 05-28 Address 11100 11101 11102 12000 12001 Content 03 C3 Instruction ADD AX, BX Next instruction 14
5.2 Arithmetic Instructions Verify the previous example using DEBUG program. 611 37100 微處理機原理與應用 Lecture 05-29 5.2 Arithmetic Instructions The original contents of AX, BL, word-size memory location SUM, and carry flag (CF) are 1234 16, AB 16, 00CD 16, and 0 16, respectively. Describe the results of executing the following sequence of instruction? ADD AX, [SUM] ADC BL, 05H INC WORD PTR [SUM] (AX) (AX)+(SUM) = 1234 16 + 00CD 16 =1301 16 (BL) (BL)+imm8+(CF) = AB 16 + 5 16 +0 16 = B0 16 (SUM) (SUM)+ 1 16 = 00CD 16 + 1 16 = 00CE 16 611 37100 微處理機原理與應用 Lecture 05-30 15
5.2 Arithmetic Instructions What is the result of executing the following instruction sequence? ADD AL, BL AAA Assuming that AL contains 32 16 (ASCII code for 2) and BL contains 34 16 (ASCII code 4), and that AH has been cleared. (AL) (AL)+(BL)= 32 16 + 34 16 =66 16 The result after the AAA instruction is (AL) = 06 16 (AH) = 00 16 with both AF and CF remain cleared 611 37100 微處理機原理與應用 Lecture 05-31 5.2 Arithmetic Instructions Perform a 32-bit binary add operation on the contents of the processor s register. (DX,CX) (DX,CX)+(BX,AX) (DX,CX) = FEDCBA98 16 (BX,AX) = 01234567 16 MOV DX, 0FEDCH MOV CX, 0BA98H MOV BX, 01234H MOV AX, 04567H ADD CX, AX ADC DX, BX 611 37100 微處理機原理與應用 Lecture 05-32 ; Add with carry 16
5.2 Arithmetic Instructions Subtraction Instructions: SUB, SBB, DEC, AAS, DAS, and NEG Mnemonic Meaning Format Operation Flags affected SUB Subtract SUB D, S (D)-(S) (D) Borrow (CF) OF, SF, ZF, AF, PF, CF SBB Subtract with borrow SBB D, S (D)-(S)-(CF) (D) OF, SF, ZF, AF, PF, CF DEC Decrement by 1 DEC D (D)-1 (D) OF, SF, ZF, AF, PF NEG Negate NEG D 0-(D) (D) 1 (CF) OF, SF, ZF, AF, PF,CF DAS Decimal adjust for subtraction DAS SF, ZF, AF, PF, CF, OF undefined AAS ASCII adjust for subtraction AAS AF,CF OF,SF, ZF,PF undefined 611 37100 微處理機原理與應用 Lecture 05-33 5.2 Arithmetic Instructions Subtraction Instructions: SUB, SBB, DEC, AAS, DAS, and NEG Destination Source Accumulator Immediate Immediate Immediate Destination Reg16 Reg8 Destination Allowed operands for SUB and SBB instructions Allowed operands for DEC instruction Allowed operands for NEG instruction 611 37100 微處理機原理與應用 Lecture 05-34 17
5.2 Arithmetic Instructions Assuming that the contents of register BX and CX are 1234 16 and 0123 16, respectively, and the carry flag is 0, what is the result of executing the instruction SBB BX, CX? (BX)-(CX)-(CF) (BX) We get (BX) = 1234 16 0123 16 0 16 = 1111 16 the carry flag remains cleared. 611 37100 微處理機原理與應用 Lecture 05-35 5.2 Arithmetic Instructions Verify the previous example using DEBUG program. 611 37100 微處理機原理與應用 Lecture 05-36 18
5.2 Arithmetic Instructions Assuming that the register BX contains 003A 16, what is the result of executing the following instruction? NEG BX (BX) = 0000 16 -(BX)=0000 16 +2 complement of 003A 16 = 0000 16 +FFC6 16 = FFC6 16 Since no carry is generated in this add operation, the carry flag is complemented to give (CF) = 1 611 37100 微處理機原理與應用 Lecture 05-37 5.2 Arithmetic Instructions Verify the previous example using DEBUG program. 611 37100 微處理機原理與應用 Lecture 05-38 19
5.2 Arithmetic Instructions Perform a 32-bit binary subtraction for variable X and Y. MOV SI, 200H MOV DI, 100H MOV AX, [SI] SUB AX, [DI] MOV [SI],AX MOV AX, [SI]+2 SBB AX, [DI]+2 MOV [SI]+2, AX ; Initialize pointer for X ; Initialize pointer for Y ; Subtract LS words ; Save the LS word of result ; Subtract MS words ; Save the MS word of result 611 37100 微處理機原理與應用 Lecture 05-39 5.2 Arithmetic Instructions Multiplication Instructions: MUL, DIV, IMUL, IDIV, AAM, AAD, CBW, and CWD Mnemonic MUL DIV IMUL IDIV Meaning Multiply (unsigned) Division (unsigned) Integer multiply (signed) Integer divide (signed) Format MUL S DIV S IMUL S IDIV S Operation (AL) (S8) (AX) (AX) (S16) (DX)(AX) (1)Q((AX)/(S8)) (AL) R((AX)/(S8)) (AH) (2)Q((DX,AX)/(S16)) (AX) R((DX,AX)/(S16)) (DX) If Q is FF 16 in case (1) or FFFF 16 in case (2), then type 0 interrupt occurs (AL) (S8) (AX) (AX) (S16) (DX)(AX) (1)Q((AX)/(S8)) (AL) R((AX)/(S8)) (AH) (2)Q((DX,AX)/(S16)) (AX) R((DX,AX)/(S16)) (DX) If Q is positive and exceeds 7FFF 16 or if Q is negative and become less than 8001 16, then type 0 interrupt occurs Flags affected OF, CF SF,ZF, AF, PF undefined OF, SF, ZF, AF, PF, CF undefined OF, CF SF,ZF, AF, PF undefined OF, SF, ZF, AF, PF, CF undefined 611 37100 微處理機原理與應用 Lecture 05-40 20
5.2 Arithmetic Instructions Multiplication Instructions: MUL, DIV, IMUL, IDIV, AAM, AAD, CBW, and CWD Mnemonic AAM AAD CBW CWD Meaning Adjust AL for multiplication Adjust AX for division Convert byte to word Convert word to double word Format Operation AAM Q((AL)/10) (AH) R((AL)/10) (AL) AAD (AH) 10+(AL) (AL) 00 (AH) CBW (MSB of AL) (All bits of AH) CWD (MSB of AX) (All bits of DX) Flags affected SF,ZF,PF OF,AF,CF undefined SF,ZF,PF OF,AF,CF undefined None None Destination Reg8 Reg16 Mem8 Mem16 Allowed operands 611 37100 微處理機原理與應用 Lecture 05-41 5.2 Arithmetic Instructions The 2 s-complement signed data contents of AL are 1 and that of CL are 2. What result is produced in AX by executing the following instruction? MUL CL and IMUL CL (AL) = -1 (as 2 s complement) = 11111111 2 = FF 16 (CL) = -2 (as 2 s complement) = 11111110 2 = FE 16 Executing the MUL instruction gives (AX) = 11111111 2 x11111110 2 =1111110100000010 2 =FD02 16 Executing the IMUL instruction gives (AX) = -1 16 x -2 16 = 2 16 = 0002 16 611 37100 微處理機原理與應用 Lecture 05-42 21
5.2 Arithmetic Instructions Verify the previous example using DEBUG program. 611 37100 微處理機原理與應用 Lecture 05-43 5.2 Arithmetic Instructions What is the result of executing the following instructions? MOV AL, 0A1H CBW CWD (AL) = A1 16 = 10100001 2 Executing the CBW instruction extends the MSB of AL (AH) = 11111111 2 = FF 16 or (AX) = 1111111110100001 2 Executing the CWD instruction, we get (DX) = 1111111111111111 2 = FFFF 16 That is, (AX) = FFA1 16 (DX) = FFFF 16 611 37100 微處理機原理與應用 Lecture 05-44 22
5.3 Logic Instructions The logic instructions include AND OR XOR (Exclusive-OR) NOT Mnemonic Meaning Format Operation Flags affected AND Logical AND AND D, S (S) (D) (D) OF, SF, ZF, PF, CF AF undefined OR Logical Inclusive-OR OR D, S (S) (D) (D) OF, SF, ZF, PF, CF AF undefined XOR Logical exclusive-or XOR D, S (S) (D) (D) OF, SF, ZF, PF, CF AF undefined NOT Logical NOT NOT D (NOT D) (D) None 611 37100 微處理機原理與應用 Lecture 05-45 5.3 Logic Instructions Logic instructions : AND, OR, XOR, NOT Destination Accumulator Source Immediate Immediate Immediate Destination Allowed operands for AND, OR, and XOR instructions Allowed operands for NOT instruction 611 37100 微處理機原理與應用 Lecture 05-46 23
5.3 Logic Instructions Describe the results of executing the following instructions? MOV AL, 01010101B AND AL, 00011111B OR AL, 11000000B XOR AL, 00001111B NOT AL (AL)=01010101 2 00011111 2 = 00010101 2 =15 16 Executing the OR instruction, we get (AL)= 00010101 2 +11000000 2 = 11010101 2 =D5 16 Executing the XOR instruction, we get (AL)= 11010101 2 00001111 2 = 11011010 2 =DA 16 Executing the NOT instruction, we get (AL)= (NOT)11011010 2 = 00100101 2 =25 16 611 37100 微處理機原理與應用 Lecture 05-47 5.3 Logic Instructions Masking and setting bits in a register. Mask off the upper 12 bits of the word of data in AX AND AX, 000F 16 Setting B 4 of the byte at the offset address CONTROL_FLAGS MOV AL, [CONTROL_FLAGS] OR AL, 10H MOV [CONTROL_FLAGS], AL Executing the above instructions, we get (AL)= 2 +00010000 2 = X1 2 611 37100 微處理機原理與應用 Lecture 05-48 24
5.4 Shift Instructions Shift instructions: SHL, SHR, SAL, SAR Mnemonic SAL/SHL SHR SAR Meaning Shift arithmetic left / Shift logical left Shift logical right Shift arithmetic right Format SAL D, Count SHL D, Count SHR D, Count SAR D, Count Operation Shift the (D) left by the number of bit positions equal to Count and fill the vacated bits positions on the right with zeros Shift the (D) right by the number of bit positions equal to Count and fill the vacated bits positions on the left with zeros Shift the (D) right by the number of bit positions equal to Count and fill the vacated bits positions on the left with the original most significant bits Flags affected CF, PF, SF, Z AF undefined OF undefined if count 1 CF, PF, SF, Z AF undefined OF undefined if count 1 CF, PF, SF, Z AF undefined OF undefined if count 1 611 37100 微處理機原理與應用 Lecture 05-49 5.4 Shift Instructions Shift instructions: SHL, SHR, SAL, SAR Destination Count 1 CL 1 CL Allowed operands for shift instructions 611 37100 微處理機原理與應用 Lecture 05-50 25
5.4 Shift Instructions Shift instructions: SHL, SHR, SAL, SAR SHL AX, 1 SHR AX, CL SAR AX, CL 611 37100 微處理機原理與應用 Lecture 05-51 5.4 Shift Instructions Assume that CL contains 02 16 and AX contains 091A 16. Determine the new contents of AX and the carry flag after the instruction SAR AX, CL is executed. (AX)=0000001001000110 2 =0246 16 and the carry flag is (CF)=1 2 611 37100 微處理機原理與應用 Lecture 05-52 26
5.4 Shift Instructions Verify the previous example using DEBUG program. 611 37100 微處理機原理與應用 Lecture 05-53 5.4 Shift Instructions Isolate the bit B 3 of the byte at the offset address CONTROL_FLAGS. MOV AL, [CONTROL_FLAGS] MOV CL, 04H SHR AL, CL Executing the instructions, we get (AL)=0000B 7 B 6 B 5 B 4 and (CF)=B 3 611 37100 微處理機原理與應用 Lecture 05-54 27
5.5 Rotate Instructions Rotate instructions: ROL, ROR, RCL, RCR Mnemonic ROL ROR RCL Meaning Rotate left Rotate right Rotate left through carry Format ROL D, Count ROR D, Count RCL D, Count Operation Rotate the (D) left by the number of bit positions equal to Count. Each bit shifted out from the leftmost bit goes back into the rightmost bit position. Rotate the (D) right by the number of bit positions equal to Count. Each bit shifted out from the rightmost bit goes back into the leftmost bit position. Same as ROL except carry is attached to (D) for rotation. Flags affected CF OF undefined if count 1 CF OF undefined if count 1 CF OF undefined if count 1 RCR Rotate right through carry RCR D, Count Same as ROR except carry is attached to (D) for rotation. CF OF undefined if count 1 611 37100 微處理機原理與應用 Lecture 05-55 5.5 Rotate Instructions Rotate instructions: ROL, ROR, RCL, RCR Destination Count 1 CL 1 CL Allowed operands for rotate instructions 611 37100 微處理機原理與應用 Lecture 05-56 28
5.5 Rotate Instructions Rotate instructions: ROL, ROR, RCL, RCR ROL AX, 1 ROR AX, CL (CL)=4 611 37100 微處理機原理與應用 Lecture 05-57 5.5 Rotate Instructions Rotate instructions: ROL, ROR, RCL, RCR For RCL, RCR, the bits are rotate through the carry flag 611 37100 微處理機原理與應用 Lecture 05-58 29
5.5 Rotate Instructions What is the result in BX and CF after execution of the following instructions? RCR BX, CL Assume that, prior to execution of the instruction, (CL)=04 16, (BX)=1234 16, and (CF)=0 The original contents of BX are (BX) = 0001001000110100 2 = 1234 16 Execution of the RCR command causes a 4-bit rotate right through carry to take place on the data in BX, the results are (BX) = 1000000100100011 2 = 8123 16 (CF) = 0 2 611 37100 微處理機原理與應用 Lecture 05-59 5.5 Rotate Instructions Verify the previous example using DEBUG program. 611 37100 微處理機原理與應用 Lecture 05-60 30
5.5 Rotate Instructions Disassembly and addition of 2 hexadecimal digits stored as a byte in memory. MOV AL, [HEX_DIGITS] MOV BL, AL MOV CL, 04H ROR BL, CL AND AL, 0FH AND BL, 0FH ADD AL, BL 611 37100 微處理機原理與應用 Lecture 05-61 31