1 2 1 2 3 4 5 6 7 8 9
10 3 1 150 2 150 1 1 1.1 1.1.1 1.2 1.2.1 1.2.2 1.2.3 1.3 1.3.1 1.3.2 1.4 1.4.1 CPU
1.4.2 I/O 1.4.3 I/O 1.5 1.5.1 CISC RISC 1.5.2 1.5.3 1.6 1.6.1 1.6.2 N 1.6.3 2 2.1 2.1.1 2.1.2 2.1.3 2.2 2.2.1
8 16 32 DSP 2.2.2 2.3 2.3.1 2.3.2 MMU 2.3.3 RAM ROM 2.3.4 (Cache) 2.3.5 2.4 I/O 2.4.1 GPIO PWM 2.4.2 A/D D/A 2.4.3 2.4.4
2.4.5 2.5 2.5.1 2.5.2 2.5.3 2.6 PCI PCI-E EISA VME CPCI PCMCIA USB SPI IIC 1394 CAN WLANZigbee WIFI GPRS 3G AFDX FC Select IO Rapid IO 2.7 2.8 2.8.1 2.8.2 PCB PCB PCB PCB PCB 2.8.3
3 3.1 3.1.1 3.1.2 Bootloader BSP 3.1.3 3.1.4 3.1.5 GUI 3.2 3.2.1 3.2.2
3.2.3 Flat 3.2.4 3.2.5 FAT JFFS YAFFS 3.2.6 3.3
3.3.1 3.3.2 / / C/C++ 3.3.3 3.3.4
3.3.5 4 4.1 4.1.1 4.1.2 4.1.3 4.1.4 4.2 4.2.1 4.2.2 4.2.3 4.3 4.3.1 4.3.2 4.3.3 4.3.4
4.4 4.4.1 4.4.2 4.5 4.5.1 4.5.2 4.5.3 5 5.1 5.2
5.3 6 6.1 6.2 6.3 6.4 7 7.1 7.2 8 8.1 8.2 9
2 1 1.1 1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 1.1.6 1.2 1.2.1 1.2.2 1.2.3 1.2.4 1.3 1.3.1 1.3.2 1.3.3 1.3.4 1.3.5 1.4 1.4.1 1.4.2 1.5 1.5.1 1.5.2
1.5.3 1.5.4 1.5.5 1.6 1.7 1.8 2 2.1 2.1.1 2.1.2 (DSP) 2.1.3 2.1.4 DMA 2.1.5 2.1.6 2.1.7 FPGA/CPLD 2.2 VHDL Verilog HDL 2.3 2.4 / 2.4.1 2.4.2 2.4.3 GPIO
USB A/D D/A Rapid IO Select IO 2.5 2.6 2.7 2.7.1 2.7.2 2.7.3 2.8 3 3.1 3.1.1 3.1.2 C 3.1.3 C++ C# Java 3.2 3.2.1 3.2.2 HALBSP 3.2.3
3.2.4 3.3 3.3.1 3.3.2 3.3.3 3.3.4 Linux WinCE VxWorks Android CO 3.4 3.4.1 3.4.2 3.4.3 3.4.4 GUI 3.4.5 4 4.1 4.2 4.2.1 4.2.2 4.2.3 4.2.4 5
1 2 1 2 3 4 5 6 7 8 9
10 3 1 150 2 150 I II III I II III 1 1 1.1 1.1.1 II 1.2 1.2.1 II 1.2.2 I
1.2.3 II 1.3 1.3.1 II 1.3.2 I 1.4 1.4.1 CPU CPU II II II 1.4.2 I/O I 1.4.3 I/O I/O II I/O I I/O DMA II 1.5 1.5.1 CISC RISC I 1.5.2 I 1.5.3 I 1.6 1.6.1 I I
1.6.2 I II II N I 1.6.3 I I I 2 2.1 2.1.1 I 2.1.2 I 2.1.3 CPLD FPGA I FPGA I 2.2 2.2.1 8 II 16 II 32 X86 ARM PowerPC II DSP TI ADI Freescale II II
II II 2.2.2 I I I II II II II 2.3 2.3.1 I 2.3.2 MMU MMU I 2.3.3 RAM ROM RAM SRAM DRAM DDRAM NVRAM I ROM PROM EPROM EEPROM ROM I 2.3.4 (Cache) Cache II Cache II Cache II
2.3.5 I I 2.4 I/O 2.4.1 GPIO PWM I 2.4.2 A/D D/A II 2.4.3 II 2.4.4 I 2.4.5 II 2.5 2.5.1 I 2.5.2 II 2.5.3 II 2.6 II II PCI PCI-E EISA VME CPCI PCMCIA II USB SPI IIC 1394 CAN II WLANZigbee WIFI GPRS 3G AFDX FC II Select IO Rapid IO II 2.7 I 2.8
2.8.1 I I I 2.8.2 PCB PCB I PCB I PCB I PCB I 2.8.3 I I 3 3.1 3.1.1 I I I I 3.1.2 Bootloader II BSP II 3.1.3 I 3.1.4 II 3.1.5
GUI II 3.2 3.2.1 MILS II API I I 3.2.2 I II II II II II II RMS EDF II II
II III II 3.2.3 Flat I II II II II 3.2.4 II II II II 3.2.5 II II II FAT JFFS YAFFS I I
3.2.6 I 3.3 3.3.1 I 3.3.2 II I I / II / II C/C++ II 3.3.3 I II II I 3.3.4 II I I
II II I 3.3.5 II II 4 4.1 4.1.1 I 4.1.2 I I I I 4.1.3 I 4.1.4 I 4.2 4.2.1 I I 4.2.2 I 4.2.3 I
4.3 4.3.1 I 4.3.2 II 4.3.3 II II II II II 4.3.4 I I I I 4.4 4.4.1 II 4.4.2 II 4.5 4.5.1 I 4.5.2 I I II 4.5.3 I
5 5.1 I I I I 5.2 I I 5.3 II I 6 6.1 I 6.2 I 6.3 I 6.4 I 7 7.1 I I I
I 7.2 I I I II 8 8.1 I 8.2 I 9 I 2 1 1.1 1.1.1 III 1.1.2 II 1.1.3 II 1.1.4 II 1.1.5 II 1.1.6 II 1.2 1.2.1 II
1.2.2 II 1.2.3 II 1.2.4 II 1.3 1.3.1 III 1.3.2 III 1.3.3 III 1.3.4 II II PCB I 1.3.5 III III II 1.4 1.4.1 I VxWorks Windows CE Linux CO I 1.4.2 II II II I 1.5
1.5.1 II 1.5.2 III 1.5.3 II 1.5.4 III 1.5.5 II 1.6 I 1.7 1.7.1 I 1.7.2 I 1.7.3 I 1.8 I 2 2.1 2.1.1 III 2.1.2 (DSP) III 2.1.3 III 2.1.4 DMA II 2.1.5 I II 2.1.6 I 2.1.7 I FPGA/CPLD III
2.2 VHDL Verilog HDL II 2.3 ASIC I FPGA I SOC I 2.4 / 2.4.1 I 2.4.2 I I 2.4.3 GPIO I USB I I II A/D D/A III Rapid IO Select IO III II III II II 2.5 I 2.6 I 2.7 2.7.1 II 2.7.2 I
2.7.3 II 2.8 I I 3 3.1 3.1.1 II 3.1.2 C III III C III 3.1.3 C++ C# Java III 3.2 3.2.1 I 3.2.2 HALBSP III 3.2.3 III 3.2.4 I 3.3 3.3.1 III III 3.3.2 MMU II
II 3.3.3 II III II 3.3.4 Linux WinCE VxWorks Android CO I 3.4 3.4.1 II 3.4.2 Ext2 Ext3 II Yaffs jffs Jffs2 II Romfs ramfs cramfs II 3.4.3 SQLite II 3.4.4 GUI II 3.4.5 Socket II WEB II 4 4.1 I 4.2 4.2.1 I 4.2.2 I 4.2.3 I 4.2.4 II
5 III 1 1 1 1 A B C D 2 RISC RISC 2 2 A B C D 3 4 2 3 1 4 1 2 3 0.90 0.70 0.70 0.75 4 3
0.75 3 A 2 0.9 (1 0.7) 0.75 C 2 0.9 (1 (1 0.7) ) 0.75 B 2 0.9 (1 0.7 0.7) 0.75 D 0.9 (0.7 0.7) 4 4 4 A B C D 5 A0-A11 A12-A19 A14 A16 5 5 A AB000H ABFFFH B BB000H BBFFFH C EF000H EFFFFH D FE000H FEFFFH 6 6 6 A
B C D CRC 7 7 7 A B C P V D 8 P V S 2-1 S 8 8 A 0 B 1 C 2 D 3 9 9 9 A B C D 10 MIC 10 10 A B C D 11 11 11 A B C D 12 D/A 12
12 A B C D 13 13 13 A B C D 14 14 14 A IC B C IC D 15. 15 15 A B C D 16 16 16 A
B API C D C 17 17 17 A B C D 18 Watch Dog 18 18 A B C D 19 19 19 A B C D 20 20 20 A B
C D 21 21 21 A 20 B 19 C 17 D 16 22 22 22 A B C D 23 C 23 23 A int B void C Interrupter D reti 24 24 25 24 A B C
D 25 A B C D 25 CMM Capability Maturity Model 2 26 26 A B C D 26 27 27 A B C D 27 28 28 A B C D CIH 28 CA B 29 B B
29 A CA B CA C B D B 29 30 30 A B C D 30 An embedded operating system is the 31 program that manages all the other programs in an embedded device after initial load of programs by a(an) 32. It normally guarantees a certain capability within a specified 33 size and 34 constraint as well as with application programs. It also normally has small foot print including initial boot loader, OS kernel, required device drivers, 35 for the user data and so forth. It has very-likely structure of a normal operating system however mainly differentiated by some factors such as type of pre-installed device, functional limits, taking designed job only. 31 A hardware B business C software D external 32 A driver B application C kernel D boot loader 33 A data B storage C bus D CPU 34 A time B format C controller D packet 35 A JAFFS B format
C file systems D protocol 2 15 1 3 1-1 1-1 1-2
1-2 1 9 1-1 8051 12MHz 10ms 15ms 1s 1 2 8051 3 8051 1-3 1-3 8051 2 6 1-2 1-4 n
1-4 15 1 3 6 FC 2-1 PowerPC7447 DSP FC
PowerPC7447 DSP 32 PowerPC7447 big_endian DSP little_endian 2-1 1 5 1 A/D A/D 10 A/D 5.115V A/D 3FFH A/D A/D A/D 1 A/D mv A/D 1 2 4.092V A/D
3 A/D 2 5 3 5 2 2-1 2-1 A 1 B 4 C 2 D 16 unsigned int msgid = 0x01; // 2 ID typedef struct FCSND_Data_struct { unsigned char A; unsigned int B; unsigned short C; unsigned char D[16]; } FCSND_DATA; FCSND_DATA senddata;..
FillfcData(&sendData); // senddata sendfc((msgid, &senddata, sizeof(fcsnd_data)); // 2 unsigned int msgid = 0x00; // ID typedef struct FCRCV_Data_struct { unsigned char A; unsigned int B; unsigned short C; unsigned char D[16]; } FCRCV_DATA; FCRCV_DATA recvdata;.. recvfc((msgid, &recvdata, sizeof(fcrcv_data)); // 15 1 3 3-1 A15 A1 1 5 8 STB
3-1 2 3 D 3 7 CPU BL 8086 1 5 START MOV DX 1 NEXT1 IN AL DX NEXT2 AND AL 2 JZ 3 MOV DX 4 IN AL DX NEXT3 MOV 5 AL RET 15 1 3
3 1 5 / 2 7 3 3 15 C 1 3 C
5-1 C 1 typedef struct 2: { int A : 16; // 16 3: char B : 8; 4: char C : 8; 5: char D : 8; 6: char E : 8; 7: int F; // 16 16 8: }radartype; 9: typedef struct 10: { unsigned int X; // 16 16 11: unsigned int Y; 12: unsigned int Z; 13: unsigned int U; 14: } datatranstype; 15: radartype myradardata[2]= 16: {{1, 'a', 'b', 'c', 0, 512}, {2, 'x', 'y', 'z', 0, 1024}}; 17: 18 void main(void) 19 { radartype *p; 20 datatranstype *q; 21 p = myradardata; 22 q = (datatranstype *)p; 23: q++; 24 } 5-1 C 1 8 16 big_endian 5-2 myradardata
5-2 myradardata 2 4 5-1 22 n q->x = 1 q->y = 2 q->z = 3 q->u = 4 ++ n q->x = 5 q->y = 6 q->z = 7 q->u = 8 3 3 text data bss bss heap stack 5-1 myradardata p q?