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OFDM FPGA Implementing Baseband Data Processing Section on FPGA of an OFDM-based Communication System 02211070 2006 6 1

OFDM FPGA

1 OFDM 2 VHDL FPGA 3 OFDM 4 5 1 OFDM 2 OFDM

1 2 3 OFDM Shinsuke Hara and Ramjee Prased, MULTICARRIER TECHNIQUES for 4G Mobile COMMUNICATIONS, MA: Artech House, 2003. 2

1 OFDM OFDM DAB HDTV Wireless LAN i.e. IEEE802.11 20 60 OFDM 3G [1] OFDM OFDM OFDM CDMA OFDM OFDM OFDM OFDM [2] 2 SBH OFDM OFDM 1

OFDM OFDM OFDM OFDM FFT 1 OFDM OFDM 1 OFDM 2 2.1 FFT FFT DSP FPGA [3] FFT FPGA FFT VHDL IP ALTERA FFT IP FFT ALTERA IP 2

FFT VHDL FFT 8 FFT 2.2 OFDM OFDM FFT 2.3 QuartusII OFDM Modem OFDM D/A D/ A OFDM A/D 2.4 PCB PCB PCB PCB 2.5 Windows [4] 3

1 SBH OFDM MULTICARRIER TECHNIQUES for 4G Mobile COMMUNICATIONS FFT ALTERA IP Core Core IFFT+FFT ALTERA 2 ALTERA FPGA Cyclone FPGA Quartus II ALTERA Quartus II 5.1sp1 [5] IP Core ALTERA ALTERA IP Core License [5] ALTERA IP MATLAB MATLAB OFDM 4

OFDM OFDM OFDM [6] OFDM 1 OFDM 1.1 OFDM FFT VHDL Quartus II 1.2 A/D D/A A/D D/A 1.3 PCB 1.4 2 2.1 OFDM 2.2 OFDM 2.3 OFDM 2.4 MATLAB MATLAB OFDM 2.5 5

[1] Shinsuke Hara and Ramjee Prased, MULTICARRIER TECHNIQUES for 4G Mobile COMMUNICATIONS, MA: Artech House, 2003. [2] http://www.ee.ccu.edu.tw/~wl/ofdm/ofdmopendata.htm [3] DSP 2003 [4] Visual C++/Turbo C 2004 [5] www.altera.com [6] OFDM 2003 1 OFDM FFT A/D D/A A/D D/A PCB 2 OFDM A/D D/A 3 OFDM A/D D/A 6

OFDM FFT A/D D/A A/D D/A PCB 7

OFDM FPGA

OFDM Orthogonal Frequency Division Multiplexing IEEE 802.11a WLAN FPGA OFDM Reed-Solomon FFT OFDM IEEE 802.11a Simulink OFDM ALTERA IP Core OFDM, FPGA, ALTERA I

Abstract Because of wireless environment where multipath maybe significant, Orthogonal Frequency Division Multiplexing (OFDM), a special form of multicarrier modulation (MCM), where a single data stream is transmitted over a number of lower rate subcarriers has recently received considerable attention for its robustness to multipath selective fading and high bandwidth efficiency. It can be seen as either a modulation technique or a multiplexing technique. The main work of my graduate design is to implement baseband data processing section on FPGA of an OFDM-based communication system. It contains Reed-Solomon channel coding (FEC), interleaver, constellation, FFT and Prefix Cyclic parts. In addition, I also pay much attention to other aspects during the design. That is, the study of OFDM, IEEE 802.11a Standard, a demo model of OFDM based on Simulink, devices and IP Megacore of ALTERA corp., which are detailed in my paper. Key words: OFDM, FPGA, ALTERA II

.. I...II.1 OFDM.4 1.1. 4 1.2 OFDM.6 1.2.1 6 1.2.2 6 1.2.3...7 1.2.4..8 1.2.5 OFDM..9 1.3 OFDM. 10 1.3.1 FFT OFDM. 10 1.3.2 OFDM....10 1.4 OFDM.. 11 1.4.1 OFDM...11 1.4.2..11 1.4.3 FFT 12 1.4.4.13 1.4.5 OFDM..13 1.5.15...15 III

802.11a.17 2.1 802.11a...17 2.1.1 WLAN 802.11...17 2.1.2 IEEE 802.11.18 2.2 802.11a..18 2.2.1 802.11a.19 2.2.2 PLCP PPDU 20 2.2.3 Preamble.20 2.2.4 G OFDM. 21 2.3 Simulink 802.11a Demo..21 2.3.1 Demo.21 2.3.2 22 2.3.3. 24 2.4..25 26 FPGA ALTERA..27 3.1 FPGA 27 3.1.1.. 27 3.1.2 FPGA. 28 3.1.3 FPGA DSP.. 28 3.1.4 FPGA ASIC. 30 3.1.5 FPGA.. 30 3.2 ALTERA. 31 3.2.1.. 31 IV

3.2.2 32 3.2.3 OpenCore plus 32 3.2.4 33 3.2.5 33 3.3 ALTERA 34 3.4.. 35..35 ALTERA FFT MegaCore 36 4.1 FFT MegaCore 36 4.2 FFT MegaCore 37 4.2.1.. 37 4.2.2 FFT MegaCore. 37 4.2.3 IP Toolbench 38 4.2.4 39 4.2.5 FFT MegaCore. 39 4.2.6 FFT MegaCore.40 4.2.7..40 4.2.8 OpenCore plus. 41 4.2.9 license.41 4.3. 42 4.3.1. 42 4.3.2 FFT Transform Length 43 4.3.3 43 4.3.4 I/O Data Flow 44 V

4.3.5 FFT Engine Architecture.. 45 4.3.6 46 4.3.7 RAM 46 4.4 FFT MegaCore 47 4.5 FFT. 48 4.6 FFT MegaCore MATLAB. 49 4.7.. 52 52 OFDM...53 5.1. 53 5.1.1 IP. 53 5.1.2 54 5.1.3 HDL 55 5.2.. 56 5.2.1.. 56 5.2.2.. 58 5.3. 59 5.3.1 59 5.3.2..60 5.3.3 R-S.. 61 5.3.4 R-S encoder.. 62 5.3.5 62 5.3.6.. 63 5.3.7 64 VI

5.3.8 IFFT FFT 65 5.3.9 65 5.3.10. 65 5.3.11 VHDL 66 5.4 66 5.4.1. 66 5.4.2 67 5.4.3 FPGA.. 67 5.5 68 68 VHDL..70.79 VII

OFDM OFDM OFDM OFDM FPGA OFDM 1

OFDM OFDM OFDM OFDM FPGA OFDM IEEE 802.11a WLAN OFDM 802.11a OFDM 802.11a FPGA OFDM DSP FPGA FPGA ALTERA FPGA ALTERA ALTERA FFT MegaCore IP OFDM FFT IP ALTERA Dylan IP Dylan 2

VHDL http://www.olivercamel.com OFDM 2007 OFDM 1 OFDM 2 IEEE 802.11a Simulink 3 ALTERA IP 4 VHDL OFDM 5 2006 6 3

OFDM OFDM OFDM OFDM 1.1 4

ISP 0 1 ADSL 56Kbps 5

1.2 OFDM 1.2.1 [1,2] 1.2.2 [3] 1.1 6

ISI 1.2 1.2.3 100 1/100 OFDM 7

[4] 1.2.4 FDM 1.3 OFDM 8

1.4 OFDM FDM FDM OFDM 1.2.5 OFDM OFDM OFDM, Orthogonal Frequency Division Multiplexing OFDM OFDM OFDM OFDM OFDM 9

1.3 OFDM 1.3.1 FFT OFDM OFDM OFDM OFDM FFT DSP FPGA OFDM OFDM DFT FFT DFT OFDM FFT OFDM [5] 1.3.2 OFDM 1990 OFDM DAB DVB-T DSL HDTV HIPERLAN IEEE 802.11 802.16 OFDM 802.11a OFDM OFDM Muticarrier techniques for 4G Mobile Communications OFDM [1] OFDM 10

OFDM [6] OFDM 1.4 OFDM 1.4.1 OFDM OFDM OFDM 1.5 OFDM FFT OFDM FFT 1.4.2 FFT BPSK QPSK QAM QPSK 11

1.6 OFDM 00-1+1i FFT 1.4.3 FFT IFFT FFT FFT 64 FFT 64 64 FFT 64 64 FFT 64 12

64 FFT OFDM 1.4.4 OFDM OFDM n n ISI OFDM FDM OFDM OFDM 1.7 1.4.5 OFDM OFDM OFDM OFDM 13

OFDM OFDM 1.8 OFDM D/A OFDM y=f(x) x f y OFDM OFDM OFDM FFT OFDM OFDM OFDM OFDM OFDM 14

1.5 OFDM OFDM OFDM OFDM OFDM [1] Shinsuke Hara and Ramjee Prased, MULTICARRIER TECHNIQUES for 4G Mobile COMMUNICATIONS, MA: Artech House, 2003. [2] Gordon L. Stüber, Principles of Mobile Communication, Second Edition,,,,, 2004. [3] Web ProForum Tutorials, OFDM for Mobile Data Communications, The International Engineering Consortium, http://www.iec.org. [4] John G. Proakis, Masoud Salehi, Gerhard Bauch, Contemporary Communication Systems Using MATLAB and Simulink, Second Edition,,, 2005. 15

[5] OFDM 2003 11 [6] Steven J. Vaughan-Nichols, OFDM: Old Technology for New Markets, Tutorial of Wi-Fi Planet, http://www.wi-fiplanet.com, November 14, 2002. 16

802.11a IEEE WLAN 802.11 802.11a OFDM 802.11a OFDM Mathworks Simulink 802.11a Demo 2.1 802.11a 2.1.1 WLAN 802.11 IEEE 802.11 802.16 802.11 WLAN Internet WLAN WLAN WLAN 802.11 802.11a 802.11b 802.11g 802.11a OFDM 802.11 1997 1M 17

2Mbps 1999 802.11a 5GHz 54Mbps WLAN 54Mbps 2.1.2 IEEE 802.11 IEEE http://www.ieee.org[1] IEEE Get IEEE 802 [1] 802 pdf sponsor Get IEEE 802 802 WLAN Get IEEE 802 802.11a 802.11a-1999.pdf[2] 802.11 802.11 [3] 2.2 802.11a 802.11 802.11a WLAN 802.11a 802.11 18

2.2.1 802.11a 802.11a PMD Physical medium dependent PLCP Physical layer convergence procedure PLME PHY layer Management Entity 2.1 802.11 OSI [3] PMD WLAN OFDM PLCP PLCP OFDM OFDM PPDU PLCP protocol Data Unit MAC PLME 19

2.2.2 PLCP PPDU 802.11a PLCP PPDU PPDU PPDU 2.2 PPDU [2] PSDU Physical sublayer Service Data Unit PMD PLCP Header Tail Pad Bits 12 PLCP Preamble PPDU PPDU 802.11a a n 14 17.3.2.1 [2] 2.2.3 Preamble 2.3 PPDU [2] PPDU 12 Preamble 20

2.3 2.2.4 G OFDM 802.11a 802.11a (annex) Annex G OFDM OFDM Annex G OFDM 1.4.5 OFDM 2.3 Simulink 802.11a Demo 2.3.1 Demo MATLAB Simulink Simulink OFDM MATLAB7.0 Commuication Blockset 21

OFDM Demo DVB ADSL HIPERLAN/2 802.11a WLAN 2.4 MATLAB Mathworks [4] 802.11a 2.3.2 MAC/PHY PLCP header Data Scrambler OFDM [5] Simulink 802.11a 22

OFDM 2.5 802.11a Simulink Demo Simulink OFDM 2.6 Simulink 23

2.7 2.3.3 54Mbps 64QAM QPSK 802.11a 24

2.8 2.4 OFDM IEEE 802.11a WLAN Simulink OFDM OFDM OFDM 802.11 OFDM OFDM 25

802.11a 802.11a Simulink 802.11a Simulink OFDM [1] http://www.ieee.org [2] IEEE Std. 802.11a 1999 Edition (R2003), Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications: High-speed Physical Layer Extension in the 5-GHz Band, IEEE, 2003. [3] IEEE Std. 802.11 1999 Edition (R2003), Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications, IEEE, 2003. [4] http://www.mathworks.com [5] Demonstration Models, IEEE 802.11a WLAN Physical Layer, Communication Blockset, The Mathsworks, Inc. 26

FPGA ALTERA OFDM FPGA OFDM FPGA FPGA FPGA OFDM ALTERA Xilinx FPGA ALTERA ALTERA 3.1 FPGA 3.1.1 PLD PLD PLD PLD VHDL Verilog HDL HDL PLD CPLD FPGA PLD PLD CPLD FPGA 27

OFDM ALTERA FPGA FPGA PLD 3.1.2 FPGA FPGA LE LE LE FPGA LE nm LE ALTERA Stratix GX LE 4 [1] LE FPGA HDL LE FPGA FPGA Stratix GX 300MHz 6Gbps [1] 3.1.3 FPGA DSP FPGA FPGA DSP DSP 28

FPGA DSP OFDM FFT 8 FFT 3.1 2 8 FFT [2] DSP FFT FPGA DSP FFT 1024 DSP [3] FPGA FPGA ALTERA NIOS FPGA DSP FPGA DSP NIOS 32 ALTERA FPGA 29

SOPC PLD ALTERA C HDL C ALTERA [4] 3.1.4 FPGA ASIC ASIC ASIC ASIC FPGA ALTERA HardCopy FPGA HardCopy FPGA ASIC FPGA ASIC ASIC ASIC FPGA ASIC ASIC FPGA HardCopy FPGA 3.1.5 FPGA FPGA FPGA FPGA DSP 30

NIOS CPU ARM FPGA FPGA FPGA LE FPGA FPGA PLL RAM FPGA 3.2 ALTERA ALTERA OFDM 3.2.1 FPGA VHDL ALTERA Verilog Xilinx ALTERA ALTERA ALTERA 31

ALTERA ALTERA 3.2.2 ALTERA ALTERA ALTERA FPGA Maxplus Quartus license HDL FPGA ALTERA ALTERA ALTERA FPGA 3.2.3 OpenCore plus IP Intellectual Property ALTERA IP OpenCore plus IP 32

OpenCore plus IP ALTERA IP RTL IP OpenCore plus IP FPGA OpenCore plus JTAG IP ALTERA IP ALTERA 3.2.4 ALTERA ALTERA MySupport ALTERA ALTERA MySupport 3.2.5 ALTERA 33

3.3 ALTERA ALTERA FPGA ALTERA Stratix Cyclone FPGA CPLD MAX II CPLD FPGA Flash FPGA [5] MAX II FPGA Quartus II 6.0 Quartus Quartus ModelSim OEM ModelSim ALTERA Quartus SignalTap Quartus II 6.0 TimeQuest FPGA DSP Builder ALTERA DSP Simulink Blockset MATLAB Simulink DSP Builder HDL ALTERA IP FPGA HardCopy NIOS SOPC ALTERA 34

3.4 FPGA FPGA OFDM ALTERA OFDM ALTERA FFT MegaCore [1] Data Sheet, Stratix GX FPGA Family, version 2.2, ALTERA corp., 2002. [2] 2004 [3] DSP 2003 [4] http://www.altera.com [5] Handbook, MAX II Device Handbook, preliminary, ALTERA corp. 35

ALTERA FFT MegaCore DFT FFT DFT FPGA IP Intellectual Property FFT FFT IP ALTERA FFT MegaCore IP ALTERA FFT MegaCore User Guide[1] FFT MegaCore 4.1 FFT MegaCore ALTERA IP MegaCore FFT MegaCore FFT/IFFT IP FFT MegaCore ALTERA FPGA Cyclone Stratix HardCopy ALTERA IP FPGA FFT ALTERA IP FPGA ALTERA FFT MegaCore 300M FFT MegaCore 8000 36

4.2 FFT MegaCore FFT MegaCore Quartus FFT 4.2.1 FFT MegaCore ALTERA DSP IP v2.2.0 4.2.2 FFT MegaCore FFT MegaCore FFT MegaCore IP Toolbench FFT MegaCore Tool MegaWizard Plug-In Manager 4.1 MegaWizard Plug-In Manager Megafunction IP 37

FFT FPGA IP Cyclone VHDL FFTcore 4.2 FFT MegaCore IP Toolbench 4.2.3 IP Toolbench IP Toolbench 38

4.3 IP Toolbench 4.2.4 Transform Length 64 64 FFT 4.2.5 FFT MegaCore Set up simulation Generation IP 39

IP Toolbench IP IP 4.2.6 FFT MegaCore FFT MegaCore (bdf) FFT IP Project HDL VHDL.cmp FFT component FFT FFT input output 4.4 bdf FFT 4.2.7 P4 1.4G 256M 15 40

4.5 FFT MegaCore MATLAB 4.2.8 OpenCore plus IP IP ALTERA OpenCore plus JTAG IP IP 4.2.9 license ALTERA IP IP ALTERA license 41

FFT MegaCore 4.3 FFT MegaCore 4.3.1 Parameters Architecture Implementation Options 1024 FFT 64 FFT 1000 LE RAM FFT 4.6 FFT FFT FPGA FFT FFT 42

4.3.2 FFT Transform Length FFT 64 16384 ALTERA FFT MegaCore FFT FFT 2 64 FFT 4 2 128 4 4 2 ALTERA 4 FFT 4.3.3 FFT 16bits 16bits ALTERA FFT MegaCore FPGA FFT FFT FFT FFT MegaCore FFT IFFT 43

16bits FFT+IFFT 8bits FFT+IFFT ALTERA Data Precision Twiddle Precision precision width 4.3.4 I/O Data Flow Architecture I/O Data Flow Engine Option FFT MegaCore I/O Data Flow Streaming Buffer Burst Burst FFT FFT FFT FFT RAM FFT FFT FFT RAM I/O Data Flow Streaming Buffer Burst Burst Streaming RAM Buffer Burst Burst RAM 44

Burst Buffer Burst RAM RAM Burst RAM 4.3.5 FFT Engine Architecture FFT FFT Engine Quad Single 4.7 Quad Output[1] 45

4.8 Single Output[1] Quad Output Single Output FFT 4.3.6 Implementation Option / / FFT MegaCore v2.2.0 [2] Cyclone II FPGA / DSP Block LE 4.3.7 RAM RAM ALTERA FPGA M-RAM M4K M512 RAM 46

RAM LE 4.4 FFT MegaCore FFT FFT Core clk reset FFT MegaCore 4.5 ALTERA Atlantic [3] Master_sink_dav Master_sink_dav 1 IP Master_sink_dav 1 Master_sink_sop 64 FFT 64 master_sink_sop 1 Inv_I FFT IFFT 0 1 FFT IFFT master_sink_sop FFT FFT IFFT Master_source_ena master_source_sop master_source_eop master_source_sop 47

master_source_eop master_source_ena 1 Master_sink_ena FFT master_sink_ena 1 0 0 Master_source_dav 1 FFT 0 Streaming IFFT inv_i master_sink_dav master_source_dav 1 master_sink_ena 1 master_sink_sop FFT 4.5 FFT FFT MegaCore FFT FFT MegaCore FFT FFT 110 90 65 7 110 11 10 9 6 0 10 FFT MegaCore 48

FFT MegaCore ALTERA [4] 4.9 [4] IFFT N N 1/N 4.6 FFT MegaCore MATLAB FFT MegaCore Quartus 49

MATLAB IP Core FPGA name_model.m MATLAB name FFT.m MATLAB % function[y, exp_out] = name_model(x,n,inverse) x N FFT INVERSE 1 IFFT 0 FFT y exp_out X y exp_out MATLAB FFT MATLAB test.m % FFT MegaCore clc; clear; % 64 1 100 a,b a = rand(1, 64); a = a * 100; a = int8(a); % b = rand(1, 64); b = b * 100; 50

b = int8(b); % % x = double(complex(a,b)); % FFT+IFFT [y, exp1] = name_model(x, 64, 0); [z, exp2] = name_model(y, 64, 1); % exp1 = exp1(1,1); exp2 = exp2(1,1); exp = 2.^(abs(exp1+exp2)-6); z = z * exp; % result = [x; z] MATLAB FFT+IFFT 16bits FFT IFFT OFDM IFFT+FFT 51

4.7 ALTERA FFT MegaCore FFT OFDM FFT MegaCore OFDM [1] User Guide, FFT MegaCore Function User Guide, ALTERA corp., 2005. [2] Errata Sheet, FFT MegaCore Function, ALTERA corp., 2006. [3] Functional Specification 13, Atlantic Interface, v3.0, ALTERA corp., 2002. [4] Application Note 404, FFT/IFFT Block Floating Point Scaling, v1.0, ALTERA corp., 2005. 52

OFDM OFDM FPGA VHDL 18 FFT OFDM 802.11a OFDM OFDM OFDM 5.1 FPGA 5.1.1 IP FPGA IP IP Intellectual Property IP 53

IP IP OFDM IP Reed-Solomen FFT/IFFT ALTERA MegaCore IP IP FFT IP FFT HDL FFT IP ALTERA ALTERA MegaCore FFT/IFFT $7995 R-S encoder $1995 R-S decoder $7995 Serial Low-speed Viterbi Decoder $9995 FIR compiler $2995 NCO compiler $2495 IP IP IP IP IP 5.1.2 FPGA FPGA 9000 LE 54

8000 LE FPGA 10000 LE A 9000 LE 1000 LE B 8500 LE 500 LE 20000 LE 500 LE ALTERA FPGA 1000 3000 5000 8000 10000 LE 9000 LE FPGA 8500 LE FPGA HDL 100 LE LE 5.1.3 HDL FPGA HDL HDL 55

5.1 5.2 OFDM FFT OFDM 5.2.1 56

5.2 VHDL IP NCO FIR IP FEC R-S Viterbi DVB 802.11a Turbo R-S Viterbi ALTERA MegaCore I Q DAC 57

IP IP ALTERA [1] 5.2.2 5.3 802.11a FEC Viterbi MegaCore R-S 58

5.3 5.3.1 ALTERA IP Atlantic [2] Atlantic Interface master slave sink source source_ena sink_ena Source_ena 1 0 Sink_ena 1 0 source_ena 59

5.4 sink_ena sink_ena source_ena sink_sop sink_eop sink_val source_sop source_eop source_val sop eop val 5.3.2 OFDM OFDM FIFO FIFO 60

FIFO 64 64 80 16 64 5.3.3 R-S Reed-Solomon R-S R-S d t L = d+t t t/2 2 4 6 6 61

[3] OFDM R-S ALTERA MegaCore 6 word word 4 bit 6 word 2 4 5.5 R-S [3] OFDM R-S MegaCore 5.3.4 R-S encoder R-S encoder 36 word 5.3.5 R-S RAM RAM 62

(symbol)6 word word 4bit RAM 36*4bit RAM s1w1 s1w2 s1w3 s1w4 s1w5 s1w6 s2w1 s2w2 s6w5 s6w6 s1w1 s2w1 s3w1 s4w1 s5w1 s6w1 s1w2 s2w2 s5w6 s6w6 5.6 [4] 6*6 5.3.6 36 words 64 IFFT 28 0 64 OFDM 63

5.3.7 OFDM FFT OFDM QPSK 8PSK 16QAM 64QAM 16QAM 16 QPSK 8PSK 64QAM word 4 bit 16 16 96 32-33 -97 16QAM 5.7 16QAM 0001-33+96i 64

4bit 10bit 10bit FFT 4bit 10bit 5.3.8 IFFT FFT FFT OFDM FFT 5.3.9 OFDM 64 FFT 64 16 64 16 64 16 FFT 5.3.10 FFT Scaler FFT+IFFT 8 Zero Remover R-S 28 FIFO 65

5.3.11 VHDL VHDL VHDL http://www.olivercamel.com olivercamel@gmail.com 5.4 5.4.1 VHDL Quartus 9000 LE 15000 bits RAM 66

5.8 5.4.2 ALTERA 5.9 5.4.3 FPGA FPGA FPGA 67

EP1C12Q240C8 16M 4bits 5.5 OFDM Viterbi A/D D/A FIR [1] White Paper, Implementing OFDM Using Altera Intellectual Property, v1.0, ALTERA corp., 2001. [2] Functional Specification 13, Atlantic Interface, v3.0, ALTERA corp., 2002. [3] User Guide, Reed-Solomon Complier User Guide, v4.0.1, ALTERA corp., 2005. 68

[4] User Guide, Symbol Interleaver/Deinterleaver MegaCore Function User Guide, v1.3, ALTERA corp., 2002. 69

VHDL http://www.olivercamel.com -- ================================================================ -- File: Interleaver.vhd -- Version: v1.1 -- Author: olivercamel -- Date: 4.16.2006 -- Description: -- This vhdl programme is to generate a Interleaver which works together with R-S -- encoder/decoder to mitigate the effects of noise in communications system. -- Actually, interleaver is a simple RAM controller that writes datas into or reads -- datas outside following specific orders. For example, symbols we used in this -- project are comprised by 6 words. Throughput of the interleaver is 6 symbols. -- And then, the input sequence is s1w1,s1w2,s1w3,s1w4,s1w5,s1w6,s2w1,s2w2,..., -- s6w5,s6w6. The output sequence is s1w1,s2w1,s3w1,s4w1,s5w1,s6w1,s1w2,s2w2,..., -- s5w6,w6w6. A 4bit * 64words RAM named ram_interleaver is required in the codes. -- Revision History: -- v1.1, 4.27.2006, deassert sink_ena earlier to avoid a control bug. -- ================================================================ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; -- ================================================================ entity Interleaver is port ( -- clock input clk: in std_logic; -- asynchroism clear input aclr: in std_logic; -- 4bit width Data ports inputdata: in std_logic_vector (3 downto 0); outputdata: out std_logic_vector (3 downto 0); -- simple ALTERA Atlantic interface ports 70

sink_val: in std_logic; sink_sop: in std_logic; sink_eop: in std_logic; sink_ena: out std_logic; source_val: out std_logic; source_sop: out std_logic; source_eop: out std_logic; source_ena: in std_logic ); end Interleaver; -- ================================================================ architecture structure of Interleaver is -- -------------------------------------------------------------------------------- -- component declaration -- generate by ALTERA ip toolbench -- name: ram_interleaver -- size: 4bit * 64words component ram_interleaver PORT ( aclr: IN STD_LOGIC; clock: IN STD_LOGIC; data: IN STD_LOGIC_VECTOR (3 DOWNTO 0); rdaddress: IN STD_LOGIC_VECTOR (5 DOWNTO 0); rden: IN STD_LOGIC; wraddress: IN STD_LOGIC_VECTOR (5 DOWNTO 0); wren: IN STD_LOGIC; q: OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ); end component; -- signals those connect to RAM signal clk_ram: std_logic; signal aclr_ram: std_logic; signal inputdata_ram: std_logic_vector (3 downto 0); signal outputdata_ram: std_logic_vector (3 downto 0); signal readenable_ram: std_logic; 71

signal writeenable_ram: std_logic; signal readaddress_ram: std_logic_vector (5 downto 0); signal writeaddress_ram: std_logic_vector (5 downto 0); -- signals those used to Atlantic interface outputs signal interval_source_val: std_logic; signal interval_source_sop: std_logic; signal interval_source_eop: std_logic; signal interval_sink_ena: std_logic; -- flag signal indicates status: '1' input process, '0' output process` signal inoutflag: std_logic; -- write address signal wraddnum: integer range 0 to 36; -- read address signal rdaddnum: integer range 0 to 36; -- write enable signal writeenable: std_logic; -- read enable signal readenable: std_logic; -- delayd signals -- sink_eop delay signal sink_eop_d: std_logic; -- readenable delay signal readenable_d0: std_logic; signal readenable_d1: std_logic; -- interval_source sop and eop delay or acceleration signal interval_source_sop_d0: std_logic; signal interval_source_sop_d1: std_logic; signal interval_source_eop_a: std_logic; signal interval_source_eop_d0: std_logic; signal interval_source_eop_d1: std_logic; -- -------------------------------------------------------------------------------- begin -- -------------------------------------------------------------------------------- 72

-- part1: ram connections -- ram ports map u1: ram_interleaver port map ( clock => clk_ram, aclr => aclr_ram, data => inputdata_ram, q => outputdata_ram, rdaddress => readaddress_ram, wraddress => writeaddress_ram, rden => readenable_ram, wren => writeenable_ram ); -- integer converts to std_logic_vector readaddress_ram <= conv_std_logic_vector(rdaddnum,6); writeaddress_ram <= conv_std_logic_vector(wraddnum,6); -- readenable delay process(clk,readenable) begin if falling_edge(clk) then readenable_d0 <= readenable; readenable_d1 <= readenable_d0; end if; end process; writeenable_ram <= writeenable; readenable_ram <= readenable_d0; clk_ram <= clk; aclr_ram <= aclr; inputdata_ram <= inputdata; -- outputs data at clk's falling edge process(aclr,clk,outputdata_ram) begin if aclr = '1' then outputdata <= "0000"; else if falling_edge(clk) then -- using falling edge outputdata <= outputdata_ram; end if; end if; 73

end process; -- -------------------------------------------------------------------------------- -- part2: generate Flag signal inoutflag -- delay input signal sink_eop process(clk,sink_eop) begin if rising_edge(clk) then sink_eop_d <= sink_eop; end if; end process; -- control inoutflag process(clk,aclr,sink_eop_d,interval_source_eop_a) begin if aclr = '1' then inoutflag <= '1'; else if rising_edge(clk) then if inoutflag = '1' then if sink_eop_d = '1' then inoutflag <= '0'; end if; else if interval_source_eop_a = '1' then inoutflag <= '1'; end if; end if; end if; end if; end process; -- -------------------------------------------------------------------------------- -- part3: generate read/write Enable/Address -- generate writeenable process(aclr,inoutflag,sink_val) begin if aclr = '1' then 74

writeenable <= '0'; else if inoutflag = '1' then writeenable <= sink_val; else writeenable <= '0'; end if; end if; end process; -- generate readenable process(clk,aclr,inoutflag,source_ena) begin if aclr = '1' then readenable <= '0'; else if falling_edge(clk) then -- using falling edge if (inoutflag = '0') and (source_ena = '1') then readenable <= '1'; else readenable <= '0'; end if; end if; end if; end process; -- write address process(clk,aclr,writeenable,sink_sop,sink_eop) begin if aclr = '1' then wraddnum <= 1; else if falling_edge(clk) then -- using falling edge if writeenable = '1' then if wraddnum = 36 then wraddnum <= 1; else wraddnum <= wraddnum + 1; end if; end if; if sink_sop = '1' then 75

wraddnum <= 2; elsif sink_eop = '1' then wraddnum <= 1; end if; end if; end if; end process; -- read address process(clk,aclr,source_ena,interval_sink_ena) begin if aclr = '1' then rdaddnum <= 0; else if falling_edge(clk) then -- using falling edge if readenable = '1' then if rdaddnum = 0 then rdaddnum <= 1; elsif rdaddnum = 31 then rdaddnum <= 2; elsif rdaddnum = 32 then rdaddnum <= 3; elsif rdaddnum = 33 then rdaddnum <= 4; elsif rdaddnum = 34 then rdaddnum <= 5; elsif rdaddnum = 35 then rdaddnum <= 6; else rdaddnum <= rdaddnum + 6; end if; end if; if rdaddnum = 36 then rdaddnum <= 0; end if; end if; end if; end process; -- -------------------------------------------------------------------------------- -- part4: Atlantic interface signals 76

-- source sop eop is controlled by rdaddnum -- generate interval_source_eop_a at the same time process(rdaddnum) begin case rdaddnum is when 36 => interval_source_eop <= '1'; interval_source_sop <= '0'; interval_source_eop_a <= '0'; when 1 => interval_source_sop <= '1'; interval_source_eop <= '0'; interval_source_eop_a <= '0'; when 30 => interval_source_sop <= '0'; interval_source_eop <= '0'; interval_source_eop_a <= '1'; when others => interval_source_sop <= '0'; interval_source_eop <= '0'; interval_source_eop_a <= '0'; end case; end process; -- source_sop source_eop delay and output process(clk,interval_source_sop) begin if rising_edge(clk) then interval_source_sop_d0 <= interval_source_sop; interval_source_sop_d1 <= interval_source_sop_d0; end if; end process; process(clk,interval_source_eop) begin if rising_edge(clk) then interval_source_eop_d0 <= interval_source_eop; interval_source_eop_d1 <= interval_source_eop_d0; end if; end process; 77

process(clk,interval_source_sop_d1,interval_source_eop_d1) begin if falling_edge(clk) then -- using falling edge source_sop <= interval_source_sop_d1; source_eop <= interval_source_eop_d1; end if; end process; -- generate sink_ena process(clk,aclr,wraddnum,rdaddnum) begin if aclr = '1' then interval_sink_ena <= '1'; else if rising_edge(clk) then if wraddnum = 35 then -- edited in v1.1 deassert sink_ena earlier interval_sink_ena <= '0'; elsif rdaddnum = 36 then interval_sink_ena <= '1'; end if; end if; end if; end process; sink_ena <= interval_sink_ena; -- generate source_val process(clk,readenable_d1) begin if falling_edge(clk) then -- using falling edge interval_source_val <= readenable_d1; end if; end process; source_val <= interval_source_val; -- -------------------------------------------------------------------------------- end structure; -- ================================================================ 78

iteartively error-control code timing recovery iterative timing recovery 82

ISI [1] deep-space 1/31 15dB Georghiades Snyder EM [2] ISI [1], [3] - [5] [1], [6] - [8] 83

a Turbo Turbo b b [10] Turbo c Turbo d soft-output BCJR[11] Baum-Welch [12] 1/T 84

r(t) k T n(t) k {kt+ } = - 85

α β 2 β 2 k - = + - α<1 α β 86