D/A DAC0832 8 ( 1us) (10~20 ) DAC0832 1
1. 20 DI7~DI0 ILE 8 8 DAC 8 D/A LE LE & RFB VREF IOUT2 IOUT1 RFB CS WR1 XFER WR2 & & AGND VCC DGND 2
DI7~DI0 ILE & 8 LE 8 DAC LE 8 D/A RFB V REF IOUT2 IOUT1 R FB CS WR1 & AGND XFER WR2 & VCC DGND V cc V REF R FB AGND DGND, +5V+15V, -10V+10V, 3
DI7~DI0 ILE & 8 LE 8 DAC LE 8 D/A RFB V REF IOUT2 IOUT1 R FB CS WR1 & AGND XFER WR2 & VCC DGND DI 7 ~ DI 0 : DI 0 DI 7 4
DI 7 ~DI 0 ILE CS WR1 XFER WR2 1 0 0 & 8 LE ILE CS WR1 & & 1 8 DAC LE 8 D/A RFB V REF IOUT2 IOUT1 RFB AGND VCC DGND,, 1 ILECSWR1, LE=1 LE1 WR1, LE=0 5
DI 7 ~DI 0 ILE & 8 LE 8 DAC LE 8 D/A RFB VREF IOUT2 IOUT1 RFB CS WR1 XFER WR2 0 0 & & 1 AGND VCC DGND XFER WR2 2 XFERWR2, LE2=1 LE2 DAC WR1, LE=0 DAC 6
DI 7 ~DI 0 ILE & 8 LE 8 DAC LE 8 D/A RFB V REF IOUT2 IOUT1 RFB CS WR 1 XFER WR 2 & & AGND VCC DGND IOUT1 IOUT2 1 255V 1, REF 256RFB 0, 0 2 IOUT1 + I OUT2 = 7
2. DAC0832 1) 2) 8
1) : D/A D/A 9
PC DAC0832 D0 DI 0 ~ ~ D7 DI 7 +5V IOW A0 ~ A9 port ILE WR1 CS RFB IOUT1 IOUT2 XFER WR2 - + Vo : DAC 10
D 7 ~D 0 +5V IOW A 9 ~A 0 C port CLK MOV AL, data ; MOV DX, port OUT DX, AL DI 7 ~DI 0 ILE WR1 CS & XFER WR2 LE & DAC LE A 15 ~A 0 D 7 ~D 0 IOW I OUT2 D/A RFB I OUT1 T 1 T 2 T 3 Tw port + Vo - T 4 PC I/O 11
PC DAC0832 D 0 DI RFB 0 ~ ~ D 7 DI IOUT1-7 +5V ILE + IOW A 0 ~ A 9 port WR2 XFER IOUT2 CS WR1 Vo : DAC 12
C D 7 ~D 0 DI 7 ~DI 0 DAC I OUT2 D/A + V o +5V port ILE WR1 CS & LE LE RFB I OUT1 - A 9 ~A 0 IOW XFER WR2 & CLK MOV AL, data ; MOV DX, port OUT DX, AL A 15 ~A 0 D 7 ~D 0 IOW T 1 T 2 T 3 Tw port T 4 PC I/O 13
2) : PC DAC0832 D 0 DI 0 ~ ~ D 7 DI 7 +5V ILE + IOW A 0 ~ A 9 port1 port2 WR1 WR2 CS XFER RFB I OUT1 I OUT2 - V REF -5V DGND AGND V o 14
C D 7 ~D 0 +5V A 9 ~A 0 IOW port1 port2 DI 7 ~DI 0 ILE WR1 CS & XFER WR2 LE & DAC LE I OUT2 D/A RFB I OUT1 + - V o MOV AL, data ; MOV DXport1 OUT DX, AL ; MOV DX, port2 OUT DX, AL ; 15
PC DAC0832 D 7 ~ D 0 DI 7 ~DI 0 +5v ILE CS WR1 XFER D/A WR2 + Vo1 A 9 ~ A 0 IOW port1 port2 port3 DI 7 ~DI 0 +5v ILE CS DAC0832 WR1 XFER D/A WR2 16 + V o2
datav1datav2 code SEGMENT ASSUME CS: code, DS:code datav1 DB 11h, 12h, 13h, 14h, 15h, 16h, 17h, 18h, 19h, 1Ah datav2 DB 21h, 22h, 23h, 24h, 25h, 26h, 27h, 28h, 29h, 2Ah start: MOV AX, code MOV DS, AX LEA SI, data_v1 LEA BX, data_v2 MOV CX, 10 next: MOV AL, [SI] ;V1 OUT port1, AL ; 0832 MOV AL, [BX] ;V2 OUT port2, AL ; 0832 code OUT port3, AL INC SI INC BX LOOP next MOV AH, 4CH INT 21H ENDS END start ; 0832 17
3. ( 1 0CDH Vo D0 ~ D7 OW C DI0 ~ DI7 +5V ILE IOUT2 + A0 ~ A9 port1 port2 WR1 WR2 CS XFER DAC0832 RFB IOUT1 VREF -5V DGND - Vo MOV AL, 0CDH MOV DXport1 OUT DX, AL MOV DX, port2 OUT DX, AL 18
D0 ~ D7 IOW DI0 ~ DI7 +5V ILE IOUT2 + A0 ~ A9 port1 port2 WR1 WR2 CS XFER RFB IOUT1 VREF -5V DGND 0FFH=255I OUT1 = Vo = - IOUT1 RFB= - 255 V REF 256 255V 256R 0CDH=205V REF = -5V - Vo REF FB Vo = - 205V REF 256 = 4V 19
Vo V REF D0 ~ D7 DI0 ~ DI7 RFB IOUT1 +5V ILE IOUT2 + IOW WR1 A0 ~ A9 port1 port2 WR2 CS XFER DGND - V REF -5V Vo 4V -10V 8V 10V -8V V REF -10V, Vo = 8V V REF 10V, Vo = -8V 20
2 4V Vo 0V t 21
ode SEGMENT ASSUME CS:code tart: MOV CX, 8000H ; MOV AL, 0 ; ext: MOV DX, port1 ; OUT DX, AL MOV DX, port2 ; Vo OUT DX, AL 4V CALL delay ; INC AL ; CMP AL, 0CEH ; JNZ next ; MOV AL, 0 ; LOOP next ; 0V MOV AH, 4CH ; DOS INT 21H delay ode ENDS END start 22 CDH
4V Vo 0V Vo 4V t 0V 23 t
/ A/D ( ) A/D ( ) A/D A/D 24
A/D A/D 011 010 001 000 011 010 001 000 1v 2v 3v 4v 5v 6v 7v 25
, 26
A/D 8D/A 8 V i - A + C C=1 C=0 C V 8 0 D/A D 7 -D D/A 0 8 CLK 0 8 0 1 EOC S CLR D0~D7 27
S S 8 0 S 8D/A 00H 0V V o V i >V o C=1, 0 V i >V o C=1 V o V i, C=0 D7-D0V i A/D C A/D 28
A/D V i V 0... 0 A/D t S EOC 29
A/D A/D A/D A1 A2 30
A/D S 2 C V 01 V X S 1 - V V N A 01 1 - + A 2 + V 01m D D... 0 t 0 t 1 t 2 t 3 T 1 T 2 A/D A/D... 31
A/D A/D 0 S2 A1 Vo1=0V S 1 V X S 2, V x ) Vo1 A2 0 S1 V N V N Vo1 Vo1=0 32
T1 : 1 RC t V01= - ( Vx) dt = - 2 t1 T1 RC 1 T1 t 2 t1 ( Vx) dt 1 T 2 Vx = ( Vx) dt T T 1 t=t2 v01m= 1 RC T1 Vx 33
: T2 : v01=v01m+[ - 1 t 3 t 2 RC V Ndt] t=t3 v01=0 T1 RC Vx 0= v01m- Ndt = NT2, T2=T1 /vn f N T T 1=N 1 /f, T 2=N 2 /f. N1VN N2 =N1 Vx V RC Vx Vx V N2, N2 A/D N 1 t 3 t 2 RC V 34
A/D A/D 8D/A. D/A VoVX A/D 35
A/D V i V O - + CLK 8 D/A D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 36
A/D V i /V 5 5 3.75 4.375 4.69 4.84 4.73 4.80 2.5... 0 t T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8... A/D A/D 37
4.80V 123AD. 1 0 2 T1 D 7 1 8D/A 10000000B Vo 5V 128/255 Vo>Vi D 7 0 ( 1 ) 38
3 T2 D 6 1 D/A 01000000B 2.5VVo<Vi D 6 1 ( D6 "0") 3 T3 D 5 1 4 D 0 1 5 8 6 7 39
A/D D/A V0V V0Vi 10000000 5.0 V0>ViD7=0 01000000 2.5 V0<ViD6=1 01100000 3.75 V0<Vi D5=1 01110000 4.375 V0<Vi D4=1 01111000 4.69 V0<Vi D3=1 01111100 4.84 V0>ViD2=0 01111010 4.76 V0<Vi D1=1 01111011 4.80 V0<Vi D0=1 0 64 64+32=96 64+32+16=112 64+32+16+8=120 64+32+16+8=120 64+32+16+8+2=122 64+32+16+8+2+1=123 40
A/D A/D A/D A/D A/D 41
A/D ( ) 1. 2. 3. 42
1 A/D ADC 011 010 001 000 011 010 001 000 1v 2v 3v 4v 5v 6v 7v -0.5~0.5v 000 0.5~1.5v 001 1.5~2.5v 010 5.5~6.5v 110 6.5~7.5v 111 43
A/D 8A/D 8 10A/D 10 44
2 ADC 45
LSB 1 ADC 2 0LSB ADC : 3 ADC 4 1 4 LSB ADC 1 2 LSB 46
3 A/D 47
A/D 1. A/D 2. A/D 48
1. A/D 49
ADC ADC ADC ADC ADC 50
4 6 8 10 12 14 16 1s 1ms 1us 1ns 51
ADC ADC0809 ADC AD570ADC1210 52
2. A/D 1) A/D 2) A/D 53
) A/D A/D A/D ( A/D 54
2) A/D A/D A/D 55
A/D A/D A/D, A/D A/D 0~10V, 0~5V 2 A/D 56
ADC ADC ADC 57
ADC PC IOR IN AL, DX CLK IOR CPU 0 0 1 A15~A0 D7~D0 ADC PC I/O T 1 T 2 T 3 Tw T 4 IOR 58
ADC PC 0 IOR 0 1 IN AL, DX CLK A15~A0 IOR CPU ADC D7~D0 IOW PC I/O T 1 T 2 T 3 Tw 59 T 4
ADC PC 8? 12 12 ADC ADC CPU 60
IOR D3~D0 port_l port_h D7~D0 0 0 0 0 1 1 8 4 8 4 12 A/D buffer: IN Al, port_l MOV buffer, AL IN AL, port_h MOV buffer+1, AL 61
A/D D/A D/A DI7~DI0 ILE 1 8 LE1 8 DAC LE2 8 D/A VREF IOUT2 IOUT1 RFB CS WR1 XFER WR2 1 1 AGND VCC DGND 62
A/D A/D A/D A/D A/D 63
/D ADC ADC0804ADC0809ADC1210 CPU PC IOW 0 0 1 A/D A/D OUT DX, AL 64
ADC AD570AD571AD572 A/D CPU ADC PC IOW 0 0 1 A/D OUT DX, AL A/D 65
EOC A/D A/D ( ) A/D A/D 66
A/D CPU A/D A/D A/D EOC 67
A/D CPU A/D A/D CPU A/D A/D A/D A/D Y? N 68
EOC CPU CPU A/D CPU A/D CPU A/D PC IOR 0 0 1 A/D A/D IN AL, DX 69
A/D A/D N Y A/D? Y N 70
A/D CPU A/D IRQ4 A/D A/D PC 71
CLI 8259A STI A/D A/D A/D ( ) EOI 8259A IRET 72 DOS
HLT CLI 8259A STI A/D A/D HLT EOI Y IRET N 8259A 73
A/D READY CPUIN READY CPU I/O READY, A/D READY CPU A/D A/D 74
CLK T 1 T 2 T 3 Tw T 4 IO/M A19~A16 /S6~S3 A15~A8 A19~A16 IO M S6 ~ S3 AD7~AD0 A7 ~ A0 D7 ~ D0 ALE RD DT/R DEN READY 8088CPU, T3 READY READY Tw ; READY T4 75
IBM PC/XT IO CH RDY IO CH RDY A/D A/D PC 76
CLK Tw Tw Tw Tw T 1 T 2 T 3 T 4 A9~A0 D7~D0 IOR IO CK RDY T3 IO CK RDY IO CK RDY Tw IO CK RDY T4 77
A/D A/D A/D A/D Y? N A/D Y? N 78