查询 UA733 供应商 2-MHz Bandwidth 25-kΩ Input Resistance 捷多邦, 专业 PCB 打样工厂,2 小时加急出货 Selectable Nominal Amplification of 1, 1, or No Frequency Compensation Required A733C...D, N, OR NS PACKAGE A733M...J PACKAGE (TOP VIEW) IN+ NC GAIN ADJ 2A GAIN ADJ 1A V CC NC OUT+ 1 2 3 5 6 7 1 13 12 11 1 9 8 IN NC GAIN ADJ 2B GAIN ADJ 1B V CC+ NC OUT IN+ GAIN ADJ 2A GAIN ADJ 1A V CC OUT+ A733M...U PACKAGE (TOP VIEW) 1 2 3 5 1 9 8 7 6 IN GAIN ADJ 2B GAIN ADJ 1B V CC+ OUT NC No internal connection description/ordering information The µa733 is a monolithic two-stage video amplifier with differential inputs and differential outputs. Internal series-shunt feedback provides wide bandwidth, low phase distortion, and excellent gain stability. Emitter-follower outputs enable the device to drive capacitive loads, and all stages are current-source biased to obtain high common-mode and supply-voltage rejection ratios. Fixed differential amplification of 1 V/V, 1 V/V, or V/V may be selected without external components, or amplification may be adjusted from 1 V/V to V/V by the use of a single external resistor connected between 1A and 1B. No external frequency-compensating components are required for any gain option. The device is particularly useful in magnetic-tape or disc-file systems using phase or NRZ encoding and in high-speed thin-film or plated-wire memories. Other applications include general-purpose video and pulse amplifiers where wide bandwidth, low phase shift, and excellent gain stability are required. The µa733c is characterized for operation from C to 7 C; the µa733m is characterized for operation over the full military temperature range of 55 C to 125 C. TA ORDERING INFORMATION PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING P-DIP (N) Tube of 25 UA733CN UA733CN Tube of 5 UA733CD C to 7 C SOIC (D) UA733C Reel of 25 UA733CDR SOP (NS) Reel of 2 UA733CNSR UA733 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2, Texas Instruments Incorporated
symbol GAIN ADJ 1A GAIN ADJ 2A IN + IN GAIN ADJ 1B GAIN ADJ 2B + _ OUT+ OUT schematic VCC+ 2. kω 2. kω 1 kω 1.1 kω 1.1 kω IN + IN 7 kω OUT+ GAIN ADJ 1A 2A 5 Ω 5 Ω 1B 2B GAIN ADJ 7 kω OUT 59 Ω 59 Ω 3 Ω 1. kω 3 Ω Ω Ω VCC Component values shown are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) A733C A733M UNIT Supply voltage VCC+ (see Note 1) 8 8 V Supply voltage VCC (see Note 1) 8 8 V Differential input voltage ± 5 ± 5 V Common-mode input voltage ± 6 ± 6 V Output current 1 1 ma Continuous total power dissipation D package 86 See Dissipation Rating Table Package thermal impedance, JA (see Notes 2 and 3) N package 8 C/W NS package 76 Maximum junction temperature, TJ 15 C Lead temperature 1,6 mm (1/16 inch) from case for 6 seconds J or U package 3 C Storage temperature range, Tstg 65 to 15 65 to 15 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential input voltages, are with respect to the midpoint between VCC+ and VCC. 2. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) TA)/ JA. Operating at the absolute maximum TJ of 15 C can affect reliability. 3. The package thermal impedance is calculated in accordance with JESD 51-7. PACKAGE TA 25 C POWER RATING DISSIPATION RATING TABLE DERATING FACTOR DERATE ABOVE TA TA = 7 C POWER RATING TA = 125 C POWER RATING J (µa733m) 5 mw 11. mw/ C 1 C 5 mw 269 mw
electrical characteristics, V CC± = ±6 V, T A = 25 C AVD PARAMETER FIGURE TEST CONDITIONS GAIN A733C A733M OPTION MIN TYP MAX MIN TYP MAX UNIT Large-signal 1 25 6 3 5 differential voltage 1 VOD = 1 V 2 8 1 12 9 1 11 V/ V amplification 3 8 1 12 9 1 11 1 5 5 BW Bandwidth 2 RS = 5 Ω 2 9 9 MHz IIO Input offset current 3 2 2 Any. 5. 3 µa IIB Input bias current Any 9 3 9 2 µa VICR VOC VOO VOPP Common-mode input voltage range Common-mode output voltage Output offset voltage Maximum peakto-peak output voltage swing 1 Any ±1 ±1 V 1 Any 2. 2.9 3. 2. 2.9 3. V 1 1.6 1.5.6 1.5 2 & 3.35 1.5.35 1 1 Any 3.7 3.7 V 1 ri Input resistance 3 VOD 1 V 2 1 2 2 2 kω 3 25 25 ro Output resistance 2 2 Ω Ci Input capacitance 3 VOD 1 V 2 2 2 pf CMRR ksvr Vn tpd Common-mode rejection ration Supply voltage rejection ratio ( VCC/( VIO) Broadband equivalent input noise voltage Propagation delay time VIC = ±1 V, f 1 khz VIC = ±1 V, f = 5 MHz 2 6 86 6 86 2 7 7 1 VCC± = ±.5 V 2 5 7 5 7 db 5 BW = 1 khz to 1 MHz Any 12 12 µv 1 7.5 7.5 RS = 5 Ω, 2 Output voltage 2 6. 1 6. 1 ns step = 1 V 3 3.6 3.6 1 1.5 1.5 RS = 5 Ω, tr Rise time 2 Output voltage 2.5 12.5 1 ns step = 1 V 3 2.5 2.5 Isink(max) Maximum output sink current V db Any 2.5 3.6 2.5 3.6 ma No load, ICC Supply current Any 16 2 16 2 ma No signal The gain option is selected as follows: Gain Option 1: Gain-adjust pin 1A is connected to pin 1B, and pins 2A and 2B are open. Gain Option 2: Gain-adjust pin 1A and pin 1B are open, pin 2A is connected to pin 2B. Gain Option 3: All four gain-adjust pins are open.
electrical characteristics, V CC± = ±6 V, T A = C to 7 C for A733C, 55 C to 125 C for A733M AVD PARAMETER FIGURE TEST CONDITIONS Large-signal differential voltage amplification GAIN A733C A733M OPTION MIN MAX MIN MAX 1 25 6 2 6 UNIT 1 VOD = 1 V 2 8 12 8 12 V/ V 3 8 12 8 12 IIO Input offset current Any 6 5 µa IIB Input bias current Any µa VICR Common-mode input voltage range VOO Output offset voltage 1 1 Any ±1 ±1 V 1 1.5 1.5 2 & 3 1.5 1.2 VOPP Maximum peak-to-peak output voltage swing 1 Any 2.8 2.5 V ri Input resistance 3 VOD 1 V 2 8 8 kω CMRR ksvr Isink(max) Common-mode rejection ratio Supply voltage rejection ratio ( VCC /( VIO) Maximum output sink current VIC = +1 V, f 1 khz V 2 5 5 db 1 VCC± = ±.5 V 2 5 5 db Any 2.5 2.2 ma No load, ICC Supply current Any 27 27 ma No signal The gain option is selected as follows: Gain Option 1: Gain-adjust pin 1A is connected to pin 1B, and pins 2A and 2B are open. Gain Option 2: Gain-adjust pin 1A and pin 1B are open, pin 2A is connected to pin 2B. Gain Option 3: All four gain-adjust pins are open.
PARAMETER MEASUREMENT INFORMATION test circuits.2 µf + + VID VOD 2 kω VID.2 µf 5 Ω 5 Ω 5 Ω 5 Ω 1 kω 1 kω Figure 1 Figure 2 + VOD 2 kω VIC 5 Ω 5 Ω +.2 µf.2 µf 1 kω 1 kω Figure 3 Figure 2B 1B.2 µf + + VOD 2 kω 5 Ω 5 Ω.2 µf 1 kω Radj 1 kω 2A 1A VOLTAGE AMPLIFICATION ADJUSTMENT Figure 5 Figure 6
TYPICAL CHARACTERISTICS 5 PHASE SHIFT FREQUENCY 5 5 PHASE SHIFT FREQUENCY GAIN 2 Phase Shift Degrees 5 1 GAIN 2 Phase Shift Degrees 1 15 2 25 3 15 35 2 1 2 3 5 6 7 8 9 1 f Frequency MHz Figure 7 5 1 1 1 f Frequency MHz Figure 8 Voltage Amplification Relative to Value at T A = 25 C o 1.2 1.1 1..9 VOLTAGE AMPLIFICATION (SINGLE-ENDED OR DIFFERENTIAL) TEMPERATURE GAIN 1 GAIN 2 GAIN 3 A733C.8 75 5 25 25 5 75 1 125 TA Free-Air Temperature C Figure 9 GAIN 3 GAIN 2 GAIN 1 Voltage Amplification Relative to Value at V CC +_ = +_ 6 V 1. 1.2 1..8.6 VOLTAGE AMPLIFICATION (SINGLE-ENDED OR DIFFERENTIAL) SUPPLY VOLTAGE GAIN 3 GAIN 2 GAIN 1. 3 5 6 7 8 VCC± Supply Voltage V Figure 1
TYPICAL CHARACTERISTICS AVD Differential Voltage Amplification 1 7 2 1 7 2 DIFFERENTIAL VOLTAGE AMPLIFICATION RESISTANCE BETWEEN G1A AND G1B VOD = 1 V See Figure 6 VS Single-ended Voltage Amplification db A 5 3 2 1 SINGLE-ENDED VOLTAGE AMPLIFICATION FREQUENCY GAIN 1 GAIN 2 GAIN 3 1 1 1 1 k k 1 k Radj Resistance Between G1A and G1B Ω Figure 11 1 1 1 f Frequency MHz Figure 12 2 18 16 SUPPLY CURRENT FREE-AIR TEMPERATURE 2 2 No Load No Signal SUPPLY CURRENT SUPPLY VOLTAGE I CC Supply Current ma 1 12 1 8 6 2 No Load No Signal A733C I CC Supply Current ma 16 12 8 75 5 25 25 5 75 1 125 TA Free-Air Temperature C Figure 13 3 5 6 7 8 VCC± Supply Voltage V Figure 1
TYPICAL CHARACTERISTICS V OPP Maximum Peak-to-Peak Output Voltage V MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE LOAD RESISTANCE 5 3 2 1 1 1 1 k k 1 k RL Load Resistance Ω Figure 15 V OPP Maximum Peak-to-Peak Output Voltage V 8 7 6 5 3 2 1 MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE SUPPLY VOLTAGE 3 5 6 7 8 VCC± Supply Voltage V Figure 16 V OPP Maximum Peak-to-Peak Output Voltage V 6 5 3 2 1 MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE FREQUENCY Figure 17 1 2 7 1 2 7 1 2 f Frequency MHz Input Resistance kω i r 35 3 25 2 15 1 5 INPUT RESISTANCE FREE-AIR TEMPERATURE GAIN 2 A733C 6 2 2 6 8 1 12 1 TA Free-Air Temperature C Figure 18
MECHANICAL DATA MCFP1A JANUARY 1995 REVISED DECEMBER 1995 U (S-GDFP-F1) CERAMIC DUAL FLATPACK.5 (1,1).26 (,66).25 (6,35).26 (6,1) Base and Seating Plane.8 (2,3).5 (1,27).8 (,2). (,1).3 (7,62) MAX 1 1.19 (,8).15 (,38).28 (7,11).23 (5,8).5 (1,27).35 (8,89).25 (6,35) 5 6.35 (8,89).25 (6,35) Places.5 (,13) MIN 179/ B 3/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only. E. Falls within MIL STD 1835 GDFP1-F1 and JEDEC MO-92AA
MECHANICAL DATA MLCC6B OCTOBER 1996 FK (S-CQCC-N**) 28 TERMINAL SHOWN LEADLESS CERAMIC CHIP CARRIER 18 17 16 15 1 13 12 NO. OF TERMINALS ** MIN A MAX MIN B MAX 19 11 2.32 (8,69).358 (9,9).37 (7,8).358 (9,9) A SQ B SQ 2 21 22 23 2 25 26 27 28 1 2 3 1 9 8 7 6 5 28 52 68 8.2 (11,23).6 (16,26).739 (18,78).938 (23,83) 1.11 (28,99).58 (11,63).66 (16,76).761 (19,32).962 (2,3) 1.165 (29,59).6 (1,31).95 (12,58).95 (12,58).85 (21,6) 1.7 (26,6).58 (11,63).56 (1,22).56 (1,22).858 (21,8) 1.63 (27,).2 (,51).1 (,25).8 (2,3).6 (1,63).2 (,51).1 (,25).55 (1,).5 (1,1).5 (1,1).35 (,89).28 (,71).22 (,5).5 (1,27).5 (1,1).35 (,89) 1/ D 1/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 65533 Dallas, Texas 75265 Copyright 2, Texas Instruments Incorporated