FPGA Advantage HDS2003.2 Mentor Graphics FPGA ModelSim Precision FPGA ( ) View All 1. Project HDL Designer Project Project Library project Project <project_name>.hdp project example project example.hdp Design Manager Project New Project Project 1
New Project, Creating a New Project 2
Project Next Project Summary Next Project Content Create design files, Finish 3
Project,Tutorial C:\tmp\Myproject\TUTORIAL\hds HDL C:\tmp\Myproject\TUTORIAL\hdl 2 Options Main General VHDL OK 4
Verilog Verilog Graphical Design Tutorial Chapter 2 Verilog Timer Exercise ( Design Manager Help HDL Designer Series Tutorials) 5
3 TOP-DOWN TUTORIAL Designer Manager Graphical View > Block Diagram 6
4 Blocks (add block) <library> <block> I1 I0 5 7
Block Block Embedded Block Block Embedded Block 6 I0 I1 eb1 8
std_logic std_logic_vector(15 downto 0) Object Properties 7 Bundle bundle I0 bundle0 Bundle global connector global connector 9
8 TUTORIAL Design Unit Timer OK Designer Manager Vew > SubWindows > Design Hierarchy Design Hierarchy 10
Design Units Timer Design Hierarchy 11
VHDL 9 Timer Object Properties Diagram > Singals > Scope for Changes Entire Net in diagram Object Properties Apply change to control Control 12
Declaration Visibility Singal Visibility 13
10 HDL OR1 Open New View Text OK HDL OR1 OR1 14
alarm <= hold OR beep; VHDL OK Apply Change Shape OR OR 15
Embedded Block Mentor Graphics 11 Control Control Open As > New View State Diagram Next Finish Control 16
12 s0 s1 s2 s3 s4 Designer Manager 17
Control Block 13 Object Properties s0 18
Name Actions VHDL 19
IF Condition IF Use Priority 20
ZEROS Declaration Diagram > State Machine Properties Architecture Declaration Tab Constant ZEROS : std_logic_vector := "0000000000"; OK 14 count count State Type Hierarchical State 21
22
15 Diagram > State Machine Properties Signals Status ( Status Help smdesign.pdf) 23
Generation Help Panel 24
16 HDL Tasks Generate Warning Error Log Window Generate HDL View > Mode >HDL Files, HDL HDL 25
17 BCDCounter HDL Designer Import Mentor Counter BCDCounter BCDCounter Designer Manager HDL Import HDL Import Wizard Next 26
Directory Browser HDS examples\tutorial_ref\import\timer Timer_BCDCounter.vhd Add Timer_BCDCounter.vhd Files to Convert Next 27
TUTORIAL Next Finish Log Designer Manager TUTORIAL Top Marker Toggle Top Marker 18 Timer Counter Open As > New View, Block Diagram, Next 28
Finish Add Component TUTORIAL BCDCounter 29
BCDCounter 30
I0 I1 BCDCounter Add Signal Stubs OK HDL Designer Stub Diagram >Autoroute > AutoRoute Option clear load dat_in Autoroute>AutoRoute 31
delay BCDCounter Generics 10 ns 5 ns 5 ns 19 ModuleWare ModuleWare Mentor HDL ModuleWare Window ModuleWare GROUND 32
Constants Ground carry_in carry_in Ground Dout 4 Set port size 4 33
gnd Object Properties 34
User Declarations gnd VHDL VHDL 35
ModuleWare Logic N Input NOR zero2 zero zero2 HDL 36
20 Counter DtoB True Table Embedded Block View Embedded Block A B C 1 2 3 37
Table Designer Hierarchy Timer Expand All Designer Manager Timer generate HDL files Log HDL Design Manager View > Mode > HDL Files, 38
HDL HDL HDL VHDL HDL 21 Test bench Designer Manager Timer File New Create 39
Test Bench Designer Manager Timer_tb VHDL Test Bench Component Timer_tester Timer_tester Import 40
Designer Manager HDL Import HDL Import Wizard BCDCounter Timer_tester.vhd TUTORIAL Designer Manager Timer_tester Timer_tb Timer_tester Add Component TUTORIAL Timer_tester Timer Generate Through Components HDL 41
22 DownStream ModelSim Precision Designer Manager Options > Main Main Setting User Variables 23 Designer Manager View > SubWindows > Task and Templetes Tasks Design Explorer Timer_tb Tasks ModelSim Complier Design Explorer Timer_tb ModelSim 42
timer_tb ModelSim Modelsim view d w DataFlow 24 Control 43
Diagram Instrument HDL for animation 44
ModelSim # hds_anim_prefs 10000 0 0 # hds_anim_enable /Timer_tb/I0/I0/ TRUE 0 - current_state # Now sending details of /timer_tb/i0/i0 to HDS for animation run -all # ** Note: Count suspended correctly # Time: 8450 ns Iteration: 1 Instance: /timer_tb/i1 # ** Note: Alarm asserted correctly # Time: 11355 ns Iteration: 0 Instance: /timer_tb/i1 # ** Failure: Timer test completed # Time: 12150 ns Iteration: 1 Instance: /timer_tb/i1 # Break at D:/mentor/FPGAdv53/Hds/examples/tutorial_ref/TIMER_Vhdl/hdl/timer_tester_test.vhd line 139 45
25 Designer Manager Timer FPGA Add IO Pads OK Precision Project Output Files RTL Area Report Timming Report 46
xilinx ISE Altera Quartus ISE5.2 QuartusII ISE5.2 ngd2vhdl: Processing design... ngd2vhdl: Preping physical only global signals... ngd2vhdl: Preping design's networks... ngd2vhdl: Preping design's macros... WARNING:NetListWriters:306 - Signal bus I0/current_state( 8 downto 0 ) on block Timer is not reconstructed, because there are some missing bus signals. WARNING:NetListWriters:306 - Signal bus I0/next_state( 7 downto 0 ) on block Timer is not reconstructed, because there are some missing bus signals. ngd2vhdl: Preping design completed. ngd2vhdl: Writing VHDL netlist Timer_out.vhd... 47
ngd2vhdl: Setting external property filter file to d:/xilinx/data/xdm2vhdl.prp. ngd2vhdl: Writing file Timer_out.vhd completed. ngd2vhdl: Writing VHDL SDF file Timer_out.sdf... ngd2vhdl: Writing file Timer_out.sdf completed. Info: place_and_route returned successfully Timer_out.sdf Timer_out.vhd Error, Tools > Options 26 48
Xilinx Simprim EDA Xilinx ISE 5.1i ISE compxlib compxlib -s mti_se -f all -l vhdl -o c:\libs ModelSim vhdl Xilinx Synthesis and Simulation Design Guide ALTERA MAXPLUSII alt_vtl maxplus2/vhdl87/vital maxplus2/vhdl93/vital QuartusII alt_vtl lpm 220model.vhd 220pack.vhd quartus/eda/sim_lib/ MODELSIM lpm vlib lpm vmap lpm < /myalteralib/lpm> lpm vcom work lpm vcom work lpm < /sim_lib/220pack.vhd> < /sim_lib/220model.vhd> FPGA IEEE 49
Modelsim VHDL Modelsim modelsim.ini [Library] std = $MODEL_TECH/../std ieee = $MODEL_TECH/../ieee verilog = $MODEL_TECH/../verilog std_developerskit = $MODEL_TECH/../std_developerskit synopsys = $MODEL_TECH/../synopsys modelsim_lib = $MODEL_TECH/../modelsim_lib lpm = < /myalteralib/lpm> lpm Modelsim library apex20k Modelsim apex20k vlib apex20k vmap apex20k < /myalteralib/apex20k> vcom work apex20k < /eda/sim_lib/apex20k_atoms.vhd> vcom work apex20k < /eda/sim_lib/apex20k_componenets.vhd> modelsim.ini Using Altera MegaWizard Plug-In Manager with FPGA Advantage.pdf Xilinx Simprim Simprim $Xilinx\vhdl\src\simprims 27 Designer Manager Timer Import Gate Level 50
HDL Netlist SDF Timer_out.vhd Timer_out.sdf OK Designer Manager Timer Views VHDL RTL EDIF VHDL Timer_out.vhd Timer View Timer_tb Modelsim add w * run all 51
high low FPGA 010 68058081/82/83, 010 68058085 52