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2 Idea Architecture Design IC Fabrication Wafer (hundreds of dies) Sawing & Packaging Block diagram Final chips Circuit & Layout Design Testing Layout Bad chips Good chips customers 3 2
4 IC Fabless Design Houses Integrated service EDA: Electronic Design Automation IP: silicon Intellectual Property SOC: System-On-A-Chip design IDM: Integrated Device Manufacturer EDA Tools Companies Design Service Companies Library & IP Providers Dedicated IC Manufacturers (Foundry) Packaging & Testing Houses 5 3
6 Behavioral Domain Structural Domain program subroutines Design Process: instructions ( -> -> ) architecture block diagram cell schematic layout placement floorplan Physical Domain 7 4
Routing Channel SRAM SRAM Data paths Standard cells Video-encoder chip [Brodersen92] 8 9 5
(Algorithm) Function Specification: A / B = Q + R Procedure of sequential divider (using shift-and-subtract) Example : A = 1011, B = 0010 iteration Partial Reminder Quotient iteration Partial Reminder Quotient 0 00001011???? 3 00011?010 1 0001011???0 4 0011 0101 2 001011??01 Result 0001 0101 A/B = (11/2) = 5 + 1 10 - B ( ) R (Partial Remainder) Q ( ) 0 0 1 0 0 0 0 0 1 0 1 1 0??? S R = R << 1; computation of i-th iteration if R [7:4] > B Next_R = R Next_Q[i] = 0 Next_R = R - B Next_Q[i] = 1 E 11 6
(Flow-Chart) If (!start) Start If (start) count = 4; Y1 States = {Start, Y1, Y2} If (count!= 0) R = R << 1; count ++; if R [7:4] > B Next_R = R Next_Q[i] = 0 Next_R = R - B Next_Q[i] = 1 Y2 If (count == 0) 12 (Synthesis) Start Y1 R = R << 1; count ++; if R [7:4] > B Next_R = R Next_R = R - B Next_Q[i] = 0 Next_Q[i] = 1 Register-Transfer Level (RTL) code (Verilog or VHDL) Y2 synthesis Standard cell library (INV, BUF) (NAND, NOR) (AOI, AIO, MUX), (Full-Adder, Half-Adder) (Flip-Flop) 13 7
A cell can be decomposed into a number of transistors D S N-channel G P-channel G S D MOS transistor 14 NOR-gate schematic NOR-gate Layout VDD V OUT GND V A V B 15 8
16 Inputs: two natural numbers x1 and x2 Output: the greatest common divisor of x1 and x2 Example: (9, 6) (3, 6) (3, 3) Found GCD = 3 START u=x1; v=x2; Flow-Chart of GCD yes u = u-v; u > v no no u==v yes v = v-u; done = 1; GCD = u; END 17 9
START u=x1; v=x2; α no u > v yes u = u-v; no v = v-u; u==v β Flow-Chart yes done = 1; GCD = u; END EFSM model if(! start ); if( u>v ) u=u-v; if( start ) {u=x1; v=x2;} if(! (u>v) ); if( u==v ) S0 S1 done=1; GCD=u; if( u!= v ) S2 v = v u; S3 if(1); 18 case(state) `S0: if(start) begin next_u <= x1; next_v <= x2; next_state <= `S1; end `S1: if(u > v) next_u <= u v; else next_state <= `S2; `S2: if(u==v) done<=1; GCD<=u; next_state <= `S3; else next_v = v u; next_state <= `S1; `S3: begin end endcase if(! start ); if( u>v ) u=u-v; if( start ) S0 {u=x1; v=x2;} if(! (u>v) ); if( u==v ) S1 done=1; if( u!= v ) S2 GCD=u; v = v u; S3 if(1); 19 10
20 image sensor array decoder and controller CDS (correlated double sampling) Multiplexor Analog-to-Digital Converter clock enable 8-bit digital output 21 11
(Sensor Cell) Operation of a cell V DD V DD source follower (1) Reset (2) Integration reset X A sensor cell RS photo diode Con. CDS MUX RS: row select ADC column line 22 Voltage at node X integration time Reset X weak illumination stronger illumination E D A B C 1 ms Time 23 12
analog output after CDS (volt) 2.0 1.8 1.6 1.4 1.2 1 Dynamic range ~ 20 log (4000) ~ 70 db saturation region Illumination (Lux) 0 5000 10000 15000 20000 25000 24 (1) (Step 1) Logarithmic Output Response (Step 2) Dynamic Range Dark Current and others Output (volt) Output (volt) Illumination (Lux) enhance response under low-light Illumination (Lux) 25 13
(2) Output (volt) (Step 1) Logarithmic Output Response (Step 2) Dynamic Range Dark Current and others Output (volt) higher dynamic range enhance response under high-light Illumination (Lux) Illumination (Lux) 26 Logarithm is approximated via a nonlinear ADC CDS output output code 255 x = code Illumination (Lux) analog input to ADC Illumination (Lux) 27 14
ADC? Input: Given an analog voltage, say 0.35 Output: What is the digital output code? 0.35 V Analog Voltage 0 V 0.25 V 0.5 V 0.75 V 1 V 0 4 8 12 16 Digital Code 28 Narrow down the possible code ranges quickly 0 V 0.25 V 0.5 V 0.75 V 1 V Output bit D 3 =0 0 V 0.25 V 0.5 V 0.75 V 1 V 0 V 0.25 V 0.5 V 0.75 V 1 V 0 V 0.25 V 0.5 V 0.75 V 1 V D 2 =1 D 1 =0 D 0 =0 Final output code for 0.35 V is D 3 D 2 D 1 D 0 = 0101 29 15
ADC 30 ADC Linear ADC Table lookup V in clk S/H comparator 10-bit code 1024 x 8 mapping table 8-bit code 10-bit DAC control logic 10-bit SAR 8-bit S/H: sample-and-hold clk 10-bit 31 16
Advantages: (1) conversion time is reduced from 11 to 9 cycles (2) table size is reduced to ~ 1/4 V in clk S/H comparator 8-bit 10-bit DAC 256 x 10 mapping table control logic 8-bit SAR 10-bit 8-bit code clk 32 ADC Integral Noise Level 0.42 LSB (Least Significant Bit Level) 0.1 0.0-0.1 INL (LSB) -0.2-0.3-0.4-0.5-0.6 0 32 64 96 128 160 192 224 256 Output code 33 17
34 Controller 176 x 144 Sensor Array Buf CDS ADC Periphery 35 18
Technology power supply resolution frame rate pixel size chip size power dissipation TSMC 0.35 µm 1P4M 3.3 V 176 x 144 (QCIF) 30 frame/s 7.5 x 7.5 µm 2 3041 x 3041 µm 2 30 mwatt 36 Signal Path: Pixel CDS MUX ADC 37 19
(1/5) 38 (2/5) 39 20
(3/5) 40 (4/5) Original Ours 41 21
(5/5) Original Ours 42 43 22
IC CS EE & CS CS EE & CS EE & CS CS EE & CS EE & CS EE EE & CS EE & CS EE, EE EE 44 23