FBC0409 V1.0 1.0 05.06.22
SIA 2005 SIA SIA SIA SIA SIA 114 86-24-23970133 HTTP://WWW.SIA.CN YANG@SIA.CN 2
...5...5...6 PIN...6...7 1 CPU...8 2...8 4...8 5 DMA...9 7....9 8...9 9...10 A...10 B...10...11. FBC0409...11....22....24 1...24 2...24 1 /...4 2 FBC0409...7 3 /...20 4 23 5 FBC0409...24 1 FBC0409...6 2 FBC0409 PIN...6 3 FBC0409...8 4 FBC0409...15 5 FBC0409.22 3
/ / FB FOUNDATION FIELD BUS: FBC FOUNDATION FIELD BUS CONTROLLER IEC INTERNATIONAL ELECTRONIC COMMITTEE: MAU MEDIUM ATTACH UNIT: DMA DIRECT MEMORY ACCESS: FCS FRAME CHECK SEQUENCE: 1 / 4
FBC0409 IEC 1158-2 FBC0409 / MAU FBC0409 4k RAM DMA CPU CPU / FBC0409 / FCS 16 1MS 16 1/32MS 16 FBC0409 FB 31.25KBIT/S / 2 DMA 4KBYTE SRAM ; CPU SRAM 1MS (1/32)MS OCTET INTEL ARM CPU STANDBY -40 85 <600UA 44 TQFP
FB 1 FBC0409 PIN FBC0409 TQFP 44 10MM X 10MM PIN 1.8MM 35 2 FBC0409 PIN 6
FBC0409 PB_ADDR[11:0] INPUT 13 PB_DATA[7:0] INOUT 8 PB_RAMCS_N INPUT RAM PB_REGCS_N INPUT RST_N INPUT PB_WR INPUT CPU PB_RD INPUT CPU SCLK INPUT CPU NCLK INPUT SCLK PO_CLK125K OUTPUT 125k PO_READY OUTPUT CPU RAM CPU PO_READY 0 PBO_INT_N OUTPUT PBI_INT_N INPUT TXEN OUTPUT FF TX_FFD OUTPUT FF RX_FFD INPUT FF VDDIO POWER IO 3.3V 5V VDD_CORE POWER 3.3V VSS GND 2 FBC0409 FF FBC0409 IEC 1158-2 INTEL 80188/80186 ARM CPU FF MANCHESTER MAU FCS 1MS 1MS/32 CPU 512 CPU DMA 4KByte SRAM 7
3 FBC0409 DMA CPU SCLK SCLK NCLK 500KHZ CPU SRAM 1 CPU CPU CPU CPU CPU SRAM SRAM CPU SRAM PB_DATA[7:0] CPU SRAM CPU FBC0409 po_rdy CPU CPU RAM PO_RDY RAM PO_RDY 2 CPU CPU CPU CPU PB_REGCS_N PB_WR PB_RD 4 SCLK NCLK 500KHZ 8
3 1MS 1/32MS 256US 16 FREE RUNNING 16 CPU 0x1f 5 DMA DMA CPU CPU DMA 2 SRAM DMA SRAM CPU SRAM PO_READY CPU 6 CPU CPU DMA DMA CPU DMA CPU RAM PO_READY DMA PO_READY DMA DMA CPU 7. ARME PSA FRAME_CODE NS HL NODE_ID[7:0] AMOF HL NS DMA SRAM NS HL AMOF ETDF 8 FF / CPU DMA DMA DRE CPU 9
RDRF_INT CPU DMA DMA SRAM CPU SRAM DMA CPU 9 CPU FF CRC CPU DMA DMA DTE CPU TDRE_INT CPU DMA SRAM DMA DMA TRM_REG 2 DMA 512 JI_INT A DMA FF 500KHz MD[1:0 00 SCLK CLK_DIV SCLK/ CLK_DIV +1 SRAM 8MHz 32MHZ CLK_DIV 0x3 20MHZ CLK_DIV 0x1 2 1/2/4/8/16 CLK_DIV 0/1/3/7/15 500KHz SCLK NCLK 2 CLKSEL FF ICLK 0 SCLK 1 NCLK MD[1:0] BR[4:0] 500KHz 16 FF MD 00: 01:H1 BR CLK500 =ICLK/(BR+1) 2 BR 0/1/3/7/15/31 B 10
FF 4K SRAM RAM PB_REGCS_N PB_RAMCS_N REGISTER RAM RAM 6 H00~6 H3F RAM RAM 12 H000~12 HFFF 11 d4095 12 HFC0~12 HFFF 6 1 REG_CSN 6 RAM 12 H000~12 HFBF 12 D4032. FBC0409 FBC0409 0x00 0x01 0x02 0x03 TRM_REG[7:0] WO DATA REG RCV_REG[7:0] RO FB_CMD0[5:0] PSE[1:0] 0x01[1:0] TFCE 0x01[2] W/R CMD REG TDE 0x01[3] FDM 0x01[4] RDE 0x01[5] FB_CMD1[4:0] ARME 0x02[0] CMD REG DRE 0x02[1] DMA W/R DTE 0x02[2] DMA LOOPBK 0x02[3] MAU_ENF 0x02[4] MAU FB_CMD2[7:0] BR[4:0] 0x03[4:0] 500K WO CMD REG MD[1:0] 0x03[6:5] 00 11
0x03 0x04 CLKSEL ISR_MSTR[4:0] CISF AISF TISF ERRF EIF ISR0[7:0] TDRE_INT TIF_INT RIF_INT REDF_INT REF_INT RSDF_INT RAF_INT 0x03[7] 0x03[0] 0x03[1] 0x03[2] TIMER/CLOCK 0x03[3] 0x03[7] PI_INT 0x04[0] 0x04[1] 0x04[2] 0x04[3] RCV_END_DLMT 0x04[4] 0x04[5] RCV_START_DLMT 0x04[6] FF (RCV ACTV) RO INTERRUPT MASTER RDRF_INT 0x04[7] 0x04 INT_CLR0[7:0] 1 WO CLEAR INT0 0x05 ISR1[3:0] BMDF_INT AMDF_INT EOTF_INT 0x05[0] 0x05[1] 0x05[2] FCF_INT 0x05[3] 0x05 INT_CLR1[3:0] 1 0x06 ISR2[5:0] MS1_32COF_INT 0x06[0] 1/32MS 0 MS1_32CF_INT 0x06[1] 1/32MS MS1COF_INT 0x06[2] 1MS 0 MS1CF_INT 0x06[3] 1MS OOF_INT 0x06[4] 0 OCF_INT 0x06[5] 0x06 INT_CLR2[5:0] 1 0x07 ISR3[6:0] LSDF_INT 0x07[0] RC RC WO RC WO RC INT0 INT1 CLEAR INT1 INT2 CLEAR INT2 INT3 12
LEDF_INT LNGFRM_INT MDERR_INT LCD_INT TRM_FAIL_INT 0x07[1] 0x07[2] 0x07[3] 0x07[4] CD 0x07[5] JI_INT 0x07[6] 0x07 INT_CLR3[6:0] 1 WO 0x08 ISR0_MSK[7:0] INT0 W/R 0x09 ISR1_MSK[3:0] W/R 0x0A ISR2_MSK[5:0] INT2 W/R 0x0B ISR3_MSK[6:0] INT3 W/R 0x0C TRM_BYTECNT[13:8] W/R 0x0D TRM_BYTECNT[7:0] W/R 0x0E TRM_BUFPTR[13:8] DMA W/R 0x0F TRM_BUFPTR[7:0] DMA W/R 0x10 0x11 0x12 RCV_BUFPTR[13:8] DMA 0x13 RCV_BUFPTR[7:0] DMA 0x14 0x15 W/R W/R CLEAR INT3 0x16 MATCH_VECT[13:8] RO 0x17 MATCH_VECT[7:0] RO 0x16 ADR_TABNS[13:8] NS WO 0x17 ADR_TABNS[7:0] NS WO 0x18 FRAME_CODE[4:0] RO 0x19 FRAME_CONTRL[7:0] RO 0x18 ADR_TABHLNS[13:8] HLNS WO CONFIGURE 0x19 ADR_TABHLNS[7:0] HLNS WO CONFIGURE 0x1A 0x1B NODE_ID[7:0] W/R CONFIGURE STATUS0[7:0] TDRE_STAT 0x1C[0] 13
0x1C 0x1D 0x1E TIF_STAT FCSF STAT REDF_STAT RDEF_STAT RSDF_ STAT RAF_ STAT RDRF_STAT STATUS1[7:0] RBMF_STAT AMOF_STAT ETDF_STAT RFCF_STAT RPSAF_STAT RNAF_STAT 0x1C[1] 0x1C[2] 0x1C[3] 0x1C[4] RCV_OVERFLOW 0x1C[5] RCV_START_DLM 0x1C[6] FF (RCV ACTV) 0x1C[7] 0x1D[0] 0x1D[1] 0x1D[2] 0x1D[3] 0x1D[4] PSA 0x1D[5] 8 NS_STAT 0x1D[6] NS ( 16 ) HL_STAT STATUS2[6:0] LSDF_STAT LEDF_STAT LNGFRM_STAT MDERR_STAT LCD_STAT LTAF_STAT 0x1D[7] HL (32 ) 0x1E[0] 0x1E[1] 0x1E[2] 0x1E[3] 0x1E[4] 0x1E[6] RO RO RO RSPF_STAT 0x1E[7] 0x1F TIMER_LATCH 0x20 MS1_32CNT[15:8] 1/32MS RO 0x21 MS1_32CNT[7:0] 1/32MS RO 0x20 MS1_32COMP[15:8] 1/32MS WO 0x21 MS1_32COMP[7:0] 1/32MS WO 0x22 MS1_CNT[15:8] 1MS RO 0x23 MS1_CNT[7:0] 1MS RO 0x22 MS1_COMP[15:8] 1MS WO 0x23 MS1_COMP[7:0] 1MS WO 0x24 OCT_CNT[15:8] RO 0x25 OCT_CNT[7:0] RO 0x24 OCT_COMP [15:8] WO STATUS0 STATUS1 STATUS2 14
0x25 OCT_COMP [7:0] WO 0x26 CLK_DIV [3:0] RAM WR 0x27 0x01 W/R 4 FBC0409 8 DMA 5 FBC0409 TRM_REG 0x00 CPU DMA CPU CPU CPU 00 TDRE 0 0x1C TDRE_INT 0 0x04 TDRE 1 TDRE_INT 1 DMA CPU DMA CPU CPU DMA DMA 0x00 CPU 00 CPU RDRF 0 0x1C RDRF_INT 0x04 RDRF 1 RDRF_INT 1 CPU DMA RAM FF 0 3 0 FB_CMD0 0x01 0 0 RDE FDM TDE TFCE PSE[1:0] RDE RECEIVE DATA ENABLE 0 1 15
FDM FULL/HALF DUPLEX MODE / 1 0 TDE TRANSMIT DATA ENABLE 0 1 TFCE TRANSMIT FRAME CHECK ENABLE 0 1 PSE[1:0] PREAMBLE SEQUENCE ENABLE 00 1 01 2 10 3 11 4 1 FB_CMD1 0x02 0 0 0 MAU_ENF LOOPBK DTE DRE ARME MAU_ENF MAU ENABLE FLAG MAU 1 MAU 0 MAU LOOPBK LOOPBACK MODE FLAG 1 FF 0 DTE DMA TRANSMIT ENABLE DMA 0 DMA 1 DMA DRE DMA RECEIVE ENABLE DMA 0 DMA 1 DMA ARME ADDRESS RECOGNITION MODE ENABLE 1 2 FB_CMD2 0x03 CLKSEL MD1 MD0 BR4 BR3 BR2 BR1 BR0 CLKSEL CLOCK SOURCE SELECTS 0 CPU SCLK 1 NCLK MD1-MD0 CLOCK MODE SELECTS 11 31.25KHZ BR[4:0] BAUD RATE SELECT CLKSEL 500K 500K / BR+1 16MHZ BR4-BR0 11111 2 1/2/4/8/16/32 BR 0/1/3/7/15/31 3 FB_CMD3 0x26 0 0 0 0 CLK_DIV[3:0] CLK_DIV[3:0] SCLK 4~6M / CLK_DIV +1 32MHZ CLK_DIV 0x7 20MHZ CLK_DIV 0x3 2 1/2/4/8/16 CLK_DIV 0/1/3/7/15 FF 0-3 0-3 ISR_MSTR 0x03 EIF 0 0 0 ERRF TISF AISF CISF EIF EXTERNAL INTERRUPT FLAG PI_INT 0 ERRF ISR3 TISF TIMER INTERRUPT SOURCE FLAG 2 6 1 TISF 1 AISF ADDRESS INTERRUPT SOURCE FLAG 1 4 16
AISF 1 CISF COMMUNICATION INTERRUPT SOURCE FLAG 0 8 CISF 1 4 1 FF PO_INT 0 ISR0 0x04 0 FF 0 CPU CPU 0x04 CPU 1 0 RDRF_INT RAF_INT RSDF_INT REF_INT REDF_INT RIF_INT TIF_INT TDRE_INT RDRF_INT RECEIVE DATA REGISTER FULL RDRF_INT 1 RAF_INT RECEIVE ACTIVE FLAG CD RAF_INT 1 RSDF_INT RECEIVE START DELIMITER FLAG RSDF_INT 1 REF_INT RECEIVE ERROR FLAG REF_INT 1 REDF_INT RECEIVE END DELIMITER FLAG REDF_INT 1 RIF_INT RECEIVE IDLE FLAG RIF_INT 1 TIF_INT TRANSMIT IDLE FLAG TIF_INT 1 CPU TDRE_INT TRANSMIT DATA REGISTER EMPTY TDRE_INT 1 1 ISR1 0x05 1 1 CPU 1 CPU 0x05 CPU 1 1 0 0 0 0 FCF_INT EOTF_ING AMDF_INT BMDF_INT FCF_INT FRAME CONTROL FLAG FCF_INT 1 EOTF_INT END OF TABLE FLAG 0 ETOF_INT 1 AMDF_INT ADDRESS MATCH DETECTION FLAG AMDF_INT 1 BMDF_INT BROADCAST MESSAGE DETECTION FLAG BMDF_INT 1 2 ISR2 0x06 2 2 CPU CPU 0x06 CPU 1 1 0 0 OCF OOF 1CF 1OF 1/32CF 1/32OF OCF OCTET COUNTER FLAG OCF 1 RESET 0 0 17
OOF OCTET OVERFLOW FLAG 0xFFFF OOF 1 1CF 1MS COUNTER FLAG 1MS 1MS 1MS 1CF 1 OCF 1OF 1MS OVERFLOW FLAG 0xFFFF OOF 1 1/32CF 1/32MS COUNTER FLAG 1/32MS 1/32MS 1/32MS OCF 1 OCF 1/32OF 1/32MS OVERFLOW FLAG 1/32MS 1/32MS 0xFFFF OOF 1 3 ISR3 0x07 3 FF 3 CPU 1 CPU 0x07 CPU 1 1 0 JI_INT TRM_FAIL_INT LCD_INT LNGFRM_INT MDERR_INT LEDF_INT LSDF_INT JI_INT JABBER INDICATION JI_INT 1 TRM_FAI_INT TRANSMIT FAILUE TRM_FAIL_INT 1 LCD_INT LOST CARRIER DETECTION CD LCD_INT 1 LNGFRM_INT LONG FRAME LNGFRM_INT 1 MDERR_INT MANCHESTER DECODE ERROR N+ N- MDERR_INT 1 LEDF_INT LOST END DELIMITER FLAG LEDF_INT 1 LSDF_INT LOST START DELIMITER FLAG LSDF_INT 1 0 ISR0_MSK 0x08 0 0 0 1 0 0 / 1 ISR1_MSK 0x09 1 1 1 1 1 0 / 2 ISR2_MSK 0x0A 2 2 2 1 2 0 / 3 ISR3_MSK 0x0B 3 3 3 1 18
3 0 / TRM_BYTECNT[13:0] 0x0C-0x0D TRM_BUFPTR[13:0] 0x0E-0x0F RCV_BUFPTR[13:0] 0x12-0x13 MATCH_VECTOR[13:0] 0x16-0x17 1 1 NS ADR_TABNS[13:0] 0x16-0x17 NS FRAME_CNTRL[7:0] 0x18 FRAME_CODE[4:0] 0x19 5BIT CPU FCODE MESSAGE FUNCTION FCODE MESSAGE FUNCTION 00000 ESTABLISH CONNECTION 1 10000 DATA TRANSFER 5 00001 ESTABLISH CONNECTION 2 10001 STATUS RESPONSE 00010 DISCONNECT CONNECTION 1 10010 COMPEL TIME 00011 DISCONNECT CONNECTION 2 10011 TIME DISTRIBUTION 00100 RESET CONNECTION 1 10100 ROUND-TRIP QUERY 00101 RESET CONNECTION 2 10101 ROUND-TRIP REPLY 00110 COMPEL ACKNOWLEDGE 1 10110 PROBE NODE 00111 COMPEL ACKNOWLEDGE 2 10111 PROBE RESPONSE 01000 COMPEL DATA 1 11000 PASS TOKEN 01001 COMPEL DATA 2 11001 EXECUTE SEQUENCE 01010 EXCHANGE DATA 1 11010 RETURN TOKEN 19
01011 EXCHANGE DATA 2 11011 REQUEST INTERVAL 01100 DATA TRANSFER 1 11100 CLAIM LAS 01101 DATA TRANSFER 2 11101 TRANSFER LAS 01110 DATA TRANSFER 3 11110 WAKE UP 01111 DATA TRANSFER 4 11111 IDLE 3 / HLNS ADR_TABHLNS[13:0] 0x18-0x19 HLNS NODE_ID 0x1B 8BIT NODE ID DMA 0 STATUS0 0x1C 0 FF RDRF_STAT RAF_STAT RSDF_STAT REF_STAT REDF_STAT FCSF_STAT TIF_STAT TDRE_STAT RDRFT_STAT RECEIVE DATA REGISTER FULL RDRF_STAT 1 RAF_STAT RECEIVE ACTIVE FLAG CD RAF_STAT 1 RSDF_STAT RECEIVE START DELIMITER FLAG RSDF_STAT 1 REF_STAT RECEIVE ERROR FLAG REF_STAT 1 REDF_STAT RECEIVE END DELIMITER FLAG REDF_STAT 1 FCSF_STAT FRAME CHECK SEQUENCE FLAG RIF_STAT 1 TIF_STAT TRANSMIT IDLE FLAG TIF_STAT T 1 CPU TDRE_STAT TRANSMIT DATA REGISTER EMPTY TDRE_STAT 1 1 STATUS1 0x1D 1 HL_STAT NS_STAT RNAF_STAT RPSAF_STAT RFCF_STAT ETDF_STAT AMOF_STAT RBMF_STAT HL_STAT HIGH LINK FLAG HLNS NS_STAT NODE SELECT FLAG NS RNAF_STAT RECEIVE NODE ADDRESS FLAG NODE ID 20
RPSAF_STAT RECEIVE PSA FLAG PSA RFCF_STAT RECEIVE FRAME CONTROL FLAG FCF_STAT 1 ETDF_STAT END OF TABLE DETECTION FLAG ETOF_STAT 1 AMOF_STAT ADDRESS MATCH OCCURENCE FLAG AMDF_STAT 1 RBMF_STAT RECEIVE BROADCAST MESSAGE FLAG BMDF_STAT 1 2 STATUS2 0x1E 2 RSPF_STAT LTAF_STAT 0 LCD_STAT MDERR_STAT LNGFRM_STAT LEDF_STAT LSDF_STAT RSPF_STAT REVERSED SIGNAL POLARITY FLAG LTAF_STAT LOOKUP TABLE ACTIVITY FLAG LCD_STAT LOST CARRIER DETECTION CD LCD_STAT 1 LNGFRM_STAT LONG FRAME LNGFRM_STAT 1 MDERR_STAT MANCHESTER DECODE ERROR N+ N- MDERR_STAT 1 LEDF_STAT LOST END DELIMITER FLAG LEDF_STAT 1 LSDF_STAT LOST START DELIMITER FLAG LSDF_STAT 1 TIMER_LATCH 0x1f 1/32MS MS1_32CNT[15:0 0x20-0x21 1/32MS 1/32MS 1/32MS MS1_32COMP[15:0] 0x20-0x21 1/32MS 1/32MS 1MS MS1_CNT[15:0] 0x22-0x23 1MS 1MS 1MS MS1_COMP[15:0] 0x22-0x23 1MS 1MS OCTET_CNT[15:0] 0x24-0x25 21
OCTET_COMP[15:0] 0x24-0x25. TQFP44 6 22
4 23
. 1-65~150-40~85-40~85 2 5 FBC0409