2005 3 13
Introduction Circuit and system representation Design strategies
Introduction Circuit and system representation Design strategies
Four Phases in Creating a Chip This Lecture Other Lecture Other Lecture Other Lecture [Adapted from Main Srivastava. Copyright 2003
Designing a IC Chip Goal is to Reduce complexity Increase productivity Increase chances of a working chip
Designing a IC Chip Choice driven by economics! Economic viability affected by design time Design time affected by the efficiency of architecture logic/memory circuit layout
Designing a IC Chip Key is the use of constraints and abstractions help automate the procedure by simplifying the problem Constraints different types of constraints and trade-offs Performance (speed, area, power) Size of die (hence cost of die and packaging) Time of design (hence cost of engineering & schedule) Easy of test generation and testability Abstractions Collapse detail and arrive at a simpler problem to deal with
Introduction Circuit and system representation Behavioral Structural Physical Design strategies
Circuit and system representation Highly automated techniques now exist for taking very high level descriptions of system behavior and converting the description into a form that eventually may be used to specify how a chip is manufactured A design is expressed in terms of the three distinct design domain: Behavioral Specifies what a system does Structural Specifies how entities are connected together to perform the prescribed behavior Physical (geometrical) Specifies how to actually build a structure that has the required connectivity to implement the prescribed behavior
Levels of Design Abstractions Each design domain may be specified at a variety of levels of abstraction System/Algorithmic Module or functional block Logical Circuit Device etc.
Levels of Design Abstractions SYSTEM MODULE + GATE CIRCUIT V in V out S n+ G DEVICE D n+ 2005-3-16 Adapted from Irwin & Nayaranan s jmlai Slides from PSU. Copyright 2002 J. Rabaey et al.
Design Methodology Design process traverses iteratively between behavior, structure, and geometry EDA tools providing more and more automation
Content Introduction Circuit and system representation Behavioral Structural Physical Design strategies CMOS chip design options Design method
Behavioral representation HDL Behavior Boolean equations Table of input and output values Algorithms written in standard high level computer languages C C++ or HDL Languages
Verilog HDL
Verilog HDL
Verilog HDL
( ) :
Behavioral representation (contd.) HDL for the carry function(co): module carry (co,a,b,c); // output co; // input a,b,c; // assign co=(a&b) (a&c) (b&c); endmodule
Content Introduction Circuit and system representation Behavioral Structural Physical Design strategies
Structural representation Level of abstraction include RTL (register Transfer Level) (Gate Level) (Switch Level) (Circuit Level)
Four-bit Adder
Example Structural representation The cascading of 1-bit adders to form 4-bit adder: module add4(s,c4,ci,a,b); input[3:0] a,b;// 4 4 input ci; output [3:0] s; output c4; wire[2:0] co; // add a0 (co[0],s[0],a[0],b[0],ci); add a1 (co[1],s[1],a[1],b[1],co[0]); add a2 (co[2],s[2],a[2],b[2], co[1]); add a3 (c4,s[3],a[3],b[3], co[2]); endmodule
Example Structural representation (contd.) module add(co,s,a,b,c); input a,b,c; output s,co; sum s1 (s,a,b,c); carry c1(co,a,b,c); endmodule module carry(co,a,b,c); input a,b,c; output co; wire x,y,z; and g1(x,a,b); and g2(y,a,c); and g3(z,b,c); or g4(co,x,y,z); endmodule
module carry (co, a, b, c); input a, b, c; output co; wire il, i2, i3, i4, i5, i6; nmos nl (i3, i4, a); nmos n2 (i4, vss, b); nmos n3 (i3, i5, b); nmos n4 (i5, vss, c); nmos n5 (i3, i6, a); nmos n6 (i6, vss, c); nmos n7 (co, vss, i3); pmos pi (il, vdd, a); pmos p2 (i2, il, b); pmos p3 (i3, i2, c); pmosp4 (il, vdd, b); pmos p5 (i2, il, c); pmos p6 (i3, i2, a); pmos p7 (co, vdd, i3); end module / / /
module carry (co, a, b, c); input a, b, c; output co; wire il, i2, i3, i4, en; nmos nl (il, vss, a); nmosn2 (il, vss, b); nmos n3 (cn, il, cn); nmos n4 (i2, vss, b); nmos ns (cn, i2, a); pmospl(i3,vdd,b);. pmos p2 (cn, i3, a); pmos p3(cn, i4, c); pmos p4 (i4, vdd, b); pmos p5 (i4, vdd, a); pmos p6 (co, vdd, cn); pmos n6 (co, vss, cn); end module
Introduction Circuit and system representation Behavioral Structural Physical Design strategies
Physical representation
4 module add4; input a [3:0], b[3:0]; input ci; output s [3:0], outpu c4; boundary [0, 0, 100, 400]; port port a [0] aluminum width=l origin =[0, 25]; port b [0] aluminum width=l origin =[0, 75]; port ci polysilicon width=l origin =[50, 0]; port s[0] aluminum width=l origin =[100, 50]; add ao origin=[0,0] add a1 origin=[0,100] end module
Simplified Flow
Introduction Circuit and system representation Design strategies Hierarchy Regularity Modularity Locality
Design Strategies
Design Strategies Hierarchy Divide a module into submodules and then repeating this operation on the submodules until the complexity of the smaller parts becomes manageable Regularity Means that the hierarchical decomposition of a large system should result in not only simple, but also similar blocks, as much as possible. Modularity Means that the various functional blocks which make up the larger system must have well-defined functions and interfaces Locality Ensures that connections are mostly between neighboring modules, avoiding long-distance connections as much as possible
Content Introduction Circuit and system representation Design strategies Hierarchy Regularity Modularity Locality
Hierarchy Divide a module into submodules and then repeating this operation on the submodules until the complexity of the smaller parts becomes manageable Hierarchy can be there in all domains Behavior, structural, physical The hierarchy in different domains may not correspond e.g. a structural hierarchy may not map well to physical
Example of Structural Hierarchy a four-bit adder circuit, showing the hierarchy down to gate level
Structural Representation module add4(s,c4,ci,a,b); input[3:0] a,b; input ci; output [3:0] s; output c4; wire[2:0] co; add a0 (co[0],s[0],a[0],b[0],ci); add a1 (co[1],s[1],a[1],b[1],co[0]); add a2 (co[2],s[2],a[2],b[2], co[1]); add a3 (c4,s[3],a[3],b[3], co[2]); endmodule
Structural Representation (contd.) module add(co,s,a,b,c); input a,b,c; output s,co; sum s1 (s,a,b,c); carry c1(co,a,b,c); endmodule module carry(co,a,b,c); input a,b,c; output co; wire x,y,z; and g1(x,a,b); and g2(y,a,b); and g3(z,a,b); or g4(co,x,y,z); endmodule
Example of Physical Hierarchy a four-bit adder in physical description domain describes the external geometry of the adder the locations of input and output pins
Layout of a 16-bit adder, and the sub-blocks of its physical hierarchy
Physical layout of the triangle generator chip
Hierarchy Hierarchy breaks a system into submodules But this may not solve the complexity problem There may not be any regularity in the subdivision We just end up with a large # of different submodules
Content Introduction Circuit and system representation Design strategies Hierarchy Regularity Modularity Locality
(Regularity) Regularity helps in many ways Correct by construction Reuse of design Simplify verification of correctness
(Regularity)
Circuit-level Regularity Example (a) A 2-1 Mux (b) D-type edge triggered flipflop (c) One-bit full add All designed using inverters and tristate buffers
Content Introduction Circuit and system representation Design strategies Hierarchy Regularity Modularity Locality
Modularity PLA
Modularity (contd.) Bad use: Use of transmission gates as inputs Internal signals now depend on source impedance Dynamic CMOS logic but fail to latch or register the inputs Because external inputs might arrived at various times with respect to the time.erroneous results might occur unless the timing of each input is individually checked
Example of Poor Modularity
Content Introduction Circuit and system representation Design strategies Hierarchy Regularity Modularity Locality
Locality Ensures that connections are mostly between neighboring modules, avoiding long-distance connections as much as possible Modules see a common clock,and hence synchronous-timing methods apply Critical paths, if possible, should be kept within module boundaries. Ensuring time locality is first to pay attention to the clock generation and distribution network Placement so that global wiring is minimized
1bit sum CMOS
Acknowledgement This lecture note has been summarized from lecture note on Introduction to VLSI Design, VLSI Circuit Design all over the world. I can t remember where those slide come from. However, I d like to thank all professors who create such a good work on those lecture notes. Without those lectures, this slide can t be finished.