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1 微算機原理與實驗 (UEE 2301/1071 ) Chap 5. MCS-51 Addressing Modes 宋開泰 Office:EE709 Phone: ( 校內分機 :31865) ktsong@mail.nctu.edu.tw URL: 1

2 Addressing Modes Addressing mode is the way the assembler determines the effective address of the operand of an instruction. For 8051, there are 8 addressing modes: Direct Indirect Register Immediate Relative Absolute Long Index 2

3 Direct Addressing Mode ( 直接定址法 ) 1). 運算元 (operand) 之 address 直接寫在指令上 2). Example : MOV A, 66H ;(A) (66H) 3). 適用範圍 : (1). Internal Data Memory : Byte address 00H ~ 7FH MOV A, 66H (2). SFR : 20 bytes (8051) or 25 bytes (8052) 80H ~ F0H MOV A, 89H ;89H is TMOD register (3). Internal Data Memory : Bit address 00H~7FH SETB 23H (4). SFR : Bit address 80H~F8H SETB CPL C C 3

4 Indirect Addressing Mode ( 間接定址法 )(1/4) 1). 以暫存器 R0, R1, SP or DPTR 儲存運算元位址, 即欲存取之資料的位址不直接寫在指令中, 而是事先存放於特定的 Register 中 2). 當間接定址用之 Register 出現在指令時, MOV R0, # 50H MOV ;(A)=(50H) 4

5 Indirect Addressing (2/4) 3). 適用範圍 : (1). Internal Data Memory 來儲存位址 MOV ;(A)=(50H) (2). Stack : 以 SP 來儲存位址 POP 30H (3). External Data Memory A (4). Internal Data Memory 的 lower 4 bits (b3~b0) 來儲存位址 XCHD 5

6 Indirect Addressing(3/4) 以暫存器 R0, R1, SP, DPTR 儲存運算元位址, 欲存取之資料位址不直接寫在指令中間接定址用之 Register 符號 MOV 41H 40H 3FH 3EH 32H 31H 30H 55H 01H 23H 20H if R1 中為 40H, 而 internal memory address 40H 中有 data 55H, 則 (A) (40H) A=55H stack, 以 SP 來儲存位址 POP POP DPH DPL Stack(Internal RAM) SP 30H Data pointer 0123H POP SP stack pointer 20H 先是 2FH, 再 20H 6

7 PUSH PUSH Operation SP contains 09H Indirect Addressing (4/4) DPL Data pointer: 0123H DPH (SP) (SP)+1 ((SP)) (direct) Stack pointer set to 0BH 23H (0AH) 01H (0BH) 0BH 0AH SP 09H 01H 23H XX 7

8 Register Addressing Mode ( 暫存器定址法 ) 1). 將欲存取之 Register 直接寫在指令中 2). Example : MOV A, R0 ;(A)=(R0) 3). 適用之 Register: (1). 4 組 Register Banks : R0~R7 ADD A, R5 (2). A, B, AB, DPTR : INC A MUL AB INC DPTR 8

9 [ 比較 ] 下列二個指令作用相同 MOV A, R7 ;Register addressing, ;Machine code : 1 byte (6E) MOV A, 07H ;Direct addressing, ;Machine code : 2 bytes (E5 06) 9

10 Immediate Addressing Mode ( 立即定址法 ) 1). 欲存取之資料直接寫在指令中, 其前面有一 # 2). Example : MOV A, #36H ;(A)= 36H ADD A, #24H ;(A)=(A)+24H 10

11 用在 jump instructions. Relative addressing 8-bit signed offset -128~+127 SJMP THERE(assembled into address 1000H) THERE Represents an instruction at location 1040H 而 SJMP THERE 在 1000H 及 1001H. The assembler will assign a relative offset of 3EH as byte 2 of the instruction. position independent code 1040H-1002H=3EH (PC) (PC)+2 (PC) (PC)+byte_2 11

12 Calculating the Offset 12

13 ACALL; AJMP; Absolute addressing Absolute Call Absolute Jump within the 2K page of the current code memory Upper 5bits determine the 2K page address A15 Current page A11 A10 11-byte 2Kpage (00001) F 4 6 H A0 11 bits determine the address within a 2K page Page 31 Page 1 Page H 0FFFH 0800H 07FFH 0000H 13

14 Memory map of pages 14

15 ACALL and AJMP 2-byte instruction AJMP st byte(a10~a8+opcode) ACALL nd byte(a7~a0) page31 2K page page0 17FFH 1000H An ACALL instruction is in memory locations 1024H and 1025H, The subroutine to which the call is directed begins in memory location 17A6H, what are the machine language bytes for the ACALL instruction? Solution: F1A6H 15

16 Determine the Address ACALL; Absolute Call, unconditionally calls a subroutine AJMP; Absolute jump Within the 2K page of code memory Upper 5 bits determine the 2k page A15 A11 A10 A0 不變 11-bit 2K page AJMP THERE nd Byte The label THERE represents an instruction at address 0F46H. 11 bits determine the address within a 2k page 111(00001) 1 st Byte 16

17 Long addressing LCALL LJMP 3-byte instructions, 16-bit addressing as bytes 2 and 3. 64K space LJMP 8AF2H The Assembler allows programmer to use generic JMP or CALL mnemonic. JMP SJMP AJMP CALL ACALL LCALL LJMP 17

18 Index Addressing(used in lookup tables)(1/3) 1) uses a base register( 基底暫存器 ), initialized to the beginning of the table) PC or DPTR(data pointer) 2) Use the Accumulator A as an offset. A : index register, ( 索引暫存器 ) MOVC 3) look-up table 只能讀, 不能寫 ( 只有用在程式記憶體 ) 18

19 Index Addressing(2/3) 基本型式 : MOV A, #ENTRY_NUMBER CALL LOOK_UP LOOK_UP: INC A MOVC RET TABLE: DB data, data, data, 例 1. REL_PC INC A MOVC RET DB 66H DB 77H DB 88H DB 99H A=01H A=77H 19

20 例 2. Index Addressing(3/3) SQUARE: INC A MOVC RET TABLE: DB 0, 1, 4, 9, 16, 25, 36, 49, 64, 81 如果不用 Look-up table SQUARE: MOV A, #6 CALL SQUARE PUSH 0F0H MOV MUL POP RET 0F0H, A AB 0F0H 20

21 8051 addressing modes 21

22 MCS-51 Common-cathode

23 Lab #2 7-Segment Display 撰寫一個倒數計時器程式, 程式啟動後會在七段顯示器上從 0 倒數至 9, 再從 9 倒數至 0, 間隔時間為 1 秒, 循環顯示 23

24 Sample program ORG 00H JMP START ORG 50H START: MOV A,#10 MOV DPTR,#TABLE LOOP: SHOW: PUSH A DEC A MOVC A,@A+DPTR MOV P1,A ACALL DELAY POP A DJNZ A,SHOW JMP START

25 DELAY: MOV R2,#10 D1: MOV R0,#250 D2: MOV R1,#250 DJNZ R1,$ DJNZ R0,D2 DJNZ R2,D1 RET TABLE: DB B, B, B, B ;O-3 DB B, B, B, B ;4-7 DB B, B, B, B ;8-C DB B, B, B, B ;D-F END

26 Lab#2 Part II - Four 7-Segment Display 7447: BCD- to 7 segment decoder IC

27 IC-7447 由於 7SEG 4 實驗模組已經內建 BCD to 7 SEG 解碼 IC 7447, 這顆 IC 可將 BCD 碼轉換為對應七段顯示器的顯示碼 LCD, 7SEGx4 Display(F9)

28 7-Segment Display MCS-51 Commoncathode

29 7447: BCD-to-7 segment decoder IC 29

30 Port connection Vcc Vcc Vcc Vcc Common-anode

31 實驗原理透過 8051 I/O port high-order nibble 送出位置控制碼, 使得程式可以控制要在哪一個七段顯示器上顯示出數字 8051 I/O port low-order nibble 輸出 BCD 碼以顯示數字如何讓四顆 7 段顯示器看起來同時亮? 由於此 IC 一次只能讓一顆 7 段顯示器作用, 因此我們必須快速的讓四個 7 段顯示器輪流顯示, 每次顯示約 1/10 秒 ( 視覺暫留時間 )

32 位數控制顯示的數字 1110 # # # #4

33 腳位對照使用 JP05 (1)Pin 腳由左到右依序是 1~8 (2)1~4( 紅色 ) 控制數字 (3)5~8( 橘色 ) 控制位數

34 DEMO 項目 (1) 請撰寫一個程式, 使得四個七段顯示器能夠顯示出 1357 (2) 請撰寫一個程式, 使得四個七段顯示器從 0 數到 200, 每間隔 0.25 秒加 10, 直到 200 並停留在顯示 200

35 35 ORG 00H AJMP MAIN ORG 50H MAIN: MOV R2,#00H LOOP: MOV P0,#FFH MOV A,R2 MOV DPTR,#SSTABLE MOVC MOV P0,A ACALL DELAY INC R2 CJNE R2,#4,LOOP AJMP MAIN SSTABLE: DB E5H,D6H,B7H,78H DELAY: MOV R6,#10H DL1: MOV R7,#10H DJNZ R7,$ DJNZ R6,DL1 RET END

36 DEMO1 參考流程圖

37 從 199 數到 0 參考流程圖請撰寫一個程式, 使得四個七段顯示器從 0 數到 199, 每間隔 0.25 秒加 1, 直到 199 再回數到 0

38 結報在結報中試說明 DEMO2 中如何處理進位以及借位的問題

DPJJX1.DOC

DPJJX1.DOC 8051 111 2K 1 2 3 ' ' 1 CPU RAM ROM / A/D D/A PC CPU 40 68 10 20 8 51 PIII 8051 2 MCS51 8051 8031 89C51 8051 8031 89C51? MCS51 INTEL INTEL 8031 8051 8751 8032 8052 8752 8051 8051 8051 MCS51 8031 8031