Atmel AVR SoC FPSLIC FPSLIC, FPSLIC System Designer 3.0, AVR FPGA FPGA Atmel FPSLIC AT- STK94, FPSLIC, SoC, (CIP) A VR SoC FPSLIC /. :, ISBN 7 8

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1 A V R SoC FPSLIC /

2 Atmel AVR SoC FPSLIC FPSLIC, FPSLIC System Designer 3.0, AVR FPGA FPGA Atmel FPSLIC AT- STK94, FPSLIC, SoC, (CIP) A VR SoC FPSLIC /. :, ISBN T P368.1 CIP (2004) AVR SoC FPSLIC * 37 ( ) : ( 010 ) : ( 010 ) / w ww.bua apress.com.cn E- mail: b hp et * :787 mm mm 1/ 16 : : : ISBN : 32.00

3 ,, SoC( System on Chip ) SoC, 21,,, SoC ( System on Chip ),, SoC,, PDA,, SoC, SoC,, SoC, SoC A tmel F PSLIC ( Field P rogrammable System Level Integrated Circuit, ) AT94K, AVR FPG A SRAM, SoC FPSLIC Syst em Designer,, F PSLIC, FPSLIC 7 1 FPSLIC, F PGA AV R, F PGA A VR 2 FPSLIC, 3 FPSLIC System Designer FPSLIC A VR 5 6 FPSLIC FPGA, FPG A, V H DL 7 FPSLIC, A tmel FPSLIC ATSTK94, FPSLIC,,

4 ATMEL A T89C51 A VR FPSLIC ( Field P rogrammable System Level Integrated Circuit )?,,, SoC( Sytsem on Chip) 21,, :, SoC A TMEL F PSLIC FPSLIC : AVR FPGA FPSLIC AV R A VR, FPGA, A VR FPG A 5K 40K, CP LD, FPSLIC FPSLIC FPGA,, ; FPSLIC,, : A VR FPG A,, ( A VR CPLD) FPSLIC,,, ATMEL,,,,,,,, ATMEL,,,,, F PSLIC ( AT MEL)

5 ATMEL ASIA LIMITED 1219 T E L: F AX : ( ) 70,710 : : 8125 T EL : F AX: ( ) : : :

6 , IC, SoC I P CORE IC SoC,, IC, SoC 3 : 3, ASIC,, ASIC, ASIC, IP ( NRE),, ASIC,,,, SoC,,, DSP,, FPGA FPGA, SoC IP IP, FPG A,,, F PGA 6, FPGA 60!,, FPG A ASIC, ASIC;,, F PGA FPG A SoC, ASIC, FPGA,, ( SoC ), IC,, ASIC NRE, ASIC, FPGA, SoC, IC SoC Atmel 1999 RISC FPSLIC ( Field P rogramma-

7 2 AVR SoC FPSLIC ble System Level Integrat ed Circuit Xilinx Altera,, IC, ASIC A tmel SoC, Internet, Atmel SoC ( PDA) M P3 GPS, ( Internet, / ), F PSLIC ( 5 ) F PSLIC, Atmel 2002, FPSLIC SRAM IP SRAM I P, A tmel ( ISP ),,,,, A tmel FPSLIC : A tmel FPSLIC SoC 8 A VR, 36 KB SRAM 4 FPGA 2 U ART 1 3 / AVR SRAM, 25 M Hz 20 MI PS / F PSLIC, A VR,

8 3 F PSLIC 100 A, 2 3 ma/ MHz ASIC, FPG A, F PSLIC SoC FPGA Atmel AT40K FPGA FPGA, F PSLIC,, SoC C, H DL ( H ardware Description Language) EDA,, FPGA H DL, H DL, SoC, C Atmel System Designer A VR, H DL,, AVR C C :

9 4 AVR SoC FPSLIC SoC ASIC SoC,, SoC ASIC, F PGA EDA C, HDL FPSLIC, Atmel EE PROM, PCB /, F PSLIC 2002, Atmel AVR J TAG FPSLIC FPSLIC FPGA ( Co - verifica tion) FPG A,, JTA G Atmel m SPI FPSLIC ( FPSLIC II) F PSLIC F PSLIC II 20 % 40 %, FPGA , A VR 40 M Hz 2005, A tmel 0.13 m FPSLIC III A VR 60 MHz, FPGA FPSLIC III

10 1 FPSLIC AT94K 1.1 AT94K FPGA F PGA F reeram F PGA / FPGA/ A VR F PGA/ AVR SRAM F PGA SRAM A VR A VR Cache F PGA/ AVR AVR A VR A VR A VR A VR F PGA A VR A VR A VR JTA G OCD / U AR T I/ O 83 2 System Designer System Designer 92

11 2 AVR SoC FPSLIC License License A VR / C FPG A V HDL A VR F PGA F PGA System Designer AVR 4.1 AVR Studio A VR Studio A VR Studio AVR System Designer A VR Design A VR Studio AVR

12 3 FPGA System Designer FPGA V H DL V HDL V HDL V HDL V HDL System Designer FPGA System Designer System Designer ModelSim 5.6e ModelSim V H DL V HDL System Designer Figaro Figaro

13 4 AVR SoC FPSLIC System Designer A VR Studio A VR Studio ModelSim AVR FPGA A VR F PGA A VR F PGA A VR F PGA A VR F PGA A VR F PGA A VR F PGA EE PROM FPSLIC F PSLIC ATST K ATSTK A TS TK System Designer 3.0 (Service pack Level 3)

14 FPSLIC AT94K SoC, Atmel RISC FPSLIC( Field Programmable System Level Integrated Circuit) AT94K, F PGA ;,, SoC ( System on Chip) FPG A FPGA/ A VR A VR F PSLIC 1.1 AT94K Atmel AT 94K 1.1.1, Atmel 0.35 m( AL) 0.18 m( A X) 5 CMOS Atmel AT40K SRAM F PGA, A tmel 8 RISC A VR, SRAM AT94K

15 2 AVR SoC FPSLIC AT40K FPGA SRAM, 3.3 V PCI, 10 ns SRAM 8, Cache Logic ( ), FPG A AT94K A VR,, 1 M PS/ MHz, A VR RISC, 32, ALU ;,, 2,, CISC 10 AVR SRAM, F PGA SRAM A VR SRAM A tmel EEPROM A T17 A T94 FPSLIC : : SRAM AT40K FPGA RISC A VR SRAM J TAG ICE SRAM FPG A, F reeram : FPGA 2K 18.4K / SRAM ; DSP FPGA ; A VR FPG A, Cache Logic ;, A VR : ;, DSP ; 1 MI PS/ MHz ; C, 32 8 ; ; 100 A, 2 3 ma/ MHz 36 KB SRAM: SRAM 16K 16, 15 n s; SRAM 16K 8, 15 ns IEEE J TAG : ; J TAG ( AV R ) VR : I 2 C 2 ; 2 UAR T ; 2 PWM 8 / ; PWM 16 /

16 1 FPSLIC AT94K 3 FPG A : A VR AVR 16 FPG A ; FPGA F PGA AVR 16 A VR 4 F PGA : 2 FPG A AVR ; FPGA : ; A VR ; ; / VCC : V 3.3 V 33 MHz PCI FPG A I/ O : / 20 ma I/ O ; FPGA I/ O 0.35 m CMOS 5 A VR FPG A A T94K AT94K A T 94K05 A T 94 K10 A T 94 K40 F PG A F PG A ( Cell) F PG A SRA M/ F PG A ( ) F PG A I/ O A VR I/ O SR AM/ KB SR AM/ KB ( 8 ) 2 U AR T / JT AG ICE A VR 25 M Hz / MI PS 40 M Hz / V A L AX

17 4 AVR SoC FPSLIC FPGA A tmel AT94K A tmel SRAM FPGA A T40K AT40K ( DSP/ ), F IR FF T ( DCT ),, / AT40K : 1) SRAM A T40K SRAM 10 ns, RAM,, Atmel, RAM ( FI FO ) 2) AT40K 8,,, AVR Cache Logic,, 3) Cache Logic, AT40K F PGA Cache Logic (, ),,,,, AT40K F PGA FPSLIC 4) A T40K,, FPG A, ;,,, FPGA A T40K,, A tmel FPGA AT40K,, 1. F PSLIC 1.2.1, 4, RAM,, RAM,

18 1 FPSLIC AT94K FPGA, 5, 3 : , 8,,,,, ; ( a) FPGA ( b ) 5 5 ( 1 ) 5 ( 1 )

19 6 AVR SoC FPSLIC

20 1 FPSLIC AT94K 7. A T40K FPG A 1.2.4, Vn n ; Hn n Vn Hn 2, Vn H n , 5, DSP/ /, FPG A ; F PSLIC System Designer 3.0 IDS, 1.2.4

21 8 AVR SoC FPSLIC FreeRAM FPSLIC RAM 2 : F PGA F reeram A VR/ FPG A SRAM SRAM 1.3, FPGA FreeRAM 1.2.6, 32 4 F reeram FPGA, ( Sector ) ( 1 ) ; ( 2 ) ; 5 5 ( 3) ; 5 5 RAM, WAddr RAddr, RAM, RAddr WAddr ; RAM, WAddr RAddr RAM RAM, WAddr /, Din ( ), RAM F reesram, WE OE V1 V2 2 WAddr RAddr WE OE

22 1 FPSLIC AT94K 9 FPGA SRAM ( RAM ) 32 4 RAM /,, Load, ; RAM ( ), Load 1, WE 0, Data ; ( ), Load 0, WE 1, Data, Clock, 1 Clock RAM, RAM ( RAM Clear Byte) RAM,, RAM,, ; RAM

23 10 AVR SoC FPSLIC FPGA / FreeSRAM F PGA 8, 6 ( ), 2 ( 5 6) A VR 1. AVR 1.2.8, F PGA 8 2 ( GCK5 GCK6 ) AV R, GCK5 A VR ; GCK6 AVR A VR, AVR FPGA GCK5 GCK6 AVR XTAL, AVR GCK5( GCK6 ) ; GCK5 ( GCK6)

24 1 FPSLIC AT94K 11 TOSC GCK, A VR GCK6 ; GCK6 GCK6, AVR, GCK GCK5 GCK6 X T A L T OSC WD T X T A L T OSC WD T X T A L T OSC WD T 2. F PGA 8 5 6,, F PGA, FPGA, , 2 ( FCK1 FCK2 ), I/ O ( 4 ), 4,, 4, ,, / I/ O /, / /, 4 /, 5 / / 5,, 4 / / /, 1, FPGA 1.2.2, FPSLIC System Designer 3.0

25 12 AVR SoC FPSLIC / F ree RAM 2 F ree RAM 1 RA M RA M

26 1 FPSLIC AT94K F ree RAM 1 RA M F ree RAM 1 5 F ree RAM 2 4 / FPGA/ AVR F PSLIC F PGA A VR, : PGA AVR 15 ns RAM A VR F PGA, FPGA A VR I/ O FPG A F PGA 16 F PGA AVR 16, AVR FPGA, ( Cache Logic) FPGA/ AVR 1.3.1, A VR F PGA 16 ( AT94K05 8 ), AVR 4, F PGA AV R 8, F PGA AVR 16 ( AT94K05 8 ), F PGA AVR F PSLIC System Designer SRAM FPGA AVR F PGA AVR 36 KB SRAM, 15 n s, A VR

27 14 AVR SoC FPSLIC SRAM FPGA AVR SRAM 8, F PGA SRAM A T94K10 A T94K40 / SRAM 3 : 10K 16 4K 8 SRAM 6K 16 12K 8 SRAM ;, AT94K05 / SRAM 3 : 4K 16 4 K 8 6 K K 8 SRAM 2 K 16 4 K 8,, SRAM, ( SCR ), F PSLIC SRAM BOOT BLOCK, ; BOOT BLOCK,, A VR FPGA A VR, 0x0000 0x001F ; 0x001F 0 x005f I/ O,, F PGA 0x0000 0x005F FPSLIC SRAM

28 1 FPSLIC AT94K 15 FPGA SRAM 1.3.3, F PGA B SRAM ( SCR63),, FPGA, / /,, Sy st em Designer SRAM SCR63, FPGA, FPG A / A VR /, F PGA,, FMXOR ( SF TCR ) A VR, SCR38 AT40K FPGA SRAM AVR A VR, FPSLIC SRAM 36K 8, 1.3.3, AVR A ; DBG, AVR S T LD B,, ( n 2 ) K 8 n 2K 8, SRAM0 SRAMn ( SRAM, AVR PC / ) 1. A A 16 0x0000 SRAM n - 1 n, SRAM ( n - 1 ), SRAMn : SCR41 = 0, SCR40 = 0, 0x2800 0x3FFF ; SCR41 = 0, SCR40 = 1, 0x2800 0x37F F;

29 16 AVR SoC FPSLIC SCR41 = 1, SCR40 = 0, 0x2800 0x2FFF ; SCR41 = 1, SCR40 = 1,, SRAM2/ 3, SRAM6/ 7, SRAM 2 7 ( 16K 16 ) AVR SRA M 0x3F F F 0 x3800 0x3F F F 0 x3800 0x37 F F 0x3000 0x37 F F 0x3000 0x2F F F 0 x2800 0x2F F F 0 x2800 0x2F F F 0 x2000 0x2F F F 0 x2000 0x1F F F 0 x1800 0x1F F F 0 x1800 0x17 F F 0x1000 0x17 F F 0x1000 0x0F F F 0 x0800 0x0F F F 0 x0800 0x07 F F 0x0000 0x07 F F 0x CR41 40 = 00 C R41 40 = 00, 01 CR41 40 = 00, 01, 10 AV R AV R AV R AV R AV R AV R AV R AV R AV R AV R 8 SRAM0 : SCR41 = 0, SCR40 = 0, ; SCR41 = 0, SCR40 = 1, 0x1000 0x1FFF ; SCR41 = 1, SCR40 = 0, 0x1000 0x2FFF ; SCR41 = 1, SCR40 = 1, 0x1000 0x3FFF, SRAM7, SRAM2,, SRAM0 7( 16K 8 ) AVR SRA M 0x07 F F 0x0000 0x07 F F 0x0800 0x17 F F 0x1000 0x1F F F 0 x1800 0x27 F F 0x2000 0x27 F F 0x2800 0x37 F F 0x3000 0x3F F F 0 x A VR / A VR / CR41 40 = 11, 10, 01 C R41 40 = 11, 10 CR41 40 = 11

30 1 FPSLIC AT94K 17 B B, 36 KB F PGA/ B, DBG, AVR S T LD B, AVR ( ST 1.3.4, LD 1.3.5), SF TCR (0 x3a/ 0x5A) 1 DBG SCR36 SCR37, AVR AVR SRAM ST AVR SRAM LD, F PGA / AVR /, FPGA AVR B, SF TCR (0x3A/ 0 x5a) 3 F MXOR SCR63 F MXOR FPG A SRAM SCR63 SCR63 0, F MXOR FPG A SRAM ; SCR63 1, F MXOR F PGA SRAM A VR F MXOR 0 F PGA ( AV R ) 36K 8, A VR FRAME ( AV R ) /, 2K 8 A VR F PGA A VR F PGA 16 8, 1.3.3, SRAM SCR40 SCR41

31 18 AVR SoC FPSLIC AVR FPGA SARM SRAM F P GA AVR DBG AVR A VR PC 00 0x0000 0x07 F F 0x x07f F 01 0x0800 0x0F F F 0x0800 0x0 F F F 02 0x1000 0x17 F F 0x x17f F 0x x3 F F F ( LS ) 03 0x1800 0x1F F F 0x1800 0x1 F F F 0x3800 0x3F F F ( M S ) 04 0x2000 0x27 F F 0x x27f F 0x3000 0x37 F F ( LS ) 05 0x2800 0x2F F F 0x2800 0x2 F F F 0x3000 0x37 F F ( MS ) 06 0x3000 0x37 F F 0x x37f F 0x x2 F F F ( LS ) 07 0x3800 0x3F F F 0x3800 0x3 F F F 0x2800 0x2F F F ( M S ) 08 0x4000 0x47 F F 0x2000 0x27 F F ( LS ) 09 0x4800 0x4F F F 0x2000 0x27 F F ( MS ) 10 0x5000 0x57 F F 0x x1 F F F ( LS ) 11 0x5800 0x5F F F 0x1800 0x1F F F ( M S ) 12 0x6000 0x67 F F 0x1000 0x17 F F ( LS ) 13 0x6800 0x6F F F 0x1000 0x17 F F ( MS ) 14 0x7000 0x77 F F 0x x0 F F F ( LS ) 15 0x7800 0x7F F F 0x0800 0x0F F F ( M S ) 16 0x8000 0x87 F F 0x0000 0x07 F F ( LS ) 17 0x x8 F F F 0x0000 0x07 F F ( MS ), FRAME( AVR ), AVR PC FRAME F rame F ra me 77F E AVR PC 77 F F FE AV R PC F FE 9B28 0 F F F C FF E 7F FE 7F F F 9B CF 1000 B A B A

32 1 FPSLIC AT94K 19 A VR AVR Cache F PGA SRAM,, AVR SRAM AV R Cache Logic I/ O 1.3.6, FPGAX FPGA Y FPG AZ FPGA, F PGAD FPG AX FPG AY FPGAZ FPGA A VR Cache Logic A VR A VR Cache F PGA CH ECK A VR U ART, FPGA, A VR, F PGA FPGA/ AVR 1. A T94K 4, 1.3.6, M0 M M2 M , 0 1 1,, Cac he( SR AM ) 4, 2 3 AT40K, 0 1 2, AVR I/ O CH ECK 2. F PSLIC 8 64, FPSLIC, F PGA AV R, FPSLIC 1.3.7, System

33 20 AVR SoC FPSLIC Designer FPSLIC SCR0 SC R1 0 = SCR2 1 = SCR2 I/ O CSO U T SC R2 1, CSO U T 0 0 = SCR3 1 = SCR3 CH ECK SC R3, CH E CK, A VR I/ O 0 = 1 = SCR4 SCR5 SCR4, SCR4, ( CH ECK ) I NI T, CON, SCR4, ;, SCR4 0 = O TS SCR6 SCR7 SC R12 1 = O TS SCR6, O TS ( Output T ri St at e) I/ O I/ O, 0 = CCL K SCR13 SCR14 R15 1 = C CL K SCR13 CCL K 0 ( ) CCL K, I/ O 0 = GCK0 GCK7 1 = GCK0 GCK7 SCR16 SCR23 SC R16 SC R23 GCK, 1 GCK, F P GA 0 = FCK 0 FCK1 1 = FCK 0 FCK1 SCR24 R25 SC R24 SC R25 FCK, 1 F CK, F PG A

34 1 FPSLIC AT94K = OCD( On Chip Debugger) SCR26 1 = OCD( On Chip Debugger) 0 = F PG A I/ O T A P SCR27 1 = F PG A I/ O T A P ID A VR I/ O OCD SC R26, SC R4 0 SCR28 R29 0 = / SCR30 1 = / SCR30 / D EF, / CON 0 = I/ O SCR31 1 = I/ O SCR31 I/ O CO N SCR32 SCR34 SCR35 SCR36 0 = A VR 1 = A VR ( ) 0 = A VR SRA M 1 = A VR SR AM ( ) SCR36 FP GA AV R SCR37 SCR38 SCR39 0 = A VR SRA M 1 = A VR SRAM 0 = ( ) F rame A VR / RA M 1 = A VR / RA M SCR41 = 0, SC R40 = 0 16K 16 / 4 K 8 SCR41 = 0, SC R40 = 1 14K 16 / 12K 8 SCR40 R41 SCR41 = 1, SC R40 = 0 12K 16 / 8 K 8 SCR41 = 1, SC R40 = 1 10K 16 / 16K 8 SCR40 SCR41 AV R / SRAM ( Sys tem Design er A T 94 K ) SCR42 SCR47 0 = EX T I N T0 E4 SCR48 1 = EX T I N T0 IN T P0 SCR48 SCR53 0 = EX T I N T1 E5 SCR49 1 = EX T I N T1 IN T P1 SCR48 SCR53

35 22 AVR SoC FPSLIC = EX T I N T2 E6 SCR50 1 = EX T I N T2 IN T P2 SCR48 SCR53 0 = EX T I N T3 E7 SCR51 1 = EX T I N T3 IN T P3 SCR48 SCR53 0 = UA R T0 E1 E0 SCR52 1 = UA R T0 SCR48 SCR53 0 = UA R T1 E3 E2 1 = UA R T1 SCR53 SCR48 SCR A VR D ; E I/ O, U AR T SCR54 SCR55 SCR56 SCR57 SCR58 R59 0 = A VR D 6 m A 1 = A VR D 20 m A 0 = A VR E 6 ma 1 = A VR E 20 m A 0 = X T A L ( R Feedba ck ) 1 = X T A L ( R Feedba ck ) 0 = T O SC2 ( R Feedback ) 1 = T O SC2 ( R Feedback ) SCR61 = 0, SC R60 = 0 1 SCR61 = 0, SC R60 = 1 A VR SCR60 R61 SCR61 = 1, SC R60 = 0 ( T OSC1) ( ASSR AS2) SCR61 = 1, SC R60 = 1 6 ( Sys tem Design er A T 94K ) SCR62 SCR63 0 = A VR F PG A Cach e Logic 1 = A VR F PG A Cach e Logic 0 = F P GA ( ) SR AM ( FR AM E ) 1 = F P GA ( ) SR AM ( FR AM E ) 1.3.7, FPSLIC 2 1 RESET, F PGA SRAM, A VR 0, 2 AVRReset, FPSLIC A VR 1.4.5

36 1 FPSLIC AT94K 23 AVR AVR A VR A VR RISC 8 CMOS, A VR 1 MIPS/ M Hz, A VR : 16 I/ O ; 32 8 ; RT C; 3 PWM / ( T/ C) ; 2 UA RT ; ; I 2 C 2 ; 3, FPSLIC System Designer 3.0 A VR, C / 1. VCC : GND : D ( PD7 PD0 ) : 8 I/ O, / 6 ma 20 ma,, D, D E ( P E7 PE0) : 8 I/ O, / 6 ma 20 ma,,, E E RX0: U ART0 ( ) TX0 : U ART0 ( ) RX1: U ART1 ( ) TX1 : U ART1 ( ) XTAL1: XTAL2: TOSC1: TOSC2:

37 24 AVR SoC FPSLIC SCL : 2 / SDA : 2 / 2. 1) 1.4.1, XTAL1 XTAL2 2), XTAL2, XTAL1, ) / 1.4.3,, /, ID D, XTAL1 RPD 4) 1.4.4, TOSC1 TOSC k H z 1 MHz,, 0 Hz 1 MHz / AVR A VR ( H arvard ),,,, CPU

38 1 FPSLIC AT94K ),, A VR CPU 32 8, 0x00 0x1F 5 ( SBCI SUBI CPI A NDI ORI), SBCI SUBI CP I ANDI ORI : R16 R31 SBC SUB CP AND OR, 1.4.5,, 32 SRAM,, X Y Z,, FPSLIC 4 16 KB SRAM, 0 x0060, : 4 KB: 8 KB: x0060 0x0FF F 0x0060 0x1FF F 12 KB: 0x0060 0x2FF F 16 KB: 0x0060 0x3FF F : SRAM, 2) X Y Z AVR CPU R26 R31, 3 X Y Z 1.4.5, 3

39 26 AVR SoC FPSLIC A VR ALU ALU 32, ALU ALU 3 : 4) A VR AVR F PSLIC AT94K SRAM, A VR ( SRAM ) ( SRAM I/ O ) 1. SRAM 5 : R26 R31, Y Z 63 X Y Z, 3 ALU I/ O 2. AV R CP U XTAL1, XT AL1, 1.4.6,, CP U, 1 MIPS/ M Hz, CPU / / , ALU 2, SRAM /, SRAM

40 1 FPSLIC AT94K 27 ALU SRAM 3. I/ O A VR I/ O AVR I/ O x3 F ( 0x5 F ) SR E G I T H S V N Z C 0x3 E ( 0x5 E ) S P H S P15 S P14 SP13 SP12 SP11 SP10 SP9 SP8 0x3D ( 0x5D ) S P L SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 0x3C( 0x5C) 0x3B( 0x5B) EI MF IN T F3 IN T F2 IN T F1 I N T F0 IN T3 IN T2 IN T 1 IN T 0 0x3A ( 0x5 A ) S FT CR F MXOR WD TS DBG SRST 0x39 ( 0x59 ) T IM SK T OI E1 OCI E1 A OCI E1B T OIE 2 T ICI E1 OCI E2 T O IE0 OCI E0 0x38 ( 0x58 ) T I FR T O V1 OCF1A OCF1B T OV2 ICF1 OCF2 T OV0 OCF0 0x37 ( 0x57 ) 0x36 ( 0x56 ) TW CR TWI N T TWEA T WST A TWS T O TW WC TWEN TW IE 0x35 ( 0x55 ) MCU R JT R F J T D SE SM1 SM0 P ORF WDRF E X T R F 0x34 ( 0x54 ) 0x33 ( 0x53 ) T CC R0 FOC0 P WM0 COM01 COM00 CT C0 CS02 CS01 CS00 0x32 ( 0x52 ) T CN T 0 / 0 ( 8 ) 0x31 ( 0x51 ) OCR0 /

41 28 AVR SoC FPSLIC x30 ( 0x50 ) S FIOR P SR2 P SR10 0x2 F ( 0x4 F ) T CC R1 A COM1A1 COM1A0 CO M1B1 CO M1B0 F OC1A F OC1B P WM11 PW M10 0x2 E ( 0x4 E ) T CC R1B ICNC1 ICES1 ICPE CT C1 CS12 CS11 CS10 0x2D ( 0x4D ) T CN T 1 H / 1 0x2C( 0x4C) T CN T 1L / 1 0x2B( 0x4B) OCR1A H / 1 A 0x2A ( 0x4 A ) OCR1A L / 1 A 0x29 ( 0x49 ) OCR1BH / 1 B 0x28 ( 0x48 ) OCR1BL / 1 B 0x27 ( 0x47 ) T CC R2 FOC2 P WM2 COM21 COM20 CT C2 CS22 CS21 CS20 0x26 ( 0x46 ) A SSR A S2 T CN20B OC R2 UB T C R2 UB 0x25 ( 0x45 ) ICR1 H / 1 0x24 ( 0x44 ) ICR1 L / 1 0x23 ( 0x43 ) T CN T 2 / 2 ( 8 ) 0x22 ( 0x42 ) OCR2 / 2 0x21 ( 0x41 ) W D TC R W D T OE W DE WDP2 WDP1 WDP0 0x20 ( 0x40 ) UBR R H1 U AR T1 ( 11 8) UA R T0 ( 11 8) 0x1 F ( 0x3 F ) TW DR 2 0x1 E ( 0x3 E ) TW AR 2 0x1D ( 0x3D ) TW SR 2 0x1C( 0x3C) TWB R 2 0x1B( 0x3B) FP GA D F PG A Cac he ( D7 D0 ) 0x1A ( 0x3 A ) FP GA Z F PG A Cac he Z ( T3 T0 ) ( Z3 Z0 ) 0x19 ( 0x39 ) FP GA Y F PG A Cac he Y ( Y3 Y0) 0x18 ( 0x38 ) FP GA X F PG A Cac he X ( X3 X0 ) 0x17 ( 0x37 ) FIS UD F PG A I/ O / D( A T94 K05 ) 0x16 ( 0x36 ) FIS UC F PG A I/ O / C ( A T 94K05 ) 0x15 ( 0x35 ) FIS UB F PG A I/ O / B 0x14 ( 0x34 ) FIS U A F PG A I/ O / A 0x13 ( 0x33 ) FISCR F IADR X FI S1 X FIS0 0x12 ( 0x32 ) P OR T D P OR T D7 P OR T D6 P OR T D5 P OR T D4 P OR T D3 P OR T D2 P OR T D1 P OR T D0 0x11 ( 0x31 ) DDRD DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 0x10 ( 0x30 ) P IND P IND7 P IND6 PI ND5 PI ND4 PI ND3 PI ND2 PI ND1 PI ND0 0x0 F ( 0x2 F ) 0x0 E ( 0x2 E ) 0x0D ( 0x2D )

42 1 FPSLIC AT94K x0C( 0x2C) UDR0 U AR T0 I/ O 0x0B( 0x2B) UCSR0A RXC0 T XC0 UDR E0 FE0 OR0 U2X0 MP CM0 0x0A ( 0x2 A ) UCSR0B RXCI E0 T XCI E0 UDRI E0 RX E N0 T X E N0 CH R90 RXB80 T XB80 0x09 ( 0x29 ) UBR R0 U AR T0 0x08 ( 0x28 ) OCDR IDRD 0x07 ( 0x27 ) P OR T E POR T E7 POR T E6 P OR T E5 P OR T E4 P OR T E3 P OR T E2 P OR T E1 P OR TE 0 0x06 ( 0x26 ) DDRE DDR E7 DDR E6 DDR E5 DDR E4 DDR E3 DDR E2 DDR E1 DDR E0 0x05 ( 0x25 ) P IN E P IN E7 P IN E6 P IN E5 P IN E4 P IN E3 P IN E2 P IN E1 PI N E0 0x04 ( 0x24 ) 0x03 ( 0x23 ) UDR1 U AR T1 I/ O 0x02 ( 0x22 ) UCSR1A RXC1 T XC1 UDR E1 FE1 OR1 U2X1 MP CM1 0x01 ( 0x21 ) UCSR1B RXCI E1 T XCI E1 UDRI E1 RX E N1 T X E N1 CH R91 RXB81 T XB81 0x00 ( 0x20 ) UBR R1 U AR T1 A VR I/ O, F PGA I/ O IN O UT I/ O, , 0x00 0x1F I/ O, SBI CBI, SBIS SBIC ; IN OU T, 0x00 0x3F SRAM I/ O, 0 x I/ O I/ O (IN/ OU T ), 16 r0 r31 (0x1 F ) r0 r63 (0x3 F ) SRAM, 0x00 0x1F, I/ O 0x20 0x5F

43 30 AVR SoC FPSLIC, I/ O, 2, IN/ OU T I/ O 0x00 0x3F SRAM 0x20 0x5F, I/ O 0x20 0 x5f, 0, I/ O 1 CBI SBI, 1,, CBI SBI 0x00 0x1F, 1) SREG( ) SREG A VR SR EG I/ O 0x3F ( 0x5F ), :,, 7 I: I 0,, I 0, RE TI 6 T : BLD BS T T BST T, BLD T 5 H : H 4 S:, S = N V S N 2 V 3 V : N : 1 Z : 0 C: 2) SP( ) A VR 16, I/ O 0x3E (0x5E) 0x3D(0x5D) 8 F PSLIC 64 KB, SP SRAM

44 1 FPSLIC AT94K 31 0x60 P US H, 1,, 2 POP, 1, RET RET I, 2 4., MCU / 1) SFTCR( ) SFTCR 7 4: A T94K, 0 3 F MXOR: F rame Mode XOR ( / ), WDTS: 1, A VR, AVR WDTS 0 1 DBG : 1, A VR SRAM A VR DBG 0 0 SRS T : 1, A VR, AVR, MCUR EXT RF, AVR SRS T 0 2) MCU / MCUR( ) MCUR MCU / MCUR 7 J T RF : J TAG J TAG AVR _ RESET ( 0xC ) JT RF 0 0 A VR 6 J TD J TAG 0, J TAG, JTA G JATG, SE : MCU, SLEEP SE, SE SLEEP 4 3 SM1/ SM2: 1 0 3, 1.4.2

45 32 AVR SoC FPSLIC 2 P ORF : A VR S M1 SM0 1 WDRF : EXT RF : ( ) : Reset/ AVRReset 1 1 SF T CR SRST 1 PORF, Reset/ A VRReset 0 0 AVR AVR FPGA 1. FPGA Cache Logic A VR FPGA, FPG A Cache F PGA Cache F PGA 1) FPGA Cache FPGAD( ) FPGA Cache FPGAD FPGAD, I/ O, F PGA Cache I/ O CACH EIOW E A VR IOWE FPGAD OU T/ ST, CACH EIOWE FPGAD, SCR62 A VR Cache, CACHEIO- W E FPGAX Z F PGA 2) FPGA Cache FPGAX FPGAY FPGAZ( ) FPGA Cache FPGAX FPGAY FPGAZ 3 FPGA Cache 24 FPG A CACHEADDR23 0 F PGAD 2. AVR FPGA I/ O A VR 16 FPGA I/ O 4 I/ O F ISUA D F PGA I/ O F ISCR FPGAIORE

46 1 FPSLIC AT94K 33 F PGAIOWE AV R IORE IOWE I/ O, 2 FPG A, FPGAIORE FPGAIO- W E FISCR, FISU A D I/ O, A VR I/ O ; IN/ OU T, F PGA FPG A IORE/ IOWE FPGA I/ O FISCR( ) FPGA I/ O FISCR 7 F IADR: F PGA FIADR, FISU A D, F PGA F IADR 0, F IS UA D / I/ O XF IS1 XFIS0, FPG A I/ O / A VR I/ O / FPG A I/ O F PGA FPG AIORE F PGAIOWE A VR FIADR 0 6 2: XFIS1 0: FPGA I/ O 1 0 XF IS1 0 I/ O F PGA I/ O FPGA I/ O / I/ O FISCR FP GA I/ O XF IS1 XF IS F IS UA 0x14 ( 0x34 ) F ISUB 0x15( 0x35 ) F ISUC 0x16( 0x36 ) FIS UD 0x17 (0x37)

47 34 AVR SoC FPSLIC : AT94K05 FISUC (0x16/ 0x36 ), 16 F PGA A VR I/ O 4 I/ O FISU A D FPGA I/ O XFIS1 IS0, FPGAIOWE, F PGA 0 3. AVR/ FPGA I/ O I/ O FISCR FISU A D 1.4.4, F ISCR, FISU A FISUB FISUC F ISUD I/ O, 8 A VR - FPGA FISCR I/ O FISCR I/ O FI ADR( 7 ) F IADR( 6 2 ) X FIS1( 1 ) X FI S0 ( 0) FI SU A F ISUB F ISU C F ISU D IOSEL0 IOSEL4 IO SE L8 IOSEL IOSEL1 IOSEL5 IO SE L9 IOSEL IOSEL2 IOSEL6 IO SE L10 IOSEL IOSEL3 IOSEL7 IO SE L11 IOSEL15 : AT94K05 IOSEL7 0 FPGA I/ O /, OU T, IN, AV R FPGA A VR ;, A VR, FPGA A VR FPG A ( IORE, AVR FPGA OUT

48 1 FPSLIC AT94K 35 F PGAIOR E n ) AV R A VR DBUS( = FPG A ), io_ select0_ write : ldi r16, 0x00 out FISCR, r16 out FISU A, r17 ret io_ select3_ write : ldi r16, 0x01 out FISCR, r16 in r18, FIS UD ret 4. AVR FPGA I/ O AVR FPGA IN FISCR FIADR 1, 4 I/ O F ISU A FISU D, F PGA FISCR FIADR 0, 4 F PGA A VR FPG A FISUA FISUB FISUC FISUD( ) FISUA FISUB FISUC FISUD

49 36 AVR SoC FPSLIC 7 4 FI F3 0 : FPGA F PGA FPG A,, 2, 1 0, 0 2, FIFn A VR, 0, 1 0 I, F PGA, 7 4 FI F7 4: F PGA FIF3 0 : FPG A FI F11 8: FPGA FI F3 0: F PGA 3 0 AT94K FI F15 12 : FPGA F IF3 0: F PGA 3 0 AT94K FINT3 0 : FPGA 3 0 FPGA 16 I 1, FPG A F PGA, FPGA 3 0 A VR A VR 3 0 FINT7 4: FPGA F INT3 0: FP- GA FINT11 8: FPGA FIN T3 0: F PGA 3 0 AT94K FINT15 12 : FPGA F INT3 0: F PGA 3 0 AT94K AVR 1. A VR 5 : : RES ET AVR RESET, MCU : MCU, FPG A :, : SRS T MCU JTA G AV R : 1 MCU, MCU, I/ O, 0x0000 0x0000 JM P,

50 1 FPSLIC AT94K ( V CC = 3.3 V) Min T yp M ax ( ) V POT ( ) V V RST R ESE T V CC / 2 V 5 CP U T OU T ms ( POR) , MCU VCC VO U T, VCC, MCU

51 38 AVR SoC FPSLIC XTAL1, 5 CP U MCU WDT, MCU RESE T VCC, VC C VCC RESE T, MCU 3. A VRRESET VRS T ( ), t T O U T MCU 4. XTAL, t T O U T VCC = 3.3 V, t T O U T 3 s 5. SF T CR SRST AVR 1. A VR FPG A 35 I

52 1 FPSLIC AT94K ,,, RE SET, F PGA_IN T0 F PGA 0, ( Hex) 01 0x0000 R ESET : 02 0x0002 F PG A_IN T 0 F PG A x0004 E X T_ IN T x0006 F PG A_IN T 1 F PG A x0008 E X T_ IN T x000 A F PG A_IN T 2 F PG A x000C E X T_ IN T x000 E F PG A_IN T 3 F PG A x0010 E X T_ IN T 3 3 0A 0x0012 T IM2_COMP / 2 0B 0x0014 T IM2_O V F / 2 0C 0x0016 T IM1_CAP T / 1 0D 0x0018 T IM1_COMP A / 1 A 0 E 0x001 A T IM_COM PB / 1 B 0F 0x001C T IM1_O V F / x001 E T IM0_COMP / x0020 T IM0_O V F / x0022 F PG A_IN T 4 F PG A x0024 F PG A_IN T 5 F PG A x0026 F PG A_IN T 6 F PG A x0028 F PG A_IN T 7 F PG A x002 A U AR T 0_RXC U AR T x002C U AR T 0_DR E U AR T x002 E U AR T 0_ T XC U AR T x0030 F PG A_IN T 8 1A 0x0032 F PG A_IN T 9 1B 0x0034 F PG A_IN T 10 1C 0x0036 F PG A_IN T 11 F PG A 8 ( A T94K05 ) F PG A 9 ( A T94K05 ) F PG A 10 ( A T94K05 ) F PG A 11 ( A T94K05 ) 1D 0x0038 U AR T 1_RXC U AR T 1 1 E 0x003 A U AR T 1_DR E U AR T 1

53 40 AVR SoC FPSLIC.4.6 ( Hex) 1F 0x003C U AR T 1_ T XC U AR T x003 E F PG A_IN T x0040 F PG A_IN T x0042 F PG A_IN T x0044 F PG A_IN T 15 F PG A 12 ( A T94K05 ) F PG A 13 ( A T94K05 ) F PG A 14 ( A T94K05 ) F PG A 15 ( A T94K05 ) 24 0x0046 TWS_IN T 2 ( ) : 0x0000 MP ESE T : 0x0002 JMP FPGA_INT0 ; FPGA 0 0x0004 JMP EXT_INT0 ; 0 0x0006 JMP FPGA_INT1 ; FPGA 1 0x0008 JMP EXT_INT1 ; 1 0x000A JMP FPGA_INT2 ; FPGA 2 0x000C JMP EXT_INT2 ; 2 0x000E JMP FPGA_INT3 ; FPGA 3 0x0010 JMP EXT_INT3 ; 3 0x0012 JMP T1M2_COMP ; / 2 0x0014 JMP TIM2_OVF ; / 2 0x0016 JMP TIM1_CAPT ; / 1 0x0018 JMP TIM1_COMPA ; / 1 A 0x001A JMP TIM1_COMPB ; / 1 B 0x001E JMP TIM0_COMP ; / 0 0x0020 JMP TIM0_OVF ; / 0 0x0024 JMP FPGA_INT4 ; FPGA 4 0x0026 JMP FPGA_INT5 ; FPGA 5 0x0028 JMP FPGA_INT6 ; FPGA 6 0x002A JMP UART0_RXC ; UART0 0x002C JMP UART0_DRE ; UART0 0x002E JMP UART0_TXC ; UART0 0x0030 JMP FPGA_INT8 ; FPGA 8 0x0032 JMP FPGA_INT9 ; FPGA 9 0x0034 JMP FPGA_INT10 ; FPGA 10 0x0036 JMP FPGA_INT11 ; FPGA 11 0x0038 JMP UART1_RXC ; UART1 0x003A JMP UART1_DRE ; UART1

54 1 FPSLIC AT94K 41 x003b MP A RT1_TXC UART1 0x003E JMP FPGA_I NT12 ; FPGA 12 0x0040 JMP FPGA_I NT13 ; FPGA 13 0x0042 JMP FPGA_I NT14 ; FPGA 14 0x0044 JMP FPGA_I NT15 ; FPGA 15 0x0046 JMP TWS_INT ; 2 ; RESE T : 0x0048 LDI r16, high( RAMBND ) ; 0x0049 OU T SP H, r16 0x004A LDI r16, low ( RAMEND) 0x004B OU T SPL, r16 0x004C < inst r > xxx : AT94K05 U AR T, 2. A VR 8 TIM SK T/ C, I 0, I, RE TI I,, 1, 0,,, 0,, I,,, 1) / EIMF( ) / EIMF 3 0 INT3 0: INT3 0, I, 7 4 INT3 0: INT3 0, INTF3 0 SR EG I INT3 0 1, MCU 0, 1 0

55 42 AVR SoC FPSLIC / TIMSK( ) / TIMSK 7 TOIE1 : T/ C1 TOIE1 I 1, T/ C1 T/ C1, TI FR TOV1, 6 OCIE1A : T/ C1 A OCIE1A I 1, A T/ C1 A, TI FR OCF1A, 5 OCIE1B: T/ C1 B OCIE1B I 1, B T/ C1 B, TIFR OCF1B, 4 TOIE2 : T/ C2 TOIE2 I 1, T/ C2 T/ C2, TI FR TOV2, 3 TICIE1 : T/ C1 TICE1 I 1, 29 ( IC1 ) T/ C1, TI FR ICF1, 2 OCIE2: T/ C2 OCIE2 I 1, T/ C2 T/ C2, TI FR OCF2, 1 TOIE0 : T/ C0 TOIE0 I 1, T/ C0 T/ C0, TI FR TOV0, 0 OCIE0: T/ C0 OCIE0 I 1, T/ C0 T/ C0, TI FR OCF0, 3) / TIFR( ) / TIFR 7 TO V1: T/ C1 T/ C1, TO V1 0, TOV1 1 0 SREG I TOIE1 TOV1, PWM, T/ C1 0x0000, TOV1 6 OCF1A : 1A T/ C1 OCF1A ( 1A ), OCF1A 0, 1 0

56 1 FPSLIC AT94K 43 SREG I OCIE A OCF1A, 5 OCF1B: 1B T/ C1 OCF1B( 1B), OCF1B 0, 1 0 SREG I OCIE1B OCF1B, 4 TO V2: T/ C2 T/ C2, TO V2 0, TOV2 1 0 SREG I TOIE2 TOV2, PWM, T/ C2 0x00, TOV2 3 ICF1 : 1, ICF1, T/ C1 ICR1 0, 1 0 SREG I TICIE1 ICF1, 2 OCF2 : 2 T/ C2 OCR2 ( 2 ), OCF2 0, 1 0 SREG I OCIE2 OCF2, 1 TO V0: T/ C0 T/ C0, TO V0 0, TOV0 1 0 SREG I TOIE0 TOV0, PWM, T/ C0 0x00, TOV0 0 OCF0 : 0 T/ C0 OCR0 ( 0 ), 3. OCF0 0, 1 0 SREG I OCIE0 OCF0, A VR 4 4, 4, PC( 2 ), SP 2,, 3, MCU 4, PC, SP 2, AVR, AVR 1. MCU R S E, SLEEP MCU R SM1 SM0 ( ), 4 EXT_IN T0 3 F PGA_ INT0 3 MCU,, MCU, SLEE P, MCU

57 44 AVR SoC FPSLIC SM1 SM0 00, SLEE P MCU ; CP U, U AR T / 2, MCU CPU 3. SM1 SM0 10, SLEEP MCU,, ( ) MCU MCU,, MCU MCU 2 2, MCU 3.3 V 25, 1 s MCU,, MCU, 4. SM1 SM0 11, SLEE P MCU, : T/ C2, ASSR AS2, MCU T/ C2,, TIMSK, SREG I,, MCU 2, MCU 3,,, JTAG OCD A VR IEEE J TAG, OCD ( On Debug) OCD J TAG, A tmel A tmel J TAG ICE Chip JT AG OCD TA P T CK T MS TA P JTA G, TDI( ) TDO( ) ( ) J TAG ID (Bypass ) A VR I/ O OCD

58 1 FPSLIC AT94K 45 JTA G : IEEE J TAG ; J TAG A VR I/ O ; JTAG A VR SRAM F PGA/ AVR ; OCD, FPGA FRAME ; A VR Studio 4 OCD JTA G 4 JT AG, TAP : MS :, TAP TCK :, JTA G TCK TDI:, ( ) TDO :, A T94K IEEE TAP T RS T TestReSeT

59 46 AVR SoC FPSLIC J TAGEN, 4 TAP I/ O J TAGEN, TAP, JTA G System Designer 3.0 OCD, RES ET R ESET, / F PSLIC 3 / : 2 8 / T/ C0 T/ C / T/ C1 /, T/ C0,, T/ C kh z, T/ C2 RT C 1. / , T/ C0 T/ C1 4 : CK/ 8 CK/ 64 CK/ 256 CK/ CK, SFIOR PSR10,, / : T/ C0 T/ C1, PSR10 T/ C0 T/ C T/ C0 T/ C , T/ C2 PCK2, PCK2 ASSR AS2, T/ C2 TOSC1, T/ C2 TOSC1 TOSC2 D, ( kh z ), TOSC1 MCU 1/ 4, 1 M Hz SF IOR PSR2,, /

60 1 FPSLIC AT94K 47 I/ O SFIOR( ) T/ C I/ O SFIOR 7 2: 0 1 PSR2 : T/ C2 T/ C2 0 0 T/ C2 CP U, 0 T/ C2, 0 PSR10: T/ C0 T/ C1 T/ C0 T/ C1 0 0, T/ C0 T/ C1, / T/ C0 T/ C T/ C0 T/ C2 T/ C0 CK CK T/ C2 CK CK TOSC1 T/ C TIFR ; TCCR0/ TCCR2 ; TIMSK /

61 48 AVR SoC FPSLIC T/ C T/ C2

62 1 FPSLIC AT94K 49 T/ C0, CPU CP U, CP U MCU CP U,, T/ C0 ;, T/ C0, T/ C0 T/ C2 8 ( PWM), /, PWM 1) / 0 TCCR0( ) / 0 TCCR0 2) / 2 TCCR2( ) / 2 TCCR2 7 F OC0/ F OC2 : 1, PE1 ( T/ C0) PE3( T/ C2) COMn1 COMn0 COMn1 COMn0 FOC0/ FOC2,,,, / 0, CTC0/ CT C2 0 FOC0/ F OC2 PWM 6 PWM0/ PWM2: PWM T/ C0 T/ C2 PWM 5 4 COM01 COM00 COM21 COM20 : COMn1 COMn0 PE1( OC0 ) PE3 ( OC2) PE1/ PE3, 1, CTC0/ CT C2: 0 / CT C0 CTC2,, T/ C0 T/ C2 0x00 CT C0/ C TC2 0, T/ C 1 C, C - 1 C 0 1 8, COMn1 COMn0 0 0 T/ C Oc n 0 1 Ocn 1 0 Ocn 1 1 Ocn

63 50 AVR SoC FPSLIC C - 1, C - 1, C - 1, C - 1, C - 1, C - 1, C - 1, C - 1 C, C, C, C, C, C, C, C 0, 0, 0, 0, 0, 0, 0, 0 1, 1, 1, 1, 1, 1, 1, 1 T/ C PWM, 0, T/ C 0 x00 0xFF, 0xFF 0x00; 1, 0xF F 0x CS02 CS00/ CS22 CS20:, T/ C0 T/ C2 CS02 CS01 CS T/ C CK CK/ CK/ CK/ CK/ P E0( T0 ), P E0( T0 ), CS22 CS21 CS T/ C PC K PC K2/ PC K2/ PC K2/ PC K2/ PC K2/ PC K2/ T/ C T/ C0 CK, T/ C0 PCK2 T/ C0, P E0 ( T0), 3) / 0 TCNT0( ) / 0 TCNT0 4) / 2 TCNT2( ) / 2 TCNT2 8 T/ C / / ( PWM ), /, T/ C

64 1 FPSLIC AT94K 51 / 0 OCR0( ) / 0 OCR0 6) / 3 OCR2( ) / 3 OCR2 8 /, T/ C T/ C OCR,, TCCR0 T CCR2 T/ C OCR,, 3. / 0/ 2 PWM PWM, / 2, 0xFF 0x00 ; 0x00 0xFF, 0xFF 0 x00 / /, T/ C ORC0 ORC2 8 PWM, PE1( OC0/ PWM0 ) P E3 ( OC2/ PWM2 ), T/ C OCR0 OCR2 8 PWM, / 2 2 PWM TCCR0 TCCR2 CTC0 CTC2 PWM CTC0/ CTC2 0, T/ C /, PE1( OC0/ PWM0) PE3( OC2/ PWM2) ( TCCR0 TCCR2)COMn1/ COMn0 PWM CTC0/ CTC2 1, T/ C,, PE1 ( OC0/ PWM0 ) PE3 ( OC2/ PWM2 ) ( TCCR0 TCCR2) COMn1/ COMn0 PWM PWM C T Cn COMn1 CO Mn0 x 0 x , ( P WM ) 0, ( P WM ) f TCK0/ 2 / 510 f TCK0/ 2 / , f TCK0/ 2 / , f TCK0/ 2 / 256 : n = 0 2 ; x =

65 52 AVR SoC FPSLIC PWM,, T/ C FFH ORC, PWM / OCR OCR OCR,, ORC0 ORC2 T/ C PWM /, 0x00 0xF F, PE1( ORC0/ PWM0 )/ P E3( OCR2/ PWM2 ) COMn1/ COMn0,, , OCR 0xFF, P E1 (OC0/ PWM0 )/ P E3( OC2/ PWM2 ) / PWM OCRn = 0x00 0xFF COMn1 CO Mn0 OC Rn P W Mn 1 0 0x00 L 1 0 0xF F H 1 1 0x00 H 1 1 0xF F L

66 1 FPSLIC AT94K 53, OCRn = 0xF F ( n = 0 2 ) /, 0x00, TO V0 TOV2 ;, T/ C 0 2 T/ C, I,, TOV0 TO V2, ASSR( ) 7 4: ASSR 3 AS2 : T/ C2 AS2 0, T/ C2 CK AS2, T/ C2 TOSC1, TCNT2 OCR2 T CCR2 2 TCN2UB: T/ C2 T/ C2, T CN T2 TCN2UB TCNT2, TCN2UB 0 TCN2UB 0 TCN T2 1 OCR2UB: T/ C2, OCR2 ORC2UB OCR2, OCR2UB 0 OCR2 UB 0 OCR2 0 T CR2UB: T/ C2 T/ C2, TCCR2 TCR2UB TCCR2, TCR2UB 0 TCN2UB 0 TCCR2,, TCN T2 OCR2 TCCR2 TCNT2, OCR2 T CCR2 4. / 2 T/ C2 : (1 ) TCNT2 OCR2 TCCR2 : OCIE2 TOIE2 0 T/ C2 AS2 TCNT2 OCR2 T CCR2 TCN2UB OCR2UB TCR2UB 0, (2 ) kh z, 256 k Hz 0 H z 1 M Hz,

67 54 AVR SoC FPSLIC ( 3) TCNT2 OCR2 TCCR2, TOSC1 3, T CNT2 OCR2 ASSR (4 ) T/ C2 MCU, TCNT2 OCR2 T CCR2 ; MCU T/ C2 T/ C2 MCU, OCR2 T CNT2 ( OCR2UB 0 ) MCU,, MCU (5 ) T/ C2, 1 TOSC1 1 TOSC1,,, : TCCR2 TCN T2 OCR2 ; ASSR ; (6 ),, T/ C kh z, 1 s,, 1 s T/ C2 (7 ) :, MCU 3,, MCU,, (8 ), 3 1, 5. / 1 T/ C1 16 /, T/ C1 T/ C1 CK CK, TIFR ; T CCR1A TCCR1B T/ C1, ; / TIM SK T/ C1 T/ C1, CP U CP U, 1 CP U MCU, 2 OCR1A OCR1B T/ C1, T/ C1 2 A T/ C PWM, OCR1A/ OCR1B 2 PWM, T/ C1 PWM

68 1 FPSLIC AT94K 55 T/ C1 PE7( ICP ), T/ C1 ICR1 TCCR1B ICP ICP, 4 4, 1) / 1 A TCCR1A( ) / 1 A TCCR1A

69 56 AVR SoC FPSLIC 7 6 COM1A1 COM1A0: 1A COM1A1 COM1A0 T/ C1, OC1A( PE6) I/ O, COM1B1 COM1B0: 1B COM1B1 COM1B0 T/ C1, OC1B( PE5) I/ O, , X = A B CO M1 X1 COM1X0 0 0 T/ C1 OC1X 0 1 OC1X 1 0 OC1X 1 1 OC1X 3 F OC1A : 1A 1, PE6 COM1A1 COM1A0, COM1A1 COM1A0 FOC1A,,,, / 0, TCCR1B CTC1 0 F OC1A PWM 2 FOC1B: 1B 1, PE5 COM1B1 COM1B0 COM1B1 COM1B0 FOC1B,,,, / 0, TCCR1B CT C1 0 FOC1B PWM 1 0 PWM11 PWM10: PWM PWM PWM PW M11 P WM T/ C1 P W M 0 1 T/ C1 8 P W M 1 0 T/ C1 9 P W M 1 1 T/ C1 10 P WM 2) / 1 B TCCR1B( ) / 1 B TCCR1B

70 1 FPSLIC AT94K 57 7 ICNC1: ( 4 CK ) ICNC1 P E7( ICP ) / ICNC1 1, ICP 4 4, ICES1 XTAL 6 ICES1: ICES1 0, T/ C1 PE7 ( ICP ) ICR1 ICES1 1, T/ C1 P E7( ICP ) ICR1 5 ICPE :, 4: 0 3 CTC1 : T/ C1 0 CT C1 1, A, T/ C1 0 x0000 C TC1 0, T/ C1 1, A C, C - 1 C 0 1 8, C - 1, C - 1, C - 1, C - 1, C - 1, C - 1, C - 1, C - 1 C, C, C, C, C, C, C, C 0, 0, 0, 0, 0, 0, 0, 0 1, 1, 1, 1, 1, 1, 1, 1 PWM CTC1 0, T/ C1 / ; T/ C1 2 0 CS12/ CS11/ CS10 : T/ C1, T/ C1 CS12 CS11 CS T/ C CK CK/ CK/ CK/ CK/ PE4 ( T1 ), PE4 ( T1 ), T/ C1 T/ C1, P E4 ( T1),

71 58 AVR SoC FPSLIC / 1 TCNT1H TCNT1L( ) / 1 TCNT1H TCNT1L 16 T/ C1 CP U 2, /, 8 TEMP OCR1A OCR1B ICR1 T EM P,,, CPU T CNT1 H, T EMP CP U TCNT1L, TEMP TCNT1, TCNT1 ( 16 ), TCNT1H CPU T CNT1L, TCNT1L CPU,, TCN T1 H T EMP CP U T CNT1 H, TEM P CPU, 16 TCNT1, T CN T1L PWM, T/ C1 / T/ C1, T/ C1 4) / 1 OCR1AH OCR1AL( ) / 1 OCR1AH OCR1AL 5) / 1 OCR1BH OCR1BL( ) / 1 OCR1BH OCR1BL

72 1 FPSLIC AT94K / T/ C1 T/ C1 T/ C1 OCR, TCNT1 OCR1A OCR1B OCR1A/ OCR1B 16, T EMP 2 CP U OCR1A H OCR1BH, TEMP ; CP U OCR1AL OCR1BL, TEM P OCR1A H OCR1BH 16 OCR1A OCR1B, OCR1A H OCR1BH TCNT1 ICR1 TEM P TEM P, 6) / 1 ICR1H ICR1L( ) / 1 ICR1H ICR1L 16 ICE S1, PE7 ( ICP ), TCNT1 ICR1, ICF1 ICR1 16, T EM P 2 CP U ICR1L, ICR1L CP U,, ICR1H TEMP CP U ICR1H, TEMP CPU, 16 ICR1, ICR1L TCNT1 OCR1A OCR1B TEM P TEMP, 6. / 1 PWM PWM, T/ C1 OCR1A/ OCR1B PWM, PD6 (OC1A) P E5( OC1B) T/ C1, OCR1B TO P ( ), 0 OCR1A/ OCR1B ( ), PD6 ( OC1A)/ PE5 ( OC1B) COM1A1/ COM1B1/ COM1B0, , T/ C1 1 PWM, T/ C1 OCR1A/ OCR1B PWM, PD6 ( OC1A ) PE5 ( OC1B ) , PWM

73 60 AVR SoC FPSLIC OCR A OCR1B TCNT1 0, 9 PWM TOP PWM C T C1 P W M11 P W M10 P WM T O P x00 F F (255) f TCK1 / x01 F F (511) f TCK1 / x03 F F (1023) f TCK1 / x00 F F (255) f TCK1 / x01 F F (511) f TCK1 / x03 F F (1023) f TCK1 / PWM C TC1 COM1X1 COM1X0 OCX , ( P WM ), ( P WM ) , 1 1 1, : X = A B PWM, OCR1A/ OCR1B , T/ C1 TOP OCR1A/ OCR1B OCR1A/ OCR1B / OCR1 OCR1A/ OCR1B,, OCR1A/ OCR1B OCR1X 0x0000 TOP, PWM /, OC1A/ OC1B COM1A1/ COM1A0 COM1B1/ COM1B0,,

74 1 FPSLIC AT94K 61 OCR , OCR1 TOP OC1A/ OC1B PWM, OCR1X PWM OCR1X = 0x0000 TOP = TOP (X = A B) COM1X1 COM1X0 OCR1X OC1X PWM /, 1 0 0x0000 L 0x0000 TOV1 1 0 T O P H, 1 1 0x0000 H 1 1 T O P L,, TOV1 MCU , VC C = 3.3 V

75 62 AVR SoC FPSLIC MHz,, WDR, FPSLIC,, WDTCR( ) WDTCR 7 5: 0 4 WDTOE: WDT 0, 1 4, 0 3 WDE : WDE 1, WDTOE 1 WDE 0 : WDTOE WDE 1, WDE 1 4, WDE WDP2 WDP0: WDP2 WDP W DP2 W DP1 WD P0 W D T V CC = 3.0 V / ms UART F PSLIC 2 U ART : ; ; 8 9 ; ; ; ; ;

76 1 FPSLIC AT94K 63 3 : ; ; U ART 2 UA RT UART U AR T UDRn UDR n,, UDRn,, UDRn 10 (11), U DR n UCSRnA UDREn, U ART, 0 ( ) 0, 9 10 ( ) 9 ( U AR T UCSRnB CH R9n ), UCSR nb TXB8 9

77 64 AVR SoC FPSLIC U AR T TXDn, ( ) U DR n, U AR T,, UDR En, U DRn UDRn, 1, UCSR na TXCn UCSRnB TXENn U AR T TXENn 0, PE0 ( U AR T0 ) P E2 ( UA RT1 ) I/ O TXENn 1, U AR T PE0 ( U AR T0 ) P E2 ( U AR T1 ),, U ART UART 16 RXDn, CPU, 1, CP U RXDn 3 2,,

78 1 FPSLIC AT94K 65 CP U 0, CP U , : U ART, ,3 2 ;, U AR T UCSR na FEn U DRn, FEn, UDRn, UCSR na RXCn UDR n,, UDR n, U DRn ; UDR n, U DRn 9 ( U AR T UCSR nb CH R9n 1 ), UCSR nb RXB8n U DRn 9 UDRn, UA RT, UCSR nb ORn U DRn ORn UDR n,, CP U, UDRn ORn UCSRnB RXEN 0, PE1 ( n = 0 ) P E3( n = 1) I/ O RXEN, UAR T PE1 ( U AR T0 ) PE3 ( U AR T1 ) UCSRnB CH R9 n 1, 9 9 TXB8n ( UDR n ), 9 RXB8n 3., MCU, MCU, MCU, 9 ( UCSRnB C H R9n ) 9 1,, ( UCSRnB CH R9n 0 ), 1,, 9 ( UCSRnB C HR9n 1), 1 9 : 1, 0 : ( UCSR na M PCMn), UCSRnA RXCn UDRn, ( ),

79 66 AVR SoC FPSLIC UCSRnA M PCMn : UCSR na RXCn 8, 0,, UCSR na F En MPCMn 0 MCU,,, 4. UART 1) UART0 I/ O UDR0( ) UART0 I/ O UDR0 2) UART1 I/ O UDR1( ) UART1 I/ O UDR1 UDR n,, UDR n, UDRn; UDRn, U DRn 3) UART0 UCSR0A( ) UART0 UCSR0A 4) UART1 UCSR1A( ) UART1 UCSR1A 7 RXC0/ RXC1: U AR T RXCn U DRn ;, UCSR nb RXCIEn 1, RXCn RXCn UDRn, UCRn RXCn;

80 1 FPSLIC AT94K 67 6 TXC0/ TXC1 : U AR T TXCn, UDRn,, UCSRnB TXCIEn, TXCn TXCn 0, UDRE0/ UDRE1: U ART UDRn, UDREn, UCSRnB UDRIEn, UDREn 1, U AR T UDRn UDREn, UA RT UDR n UDREn, U DREn 1, 4 FE0/ F E1: MCU ( 0), F En 1, FEn 0 3 OR0/ OR1: UDR n,, ORn, UDRn 2: 0 1 U2X0/ U2X1: U AR T U2Xn U ART, / 8 CPU 16 0 MPCM0/ M PCM1: MCU, MPCMn, MCU M PCMn 0, 5) UART0 UCSR0B( ) UART0 UCSR0B 6) UART1 UCSR1B( ) UART1 UCSR1B 7 RXCIE0/ RXCIE1 :, UCSRnA RXCn 1,, MCU 6 TXCIE0/ TXCIE1:, UCSR na TXCn 1,, MCU

81 68 AVR SoC FPSLIC 5 UDRIE0/ UDRIE1: U AR T, UCSRnA U DREn 1,, MCU U AR T 4 RXEN0/ RXEN1: UA RT TXCn ORn F En, 3 TXEN0/ TXEN1:, U ART TXENn 0,, 2 CH R90/ C H R91: 9, MCU 9 9 / UCSRnB RXB8n/ TXB8 n 9 1 RXB80/ RXB81: 9 CH R9n, RXB8n 9 0 TXB80/ TXB81 : 9 CH R9n, TXB8n 5. 9 U AR T UCSRnA U2X, U ART 1,, 8 RXDn,, 1, CPU RXDn 3 2,, CPU 1 0, CP U , BA UD = FC K 16 ( UBR + 1), BA UD ; FC K ; UBR UBRRHI UBRRn ( ), UBR

82 1 FPSLIC AT94K / / MH z UBRRHI 3 0 UBR Rn UBR H E X UB R UBR UBRRHI 7 4/ / % / M Hz C E F B D E C A E B D UBR Rn UBR H E X UB R / % F B DF E F F B D E A C A A U AR T, 1, 16 8, 0.5 % UBR

83 70 AVR SoC FPSLIC UBR UBRRHI UBRRHI UBR 7 4/ UBR Rn H E X UB R UBR 7 4/ UBR Rn H E X UB R / MH z 3 0 / % / M Hz 3 0 / % F F C F B DF BF E F DF E F F F B F D B E D E DD A A E A C B A D A ) UART0 UART1 UBRRHI( ) UART0 UART1 UBRRHI UA RT 12 4 UBRR HI UA RT0 U AR T1

84 1 FPSLIC AT94K 71 4 U ART1 ; 3 0 U ART0 2) UART0 UBRR0 ( ) UART0 UBRR0 3) UART1 UBRR1 ( ) UART1 UBRR1 2, 2, SCL ( ) SDA ( ), F PSLIC 2 2, /, / 400 kh z 7, 10 T WEN 2, SCL SDA, 2, ,, ACK

85 72 AVR SoC FPSLIC 1. CP U I/ O 2 2 T WBR 2 TWCR 2 T WSR 2 T WDR, 2 TWAR 1) 2 TWBR( ) TWBR 7 0: 2 T WBR, SCL, Bit-ra te = fc K ( T WBR ), Bit-rate SCL ; fc K CPU ; TWBR 2, SCL,

86 1 FPSLIC AT94K 73 TWCR( ) TWCR T WCR 2,,,, STOP, T WDR, 7 T WIN T : 2 2,, TWINT SREG I T WCR T WIE, MCU 0x0046 T WINT, SCL T WINT 0 1, 0 : 0, 2, 0T WINT, TWAR T WSR T WDR 6 T WEA : 2 T WEA T WEA,, ACK : ; T WAR T WGCE ( General Call) ; / TW EA 0 5 T WS TA : 2 STAR T CPU, TWSTA 2, ST ART,, STOP, ST ART 4 T WS TO : 2 STO P T WSTO S TOP, T WS TO, S TOP, TWSTO 0, T WSTO STOP 3 T WWC: 2 T WIN T, T WDR TW WC T WDR 2 T WEN : 2 T WEN 0 SDA SCL, T WEN 1 1: 0 0 T WIE : 2 SREG I TWIE, T WINT 1, 2

87 74 AVR SoC FPSLIC TWSR( ) TWSR T WSR 2 26 T WSR 0 xf8,, 2 TWINT, T WSR, T WINT TWS: : 0 4) 2 TWDR( ) TWDR 2 T WDR,, T WDR ;, T WDR 2 ( TWINT ), TWDR, T WDR, MCU 2,,, ( MCU ) ACK 2, CPU ACK 5) 2 TWAR( ) TWAR T WAR 7, T WGCE 0x00, 7 1 TWA : TWGCE: 2, MCU : : S: TAR T ;

88 1 FPSLIC AT94K 75 R: 1 ( SDA ) ; A : ( SDA ) ; W: 1 ( SDA ) ; A : ( SDA ) ; Da ta: 8 ; P : S TOP , 2 TWSR, 2 2, 0, 2, 0,, 0 T WAR T WDR TWSR 2, TWSR 1),, , TWCR

89 76 AVR SoC FPSLIC.4.20 TWCR: TWCR TWI N T TWEA TWST A TW ST O TW WC TWEN TW IE 0 X X T WEN 2, T WS TA T WS TO 0, T WS TA 2, STA RT TWINT, T WSR 08H MCU T WDR ( 7 ) ( SLA + W ), T WIN T 0, 2 T WINT 1 0, T WINT, T WSR 0x18 0x20 0x38; 0x68 0 x78 0xB T WIN T ;,, T WCR T WWC T WCR T WS TO, 2 2 / TW DR TWCR ST A ST O TW IN T TWEA 2 0x08 ST A R T SL A + W X 0 1 X SL A + W 0x10 ST AR T SL A + W SL A + R X X X X ACK N O T ACK SL A + W ACK N O T ACK SL A + R 0x18 SL A + W ( ) X, ACK ACK NO T ACK T WDR X ST AR T T WDR X ST OP, TWST O T WDR X ST OP, ST AR T, TW ST O 0x20 SL A + W ( ) X, ACK NO T ACK T WDR X ST AR T N O T ACK T WDR X ST OP, TWST O T WDR X ST OP, ST AR T, TW ST O 0x28 ( ) X, ACK NO T ACK ACK T WDR X ST AR T T WDR X ST OP, TWST O T WDR X ST OP, ST AR T, TW ST O

90 1 FPSLIC AT94K / TW DR TWCR ST A ST O TW IN T TWEA 2 0x30 ( ) X, ACK NO T ACK N O T ACK T WDR X ST AR T T WDR X ST OP, TWST O T WDR X ST OP, ST AR T, TW ST O 0x38 SL A + W T WDR X 2, T WDR X S T AR T STA RT ( Repeated S TAR T, 0x10),2 T WDR SLA + R 2),, STAR T TWINT TWDR (7 ) ( SLA + R ), TWINT , T WINT, T WSR 0x40 0x48 0x38, 0x68 0 x78 0xB T WIN T

91 78 AVR SoC FPSLIC TWDR ), TWCR T WSTO STAR T ( 0x10 ), 2 TWDR SLA + W TWCR / TW DR ST A ST O TW IN T TWEA 0x08 ST A R T SL A + R X 0 1 X SL A + R ACK N O T ACK 0x10 ST AR T SL A + R SL A + W X X X X SL A + R ACK N O T ACK SL A + W 0x38 SL A + R T WDR X 2, N O T ACK T WDR X S T AR T 0x40 SL A + R ACK T WDR T WDR , NO T ACK, ACK 0x48 SL A + R T WDR X ST AR T N O T ACK T WDR X ST OP, TWST O T WDR X ST OP, ST AR T, TW ST O 0x50 ACK , NO T ACK, ACK 0x X ST AR T N O T ACK X ST OP, TWST O X ST OP, ST AR T, TW ST O 3),, , T WCR T WAR TWAR TWCR: TW AR TW A6 TW A5 TW A4 TW A3 TW A2 TW A1 TW A0 T WGCE TWCR TWI N T TWEA TWST A TW ST O TW WC TWEN TW IE X 7 2 LSB, 2 0x00 T WEN 2 T WEA, ( ) ACK T WS TA T WS TO 0

92 1 FPSLIC AT94K TWAR TWCR,2, (, TWAR T WGCE ), 0 ( ) 2, TWSR ( 0x68 0x78 ), CP U / TW DR TWCR ST A ST O TW IN T TWEA 2 0x60 SL A + T WDR X 0 1 0, NO T ACK W T WDR X 0 1 1, ACK ACK 0x68 SL A + R/ W T WDR X 0 1 0, NO T ACK T WDR X 0 1 1, ACK ; SL A + W ACK

93 80 AVR SoC FPSLIC 2 2 / TW DR TWCR ST A ST O TW IN T TWEA 2 0x70 ACK T WDR T WDR X X , NO T ACK, ACK 0x78 SL A + R/ W T WDR X 0 1 0, NO T ACK T WDR X 0 1 1, ACK ; ACK 0x80 T WDR X 0 1 0, NO T ACK SL A + W T WDR X 0 1 1, ACK ; NOTACK 0x ; SL A + W SL A GCA ; ; SL A ; GC = 1, NO T ACK GCA ; SL A GCA; ST AR T ; SL A ; GC = 1, GCA ; S T AR T 0x90 X 0 1 0, NO T ACK ; X 0 1 1, ACK ACK 0x ; ; SL A GCA ; NO T ACK SL A ; GC = 1, GCA ; SL A GCA; ST AR T ; SL A ; GC = 1, GCA ; S T AR T

94 1 FPSLIC AT94K / TW DR TWCR ST A ST O TW IN T TWEA 2 0 xa ; ST O P SL A GCA ST AR T ; SL A ; GC = 1, GCA ; SL A GCA; ST AR T ; SL A ; GC = 1, GCA ; S T AR T T WEA (0 ), 2 SDA T WEA 2, TW EA,, T WEA 2 ADC, 2, / CP U,,2 SCL, T WCINT 0 MCU,, TWDR 4),, TWAR TWCR,2,

95 82 AVR SoC FPSLIC, T WAR T WGCE ), 1( ) 2, T WSR ( 0 xb0 ), CP U / TW DR TWCR ST A ST O TW IN T TWEA 2 0x A8 SL A + 1 X , NO - R T ACK ACK 1 X 0 1 1, ACK 0xB0 SL A + R/ W 1 X , NO - T ACK ACK 1 X 0 1 1, ACK 0xB8 T WDR 1 X , NO - T ACK ACK 1 X 0 1 1, ACK 0xC0 T WDR T WDR ; SL A GCA N O- T WDR ; T ACK SL A ; GC = 1, GCA T WDR ; SL A GCA; ST AR T T WDR ; SL A ; GC = 1, GCA ; S T AR T 0xC8 T WDR T WDR ; SL A GCA ( T WEA = 0 ) T WDR ; ACK SL A ; GC = 1, GCA T WDR ; SL A GCA; ST AR T T WDR ; SL A ; GC = 1, GCA ; S T AR T TW EA, 2 0xC0 0xC8,, 1

96 1 FPSLIC AT94K 83 T WEA, T WEA,, T WEA 2 5) , 0xF8 0x / TW DR TWCR ST A ST O TW IN T TWEA 2 0x F8 0x00 ; T WIN T = 0 START S T OP TW DR T WCR ; TW DR X ST OP 0 TW ST O 0xF8, T WINT 0 2 0x00 STA RT S TOP,, ACK ST ART STO P T WINT, TWSTO, 1 T WINT 0 2 T WS TO 0 ( TWCR ), SDA SCL, S TO P I/ O A VR I/ O / SBI CBI ( / ), ( / ) 1. D D 8 I/ O D 3 : POR TD (0 x12/ 0x32 ) ; DDRD ( 0x11/ 0x31 ) D PIND (0 x10/ 0x30) PORTD DDRD /, P IND D, 20 ma PD0 PD7,,, 1) D PORTD( ) D PORTD

97 84 AVR SoC FPSLIC D DDRD( ) D DDRD 3) D PIND( ) D PIND D, D D, D ; PIND, D I/ O PDn I/ O, DDRD DDDn DDDn 1, PDn ; DDDn 0, PDn PDn, POR TDn, PDn, PORTDn 0,, D DDDn D D

98 1 FPSLIC AT94K 85 PORTD DDDn DDDn POR T Dn I/ O 0 0 ( High Z ) 0 1, PDn : n = 7 0, 2. E E 8 I/ O E 3 : P OR TE ( 0x07/ 0x27 ) ; DDRE( 0x06/ 0x26) PINE ( 0x05/ 0x25 ) PORT E DDRE /, PINE E, 20 ma PE0 PE7,,, E, SCR AVR I/ O E PE0 T X0( U AR T 0 ) 0 PE1 RX0( U AR T 0 ) 0/ P W M0 PE2 T X1( U AR T 1 ) PE3 RX0( U AR T 1 ) 2/ P W M2 PE4 IN T0 ( 0 ) 1 PE5 IN T1 ( 1 ) 1B/ P W M1B PE6 IN T2 ( 2 ) 1 A/ P WM1 A PE7 IN T3 ( 3 ) 1, DDRE PORT E, 1) E PORTE( ) E PORTE

99 86 AVR SoC FPSLIC E DDRE( ) E DDRE 3) E PINE( ) E PINE PINE, E, ; P INE, 1) E I/ O P En I/ O, DDRE DDEn DDEn 1, P En ; DDEn 0, P En P En, PORT En, P En, POR TEn 0,, E DDEn E DDEn DD En POR T E n I/ O 0 0 ( High Z ) 0 1, PEn : n = 7 0, 2) E UART / 0: U AR T0 1: U AR T0 U AR T0, DDRE0, POR TE0 1 2: U AR T1, U AR T,, F PSLIC SCR52, E UAR T0 E U AR T1 SCR53 3: U AR T1 U AR T1, DDRE2, POR TE : 0/ 1/ 2/ 3 PE4 PE7 MCU,, SCR48 SCR51 INT0 INT3

100 1 FPSLIC AT94K 87 E CH ECK CON FPSLIC ( ) P E7/ CHECK, CHECK P E7 INT3 3) E / E /, ( T/ C0 T/ C1 ) ( T/ C1) PWM ( TC0 TC1 TC2), ( TC0 TC1 TC2 ) E, E (PE0)

101 88 AVR SoC FPSLIC E (PE1) E (PE2)

102 1 FPSLIC AT94K 89 E (PE3) E (PE4)

103 90 AVR SoC FPSLIC E (PE5) E (PE6)

104 1 FPSLIC AT94K 91 E (PE7)

105 System Designer 3.0 System Designer 3.0 Atmel FPSLIC ( Field P rogrammable Syst em Level Integrat ed Circuit, ) 2.1 System Designer 2.1.1, System Designer MB Windows N T/ 2000/ XP ( Service Pack 6) 128 MB Intern et E xplorer 5.0,, ( HostID ), Licen se;,, System Designer : (1 ) System Designer 3.0, SETU P.EXE, (2 ) INS TALL PRODUCT S, 2.1.2

106 2 System Designer

107 94 AVR SoC FPSLIC FPSLIC SYST EM DESIGNER Sy st em Designer, (4 ) Yes System Designer, ; No, (5 ) Remove Next, (6 ) O K, System Designer, 2.1.5, Mentor Graphics Licensing, (7 ) Yes, 2.1.7

108 2 System Designer System Designer 3.0

109 96 AVR SoC FPSLIC Next, (9 ) System Designer,, Yes, No, 2.1.9

110 2 System Designer Next, System Designer C: \ SystemDesigner, Browse : (, C: \ Sysem- Designer, C: \ System Designer ) (11) Next,

111 98 AVR SoC FPSLIC A tmel, Next, (13), N ext, OK, , Atmel License, License, ( License (, , H ostid ; License,

112 2 System Designer License License, Request License, Atmel ;, 24 h License License, Continue Install (14), , README, System Designer 3.0 Finish,,

113 100 AVR SoC FPSLIC.1.3 License License, License (1 ) License C: \ SystemDesigner \fpslic.dat (2 ), Atmel Mentor Graphics Licen sing Configure Licensing, (3 ) Next,

114 2 System Designer Define product licen se locations Next, License (5 ) C: \ SystemDesigner \ fp slic.dat, Next, License (6 ), Licen se License, Licen se, Licen se (1 ) License C: \ SystemDesigner \fpslic.dat (2 ), Atmel Mentor Graphics Licen sing Configure Licensing,

115 102 AVR SoC FPSLIC Next, (4 ) Load hardware key device driver ( s) Define product licen se locations Next,

116 2 System Designer GLOBE trotter FLEXid made by Dallas Semiconductor ( Dallas DS1410E hardware key ) Next, Sy st em Designer,, < CD Drive > : \ License \ Drivers \ Dallas Next, (6 ) O K, (7 ) C: \ SystemDesigner \ fp slic.dat, Next,

117 104 AVR SoC FPSLIC Windows (8 ) License, Yes, I want to restart my computer now., Finis h License 2.2 System Designer, 2.2.1, F PGA AVR, ( SW1 SW4 ) A VR, A VR ( C ), 8 ( L1 L8) 5 8 ( SW5 SW8 ) F PGA I/ O, F PGA ( FINT0 F INT3 ) A VR, FPG A, FPGA 4 A VR A VRCLK FPG A GCLK

118 2 System Designer FPGA AVR C: \ Sy st emdesigner \ Examples \ AT94K \ Coverify \2451.zip,2451.zip zip * q s_fpga.vhd q s_fpga.pin wa ve.do q s_ avr.asm q s_ avrim.c At94 kdef.inc V H DL F PG A AVR I ma gecraft Compil er C Includ e, : (1 ) C: \ training\ fp slic \ lab1; (2 ) 2451.zip lab1, ImageCraft C : (1 ) System Designer (2 ) Install P roducts ImageCraft C Compiler SystemDesigner 3.0 ImageCraft C 30 Image- Craft C, ImageCraft ImageCraft,

119 106 AVR SoC FPSLIC System Designer 3.0, System Designer System Designer (2 ) P roject N ew, 2.2.3,

120 2 System Designer Next, (4 ) C: \ training\fpslic \ lab1, lab1.apj, N ext,

121 108 AVR SoC FPSLIC AT94K40 25DQC, Next, (6 ) Toolflow Mentor V HDL, Next, 2.2.7,

122 2 System Designer Next, ( 8) Finis h, lab1.apj, AT94K40 25DQC lab1.apj System Designer

123 110 AVR SoC FPSLIC, Quick Flow, Quick Flow (10) Advanced Flow, F PSLIC Advanced Flow

124 2 System Designer AVR / C (1 ) Advanced Flow SW Compiler, A VRStudio, SystemDesigner Tools R un Software Compiler, SW Compiler Change T ool Settings C: \ SystemDesigner \ bin \ Wavrasm. exe, Wavras m (2 ) AVRStudio, SW Compiler, No, qs_avr.asm ; A VRStudio, Project Build, Assembly complet e with no errors A VRStudio, Sy stemdesigner, Wavrasm, Wavrasm File Open, ( 3) C: \ training\ fp slic \ lab1 qs_avr.asm,, qs_avr.asm ( 4) Wavrasm Assemble,, Message, Assembly complete with no errors, System Designer (5 ) C, ImageCraft C SW Compiler, SW Compiler (6 ) Change Tool Settings, , C: \ icc \ bin\ iccavride.exe (7 ) O K, ( 8) ImageCraft C, Yes ; ImageCraft C, No (9 ) SW Compiler, ImageCraft C (10) Project New, C: \ training \ fp slic \ lab1, qs_avrim Save

125 112 AVR SoC FPSLIC ImageCraft C

126 2 System Designer Files,, Add File( s) C (12) qs_avrim.c Open, C Files, qs_avrim.c, (13) Project Options, (14) Target, Device Configuration A T94K40, FPSLIC Memory 32K Code/ 4K Data, OK qs_avrim.c

127 114 AVR SoC FPSLIC.2.19 (15) Project Rebuild A ll, Done, ;, ImageCraft

128 2 System Designer File, Exit, System Designer : FPSLIC C FPSLIC : / briefcase.yahoo.com/ Yahoo! ID : atmel_soc Yahoo! Password: fpslic FPGA VHDL (1 ) Advanced Flow ( ) Synthesis Tool, V H DL, VHDL (2 ) Yes, (3 ) qs_fpga.vhd, LeonardoSpectrum, LeonardoSpectrum (4 ) Technology AT 94K, Leonardo Input qs_fpga.vhd Run Flow, Leonardo, V HDL, Output qs_fpga.edf, ( IDS)

129 116 AVR SoC FPSLIC.2.23 (5 ), Leonardo, System Designer AVR FPGA ( 1 ) Advanced Flow ( ) AV R FPG A Interface,, (2 ) O K, qs, (3 ) AVRIoSelects

130 2 System Designer Input design ports load ( 0 ), I/ O Select lines from A VR IOSELA0 (5 ) Connect, load (0 ) IOSELA Input design port s I/ O Sel ec t lines from AV R A VRIoSelec ts load0 lo ad3 IOSEL A0 IOSEL A3 F P GAInt errupt s fint s0 fints3 IN T A0 I N T A3 Da taf rom A VR din ADI NA0 A VR Controls wen F IOWE A F P GAClock s clk GCL K5 (6 ) /,

131 118 AVR SoC FPSLIC.2.26 (7 ) Generate Template Test Bench file, OK,, (8 ) Yes,, System Designer FPGA (1 ) Advanced Flow ( ) Figaro IDS..., FPGA, Files Settings 3, : EDI F ; FPG A ( *.fgd) ; FPG A

132 2 System Designer FPGA (2 ) ( Open EDI F Netlist), Browse, C: \ training \ fpslic \ lab1 qs_ fpga.edf ( LeonardoSpectrum V H DL ),, FPGA (3 ) User Library Settings, FPG A FPGA

133 120 AVR SoC FPSLIC O K, Design Constraints ( ), : lick here to edit/ assign pin locks ( ) I/ O, Assign Pin Lock s, I/ O,, File Export Click here to import constraints from file ( ) Figaro yourfilename.rct qs_fpga.pin, (5 ) Import Con straints,

134 2 System Designer List Files of Type Part/ Pinout( *.pin), qs_fpga.pin (7 ) O K, ( ) Place and Rout e, : uality Quality Timing Driven Design Figaro, C: \ SystemDesigner \ doc \ Tutorial.pdf (8 ) Quality (9 ) Compile, (10) Compile, Window New Compile Window,,, F7 F8, (11) File Exit, Yes, Figaro, System Designer,, ( 1) Advanced Flow ( ) P re layout Coverify,, C: \ training\ fp slic \ lab1 qs_fpga_pretb.vhd (2 ) Edit Testbench, qs_fpga_pretb.vhd H DLPlanner, , : signal sig_ext : std_logic_vector (3 dow nto 0) : = "1111 " ; signal sig_pd : std_logic_vector( 7 downto 0 ) ; (3 ), , : EXT_INT0 = > sig_ext( 0), - - External Interrupt 0 EXT_INT1 = > sig_ext( 1), - - External Interrupt 1 EXT_INT2 = > sig_ext(2 ), - - External Interrupt 2 EXT_INT3 = > sig_ext( 3), - - External Interrupt 3 PORTD = > sig_pd, - - LEDs (4 ) stimulus process, : stimul us_proces s: PROCESS BEGIN sig_sw < = "0001 " ; - - switch 5, you should see on alpha0 & alpha1 wait for 10 us ;

135 122 AVR SoC FPSLIC HDLPlanner HDLPlanner

136 2 System Designer * * * Add your stimulus values here * * * * sig_se < = "0001" ; - - switch 5, you shoule see * pattern on alpha0 & alphal wait for 10 ns ; sig_ext < = "1110 " ; - - switch 1, you should see Counting Up pat tern on PORTD (L EDs ) wait for 10 us ; sig_sw < = "0010 " ; - - switch 6, you should see + pattern on alpha0 & alpha1 wait for 10 us ; sig_ext < = "1101 " ; - - switch 2, you should see Counting Dow n pattern on PORTD ( LEDs) wait for 10 us ; sig_sw < = "0100 " ; - - switch 7, you should see x pattern on alpha0 & alpha1 wait for 10 us ; sig_ext < = "1011 " ; - - switch 3, you should see K nightrider pat tern on PORTD (L EDs ) wait for 10 us ; sig_sw < = "1000 " ; - - switch 8, you should see 0 pat tern on alpha0 & alpha1 wait for 10 us ; sig_ext < = "0111" ; - - switch 4, you should see Bounce pat tern on PORTD ( LEDs ) wait for 10 us ; END PROCESS stimulus_process ; (5 ), HDLPlanner ( 6) OK, Test Bench Manager,, qs_test_bench (7 ) O K, 3, DOS ModelSim A VR Studio, ModelSim A VR Studio, (8 ) AVR Studio, File Open File qs_avrim.cof, Fpslic_avr_core FPSLIC CoSimulator

137 124 AVR SoC FPSLIC Finis h, AVR Studio, ModelSim, A VR Studio, ModelSim (10) ModelSim, add wave r / *,, (11) ModelSim, ru n all, ModelSim, AVR Studio ( : ModelSim A VR Studio, ModelSim run all ; A VR Studio ModelSim, A VR Studio Auto Step, H ardware Break ) (12) A VR Studio, Workspace I/ O Auto Step ( POR TD External Interrupt ) (13) H ardware Break, ModelSim (14) WAVE, Zoom Zoom Full (15) Tools Window P references,

138 2 System Designer Display Signal Path 0 1, OK, (17) ModelSim, run all (18) A VR Studio, File Exit, ModelSim ( 1) Advanced Flow Post layout Coverify..., C: \ training \fpslic\ lab1 qs_fpga_posttb.vhd ( 2) Edit Testbench, qs_fpga_posttb.vhd H DLPlanner 3, qs_fpga_pretb.vhd, (3 ), HDLPlanner (4 ) Execute Command File at startup, C: \ training\ fpslic \ lab1 wave.do, (5 ) OK, V HDL, VHDL

139 126 AVR SoC FPSLIC post_test_bench, OK, SDF Timing Value (7 ) typical, OK, 3 : DOS Model- Sim AVR Studio, wave ModelSim A VR Studio, (8 ) AVR Studio, File Open File qs_avrim.cof (9 ) AVR Studio (10) Auto Step ( PORTD External Interrupt ) (11) H ardware Break, ModelSim (12) WAVE, Zoom Zoom Full (13) ModelSim, run all (14) A VR Studio, File Exit, ModelSim (1 ) Advanced Flow Device Programming,, A VR, FPGA AVR, AVR H ex Include A VR H ex File, Browse, FPGA A VR, FPGA Bitstream Include F PGA Bitstream, Browse AVR F PGA, A VR Hex FPG A Bit stream (2 ) FPGA Bitstream Include F PGA Bit stream, Browse qs_fpga.bst (3 ) AVR H ex Include A VR H ex File, Browse qs_avr.hex (4 ) Bitstream Download P rogram Configurator, 1M (5 ) , F PSLIC CR Set tings FPGA CR Set tings OK, (6 ) 25, 10

140 2 System Designer A TS TK94 J1 (7 ) 9 V ATSTK94 P3 (8 ) , ATSTK94, A F A VR FPGA L1 L8 A VR SW1 SW4 A VR, SW5 SW8 F PGA (9 ) SW10 PROG SW10 ( PROG) ( RU N ) PROG, CPS, System Designer F PSLIC RU N, F PSLIC (10) SW14 ON, ( ),,, (11) OK, fpslic_fpga.bst, ATSTK94, Atmel A T17 ( CPS),

141 128 AVR SoC FPSLIC ATSTK94, CPS (12) SW10 RU N (13) FPSLIC, AVR A VR A VR, ;, JP19 A VR JP19 SW12 SW12 (14) SW1 SW8, (15),, F PSLIC System Designer

142 System Designer System Designer 3.0 System Designer atmel SystemDesigner 3.0, Sy st emdesigner,,,,,,,,,, Mentor Model- Sim, Viewlogic ; A VR, ICC IAR,,,,,, 3.1.2, , :, 3.1.1,,

143 130 AVR SoC FPSLIC , : (1 ) P roject Open,, ( I) *.apj 3.1.2

144 3 System Designer (2 ),, 3.1.3, *.apj ; U1;, H DL Synhesis F PGA Place and Rounter ;, H DL Synthesis *.vhd, ; 3, ,, 3, 3, 3 : Quick Flow( ) Advanced Flow( ) Device View( ) DeviceView, 3.2.1

145 132 AVR SoC FPSLIC :,, F PGA SRAM A VR AVR ;,,, A VR BUS, A VR interface: T his AV R interface component define the interface bet ween the AVR CPU and F PGA core.the FPG A core can not directly interact with AVR and its peripheral, it has to use the AVR bus architecture interact with them : 5, 5 FPSLIC, ;, Device View, Quick Flow, 3.2.2

146 3 System Designer ,, FPSLIC 3, FPGA, A VR, F PGA A VR,, /, Text Editor Simulator, Simulator, Text Editor *.vhd *.v Simulator ; *.vhd *.v,, Figaro Post layout Coverify,, FPG A,, FPSLIC,

147 134 AVR SoC FPSLIC , 5 : 5, ( Project) : System Desinger 3.0 EW :, Project New,,, Figaro A VR Studio,,, Edit Add Design Open:

148 3 System Designer lose:, Save:, Save As :, P rint: Open Log Viewer: pen EasyPlanner: Easy Planner EasyPlanner Atmel, : :, : : ; H tml : :, :, ( CIV ) : CIV, : Inspect, ; Delete :, :, V HDL V erilog ; V HDL Verilog, Exit : System Desinger ( Edit ) dd Part :,, Add Design File : Edit Add Design File,, Ctrl,, Delet e: Rename:, Change Part :,, Edit Change Part,, O K

149 136 AVR SoC FPSLIC hange Tool Settings: *.exe *.pcl, Lau nch Project Tool, *.pcl A t- mel,,, Default et tool Flow : V HDL V erilog Set Design Directory: System Desinger,,, Launch P roject T ool:,, Chang T ool Settings Chang Tool Set tings Launch Windows Associated Tool : Expand: Collap se : ( Option s ), egistered File T ypes :,,, Registered File Types, Edit Associated OS P rogram, New Type, OS default.opt : Mouse Buttons: ; H elp Options: Syst em Desinger 3.0 F PSLIC

150 AVR A VR Studio 4 A VR ( Integrat ed Development Environment, IDE) AVR 8 RISC, A VR Studio A VR STK AVR Studio A VR Studio, Atmel A VR Tools A VR Studio 4 A VR Studio 4, AVR,,, A VR Studio AVR Studio A VR Studio aps, A VR Studio, Project I/ O Info 3, 3, Project ;, P roject, 4.1.2,,, Set as Entry File I/ O I/ O 3, 4.1.3, 4,, I/ O 3 :

151 138 AVR SoC FPSLIC AVR Studio A VR R0 R31 32,,, I/ O AV R I/ O, Atmega128

152 4 AVR 139 I/ O A T90S8515, / 8 16 Info 3 :, A VR, I/ O I/ O,

153 140 AVR SoC FPSLIC,,, 3. Build Messages Find in files Breakpoints 4 Build essages,,,, Find in files Breakpoints, 4. C/ C + +,,,,, +,, 5. A VR, SRAM, I/ O I/ O,, Flash EE PROM,,, View, AVR Studio 1. Debug : tart Debugging,,,, Stop Debugging,, Reset(Shift + F5),

154 4 AVR 141 Run ( F5 ) ( ), Break ( Ctrl + F5 ),,, Step Into( F11 ) A VR Studio, ;,, Step Over ( F10),,, Step Out(Shift + F11 ) Step Over,, Step Out,, Step Out, Run To Cur sor ( F7 ), Run T o Cursor,,,, Auto Step( Alt + F5 ) Step Into AVR Studio, ;, Step Into, Step Into Auto Step, Set next sta tement,, Show next statement 2.,, Breakpoints : oggle Breakpoint( F9),, Disable/ Enable breakpoint,, Enable breakpoint Remove all Breakpoints

155 142 AVR SoC FPSLIC Breakpoints, Breakpoints, P roperty, : tera tions,,, ;,, AVR Studio Wa tchpoint,,, Show message,,, AVR 3 Tools Options Breakpoint, : ; ;, AVR Studio

156 4 AVR :, 4.2 AVR A VR F PGA, AVR, FPG A, A VR FPG A, System Designer Advanced Flow A VR Design, AVR Studio AVR, FPGA System Designer AVR Design Sy st em Designer Advanced Flow AVR Design, A VR Design, 3 : ( 1) SW Compiler, A VRStudio, SystemDesigner Tools Run Software Compiler, SW Compiler Change Tool Set ting s C: \ SystemDesigner \ bin \ Wavrasm.exe, Wavrasm (2 ) AVRStudio, SW Compiler, Yes, AVRStudio,, *.ASM AT94Kdef.inc, Project Build, Assembly complete with no errors A VRStudio, SystemDesigner

157 144 AVR SoC FPSLIC Advanced Flow AVR Design, Wavrasm, Wavrasm File New,, *.ASM File Open, ASM,, C ImageCraft C C, ImageCraft C SW Compiler, Change Tool Settings,, c: \ icc\ bin\ iccavride.exe OK, ImageCraft C, Yes; ImageCraft C, No SW Compiler, ImageCraft C Project New Files, Add File( s ), C Project Options, Target,, F PSLIC Memory, O K Project Rebuild A ll C, Done;, File Exit, System Designer (3 ) SW Debugger, A VR Studio 4,

158 4 AVR 145 A VR Studio AVR Studio A VR Studio A VR, A tmel A VR Tools AVR Studio 4 : (1 ) P roject N ew Project, ,,,, Initial File, *.asm ; Creat Folder,,, Next ; Finis h ;, (2 ) Next, 4.2.3, ; (3 ), Finish, *.aps, Next, Finish, *.aps AVR Studio, Debug Select Platform and Device, (4 ), *.asm,, A VR,

159 146 AVR SoC FPSLIC Syst emdesign er S W Debugger ( ICC *.cof, IAR *.dbg, Cod evision *.cof, oth ers *.obj),, 4.2.3,,,, F1,,, * def.inc, ASM.include " * def.inc" *.inc,, \ SystemDesigner \ AVRStudio4 \ AvrAssembler\ Appnotes, ATmega8 m8def.inc, (5 ) ASM,,,, AVR Studio,,, A VR Studio A VR Studio 4 UBRO F (IAR ) Nordic( AVR Assembler ) COFF ( Imagecraft Codevision ELAB ) Intel 16 A VR Assembler, P roject A VR Assembler Setup, , AVR, 3 Intel 16 Motorala 3 Include path, Map List, System Designer P roject, OK (6 ) F7( Build ), ASM, Build,,

160 4 AVR 147 AVR Assembler, (7 ) File Open Files, *.obj, 4.3 AVR A VR A VR CP U, I/ O I/ O, PC, 4.3.1, Debug A VR Simulator Options, A VR Device Device,,, MHz, I/ O, I/ O Stop Watch Enable external Memo, SRAM SRAM I/ O, T WI

161 148 AVR SoC FPSLIC.3.1, A VR 1.5 I/ O, I/ O /, / UA RT/ USAR T S UA RT, U AR T Receive/ T ransmit UAR T SPI SPI, SPI SCK/ MISO/ MOSI/ SS SPI SPI SPI MAST ER, SPI, EE PROM, 22,

162 FPGA System Designer FPGA F PGA, FPGA EDA,, EDA, EDA,, EDA, FPG A FPGA 4 : 5.1.1, Protel, F PGA F PGA, 1. (SCH), Protel,, P rotel,, : I/ O, EDA,,,,,,,,,, 2. (HDL),,,,,,, EDA

163 150 AVR SoC FPSLIC,,,,,,,,, EDA,,,,,, 3. (FSM),,,,, EDA, FSM 4. (Truth table),,, EDA 5. (Flow),,, C, EDA 5, EDA, EDA,, 5.1.2,,, 1.,,,,,,,,,,,, 2.,,,

164 5 FPGA System Designer ,, :,,,, /, ;,,,,,,,,,,,,,,,, 5.1.3,, *.edf,,,,, /,,,,,, if, case,,,,,,,,, ;,, IEEE, EDI F, EDIF 5.1.4, EDA, EDA ; FPG A, FPG A, PCB, FPGA

165 152 AVR SoC FPSLIC ( CLB),, FPG A I/ O, FPGA PCB,,, FPG A, 4, FPGA 5.2 VHDL,,, FPGA, Syst em Designer 3.0 V H DL V erilog H DL V HDL V erilog H DL,, Verilog H DL ASIC, V HDL FPGA, F PSLIC, V H DL V H SIC( Very High Speed Integrated Circuit) V HSIC , ( HDL ), ( V H SIC H ardware Description Language), V H DL 1986, IEEE V HDL, V H DL, , V H DL IEEE , Milstd 454 ASIC V H DL 1993, IEEE 1076, V H DL IEEE , IEEE V H DL V H DL,, V HDL VHDL V H DL, (Design Entity ), CPU : ( Entity Declaration) ( Architecture Body),, System Designer 3.0,, EN TI TY mux IS GENERIC( m : TIME = 1 ns) ; PO RT( d0, d1, sel :IN BIT ; q: OU T BIT ) ; END mux; ARCH IT ECT URE connect OF mux IS

166 5 FPGA System Designer SIGNAL tmp BIT ; BEGIN cale : PROCESS( d0,d1, sel) VARIABLE t mp1, tmp2, tmp3: BIT ; BEGIN tmp1 = d0 AND sel ; tmp2 = d1 AND( NO T sel) ; tmp3 = t mp1 OR tmp2 ; tmp < = tmp3; q < = tmp AFT ER m ; END P ROCESS ; END connect ; 1.,, ENT ITY IS [ GENE RIC( ) ; ] [ PORT ( ) ; ] END [ EN TITY] [ ] ; [ ] 1),,,, GENERIC ( m: TIME : = 1 n s), m 1 ns, tmp1: = d0 AND sel AFT ER m ; d0 sel, 1 ns tmp1, GENERIC tmp1 2), /, : POR T ( {, }: ; {, }: ) ;,,, d0 d1 sel q, 4 : IN( ) O UT ( ) INO UT (

167 154 AVR SoC FPSLIC ), ) BU FF ER (,, V H DL 10, ,, ARCHITEC TUR E OF IS [ ] ; BEGIN [ ] ; END ;, OF, behavioral( ) dataflow( ) str uctural( ) ARC HITECT URE BEGIN, : ARC H IT ECT URE behav OF mux IS SIGNAL nesl :BIT ; BEGIN END behave;,, BEGIN END, 5.2.2, 3, ,,,,,,

168 5 FPGA System Designer EN TI TY add1 IS PO RT( A,B, Cin: IN END add1 ; STD_LOGIC; Co, S : OUT STD_LOGIC) ; ARCH IT ECT URE behave OF add1 IS BEGIN P ROCESS ( A,B,Cin) VARIABLE n :IN TEGER; CONSTANT S_vector: STD_LOGIC_VECTOR (0 T O 3 ) = 0101 ; CONSTANT BEGIN n = 0 ; if( A = 1 ) then end if; n = n + 1 ; if(b = 1 ) then end if; n = n + 1 ; if(cin = 1 ) then end if; n = n + 1 ; S < = S_vector( n) ; Co < = Co_vector( n) ; END P ROCESS ; END behave ; 2. Co_vector : STD_LOGIC_ VECTOR(0 TO 3) = 0110 ;, ( ),,,, EN TI TY add1 IS PO RT( A,B, Cin: IN END add1 ; STD_LOGIC; Co, S : OUT STD_LOGIC) ; ARCH IT ECT URE dataflow OF add1 IS SIGNAL BEGIN tmp1 < = A XOR B; tmp1, tmp2 : STD_LOGIC; tmp2 < = tmp1 AND Cin; S < = tmp1 XOR Cin; Co < = tmp2 OR ( A AND B) ; END dataflow ;

169 156 AVR SoC FPSLIC,, ( ) ( ),,,,,, EN TI TY add1 IS PO RT( A,B, Cin: IN STD_LOGIC; Co, S : OUT STD_LOGIC) ; END add1 ; ARCH IT ECT URE structure OF add1 IS BEGIN COMPONENT and2 PORT (a : IN STD_LOGIC; b : IN STD_LOGIC; c : IN STD_LOGIC) ; END COMPONENT ; COMPONENT or2 PORT (a : IN STD_LOGIC; b : IN STD_LOGIC; c : IN STD_LOGIC) ; END COMPONENT ; COMPONENT xor2 PORT (a : IN STD_LOGIC; b : IN STD_LOGIC; c : IN STD_LOGIC) ; END COMPONENT ; SIGNAL tmp1, tmp2, tmp3 : STD_LOGIC ; BEGIN U1 : xor2 PORT MAP( A, B, t mp1) ; U2 : and2 PORT MAP ( tmp1, Cin, t mp2 ) ; U3 : xor2 PORT MAP( tmp1, Cin, S) ; U4 : and2 PORT MAP ( A, B, tmp3) ; U5 :or2 PORT MAP (t mp2, tmp3, Co) ; END structure ; V H DL, 3 : 1. V H DL,

170 5 FPGA System Designer ), V HDL, USE LIBRARY ; V H DL,, 1) V H DL 5 : IEEE S TD ASIC WORK (1 ) IEEE IEEE, S TD_ LOGIC_1164 N UMERIC_S TD MAT H_COM PLEX MAT H_R EAL S TD_LOGIC_ 1164 N UME RIC_STD IEEE, Synopsys STD_ LOGIC _ARIT H S TD_ LOGIC_SIGNED STD_ LOGIC _U NSIG NED, IEEE, IEEE (2 ) STD STD VHDL, STANDARD TEXTIO STANDARD BIT BIT_VECTOR ; TEXTIO / TEXTIO, ; STANDARD, (3 ) ASIC V H DL,, ASIC, ASIC, (4 ) WORK WORK V H DL V HDL, WORK,, WORK WORK V H DL WORK, WORK (5 ) VD HL,,,,,, 2) STD WORK,, : LIBRARY I EEE ; USE IEEE.STD_LOGIC_1164.AL L ;,, LIBRARY ; USE, ( ),

171 158 AVR SoC FPSLIC USE..ALL ; 2. IEEE S TD_LOGIC_1164, V HDL V HDL,, STD_LOGIC_1164 ST ANDARD, P ACKAGE ; END [ ] ; IS P ACKAGE BODY IS ; END [ ] ;, ;,,,,, P ACKA GE thr ee_state_logic IS T YPE bit3 IS ( 0, 1, Z ) ; FUNCTION END t hree_state_logic ; and (a, b: bit3) RE TU RN bit3; P ACKA GE BODY thr ee_state_logic IS FUNCTION BEGI N I F E LSIF and (a, b: bit3) RE TU RN bit3; (a = 1 ) AND( b = 1 ) T HEN RET UR N 1 ; ( a = 0 ) OR( b = 0 ) T H EN RE TU RN 0 ; E LSE RE T URN Z ; END IF ; END and ; END three_ state_logic ;, USE, USE.. ; 3. ( CO NFIGU RATION ),

172 5 FPGA System Designer ,, V H DL,,,,,, F OR : USE EN TITY. [ ( ) ] ; CON FIG URATION OF IS END F OR END FOR ; ; ;,, ( Block ) ( Components), EN TITY counter IS PORT( load, clear, clk :IN STD_LOGIC ; END coun ter ; ARCH IT ECT URE BEGIN P ROCESS (clk) data_in: IN IN TEGER ; data_out : OU T INT EGER) ; count_255 OF counter IS VARIABLE count : INT EGER = 0; BEGIN IF( clear = 1 ) T H EN count = 0; E LSIF (load = 1 ) T H EN count = da ta_in; E LSIF (clk EVENT ) AND(clk = 1 ) T H EN I F(count = 255) T H EN E LSE count = 0 ; count = count + 1; END IF ; E ND IF ; data_out < = count ; END PROCESS;

173 160 AVR SoC FPSLIC END count_255; ARCH IT ECT URE BEGIN P ROCESS (clk) count_64 K OF counter IS VARIABLE count : INT EGER = 0; BEGIN IF( clear = 1 ) T H EN count = 0; E LSIF (load = 1 ) T H EN count = da ta_in; E LSIF (clk EVENT ) AND(clk = 1 ) T H EN I F(count = 65535) T H EN E LSE count = 0 ; count = count + 1; END IF ; E ND IF ; data_out < = count ; END PROCESS; END count_64 K; CON FIG UR AT ION small_coun t OF counter IS FOR coun t_255 ;, : 8 ; 16 :,,, VHDL V H DL,, V HDL, V HDL,, V H DL, 4 : ( Constant ) ( Signal) ( Variable) ( File),, ; 1.,,,,,,, :

174 5 FPGA System Designer CONS TAN T : = ; : CONSTANT Vcc : REAL = 5.0; CONSTANT Delay : TIME = 25 ns ; 2.,, ( ) : SIGN AL : = ; : SIGNAL SIGNAL clk:bit = 1 ; GND :BIT = 0 ;,, = ;, < =,, 3.,,,,, : V ARIABLE : = ; : VARIABL E a, b :IN TEGER ; VARIABL E count : INT EGER R ANGE 0 TO 255 = 0; 4. V HDL 93,,, : F ILE : IS[ ] ; FILE, ;, ; :, in out ;, V H DL,

175 162 AVR SoC FPSLIC VHDL V H DL, V H DL,, 1. V HDL, 10, VHDL 32, , E E ASCII, f s ps ns s ms sec min hr NO T E WAR NIN G E R ROR F AI L UR E ( : 0 ; : > 0 ) 2. V H DL, : TYP E {, } ; ( Enumerated) ( Integer ) ( Real) ( Array) ( Acess ) ( File) ( Recode) ( Time) 3., SUBTYPE IS [ ] ;, S TD_LOGIC_VECTOR : SUBTYPE da tabus IS STD_LOGIC_VECTOR (7 DOWNTO 0) ; SUBTYPE num IS INT EGER RANGE 0 T O 9 ;,,

176 5 FPGA System Designer V H DL,,, V H DL, S TD_ LOGIC_ 1164 S TD_ LOGIC_ARIT H S TD_LOGIC_ U NSIGNED ST D_ LOG IC_1164 T O_ST D L OGIC VE CT O R( A) T O_BI T V EC T OR ( A ) T O_ST D L OGIC( A ) T O_BI T ( A ) BI T _V EC T OR ST D_ L OGIC_V E CT OR ST D_L OGIC_ V EC T OR BI T _V E CT OR BI T ST D_ L OGIC ST D_L OGIC BI T ST D_L OGIC_ ARI T H CO NV_ST D_ LOGIC_ V EC T OR ( A, ) CO NV_I N T EG E R( A ) I N T E GE R U N SIGN E D SIGN E D ST D _ LOG IC_ V EC T OR UN SIGN E D SIGN E D I N T EG E R ST D_L OGIC_ U NSIG NE D CO NV_I N T EG E R( A ) ST D_L OGIC_ V EC T OR I N T EG E R 5. IEEE STD_LOGIC STD_LOGIC_VECTOR, BIT 0 1 X,,,, IEEE 1993 ( IEEE STD1164 ), STD_LOGIC 9 : U ; X ; 0 0 ; 1 1 ; Z ; W ; L 0 ; H 1; - STD_ LOGIC STD_ LOGIC_ VECTOR IEEE, V HDL,,

177 164 AVR SoC FPSLIC VHDL V HDL,, V H DL, V H DL 4, ( Logical) ( Relational) ( Arithmetic) ( Connectenation ) 1. V H DL 7, A ND XOR OR X NOR N AND NO T N OR BI T BOOLEAN S TD_LOGIC, 2. V H DL 16, ( ) - * / ABS SL L SR L MOD SL A R E M SR A * * + ( ) RO L ROR, ( ), /,, (, ) SLL( ) SRL ( ) SLA ( ) SRA ( ) ROL( ) ROR( ),,

178 5 FPGA System Designer BIT BOOLEAN, 3. V H DL 6, = / = < < = > > =,, BOOLEA N, T RUE FALSE = / =, ( INTEGE R ) ( R EAL ) ( BI T ) S TD_LOGIC 4. V H DL &,,, SIGNAL a, b, c,d : STD_LOGIC; SIGNAL q: STD_LOGIC_ VECT OR(3 DOWN TO 0 ) ; q < = a & b & c & d; 4 S TD_ LOGIC a b c d, q 5. V H DL,,, * * NO T ABS * / MOD R E M + ( ) - ( ) + ( ) - ( ) & SLL SR L SL A SRA RO L ROR = / = < < = > > = A ND OR N A ND N OR XOR X NOR V H DL, V H DL

179 166 AVR SoC FPSLIC, ;,,, ;, V H DL, I F CASE LOOP 1. < = ; = ; < = =, ; < = =,, ;,, 2. IF I F V HDL IF I F ELSE IF I F TH EN ; [ ELSIF T H EN ; ] [ ELSIF T H EN ; ] [ ELSE ; ] END IF ; I F IF END I F I F END IF ELSIF ELSE,, ; ELSIF ELSE I F :

180 5 FPGA System Designer IF sel = 00 ) T H EN ELSIF ELSIF ELSE q < = d0 ; ( sel = 01 ) T H EN q < = d1 ; ( sel = 10 ) T H EN q < = d2 ; q < = d3 ; END I F; IF, sel, d0 d1 d2 d3 q 3. CASE CASE, IF, CASE, IF CASE CASE IS WH EN 1 = > ; WH EN 2 = > ; WH EN 3 = > ; WH EN OT HERS = > ; END CASE ; CASE CASE IS,, END CASE, WH EN CASE 3 : WH EN, ; WH EN CASE, ; CASE WH EN, OT HE RS CASE : CASE sel IS W H EN 00 = > q < = d0 ; W H EN 01 = > q < = d1 ; W H EN 10 = > q < = d2 ; W H EN 11 = > q < = d3 ; END CASE ;

181 168 AVR SoC FPSLIC LOOP LOOP LOOP 1) FOR [ ] : FOR IN LOOP ; END LOOP [ ] ;,, LOOP, IN : ASUM : FOR i IN 1 TO 9 LOOP s um = i END LOOP ASUM ; + sum;, i, 1,2,, 9 9, s um = i + sum ) WHILE [ ] : W HILE ; END LOOP [ ] ; LOOP LOOP,, ;, : i = 1 ; sum = 0 ; sbcd: W H ILE ( i < 10 ) LOOP sum = i + sum ; i = i + 1 ; END LOO P sbcd; FOR LOOP, 1 9 i < 10, i i = i NEXT LOOP, NEXT, NEXT [ ] [ W HEN ] ; NEXT, NEXT, W HEN W HEN : NEXT NEXT,

182 5 FPGA System Designer FO R i I N T O 255 LOOP IF ( done( i) = TR UE) T H EN E LSE NEXT ; done(i) = TRU E ; E ND IF ; q( i) < = a(i) AND b(i) ; END LOO P;, LOOP, NEXT W HEN, NEXT LOOP 6. EXIT ; EXIT LOOP NEXT, EXIT, LOOP EXI T EXIT [ ] [ W HEN ] ; EXI T WH EN, LOOP,, LOOP : FO R i I N 0 T O 255 LOOP IF ( int_a < = 0 ) E LSE E ND EXIT ; int_a = int_a - 1 ; T H EN q(i) < = / REAL(a * i) ; IF END LOO P;, int_a 0 int_a 0, IF, EXIT, LOOP, EXIT, V HDL,, V HDL : ( PROCESS) ( Concurrent Signal Assignment) ( Conditional Signal Assignment ) ( Selective Signal Assignment) ( Concurrent P rocedure Call) (BLOCK) ( ASSE RT ) ( COMPO NENT ) 1. (PROCESS),,

183 170 AVR SoC FPSLIC BEGIN : ] PROCESS [ ( ) ] [IS ] [ ; ] ; END PROCESS [ ] ;,,,, ; WAIT WAIT [ ON ] ; WAIT [ U NTIL ] ; WAIT [ FOR ] ; : WAIT ON, ; WAI T U NTIL, ; WAI T FOR, WAIT FOR,, WAIT FOR, WAIT, WAIT ;,, D : ; WAIT : EN TI TY d_ff IS PORT( d, clk :IN BIT ; END d_ff; q, nq: OU T BIT) ; ARCH I T ECT UR E desc rib1_dff OF d_ff IS BEGIN P ROCESS (clk) BEGIN IF ( clk = 1 ) AND( clk EVEN T) T H EN q < = d; nq < = NO T d; END IF ; END P ROCESS ; END describ1_dff; : ARCH I T ECT UR E desc rib2_dff OF d_ff IS BEGIN

184 5 FPGA System Designer P ROCESS BEGIN IF clk = 1 ) AND( clk EVEN T) T H EN q < = d; nq < = NO T d; END IF ; WAIT ON clk ; END P ROCESS ; END describ2_dff; D clk 1, 2. (Concurrent Signal Assignment),, : ARCH IT ECT URE behav OF a_var IS BEGIN output < = a(i) ; END behave ; ARCH IT ECT URE behav OF a_var IS BEGIN PROCESS(a, i) BEGI N output < = a(i) ; END PROCESS; END behave ;, < =,, < =, PROCESS, a i,,, output,, : a < = b + c ; d < = e * f ; ;,,

185 172 AVR SoC FPSLIC,, 3. (Conditional Signal Assignment), < = 1 W HEN 1 ELSE 2 W HEN 2 ELSE 3 W HEN 3 ELSE n ; ELSE WH EN, ;,, : EN TI TY mux4 IS PORT(i0, i1, i2, i3 :I N STD_LOGIC; END mux4 ; sel : IN STD_LOGIC_ VECT OR(1 DOWN TO 0) ; q : OU T STD_LOGIC) ; ARCH IT ECT URE rtl OF mux4 IS BEGIN END rtl ; q < = i0 WH EN sel = 00 ELSE i1 WH EN sel = 01 ELSE i2 WH EN sel = 10 ELSE i3 WH EN sel = 11 ELSE X ; IF :, ELSE ; IF,,, 4. (Selective Signal Assignment) CASE,, WIT H SELECT < = 1 WH EN 1, 2 WH EN 2,

186 5 FPGA System Designer EN TI TY mux4 IS PORT(i0, i1, i2, i3 :I N STD_LOGIC; END mux4 ; n WH EN n sel : IN STD_LOGIC_ VECT OR(1 DOWN TO 0) ; q : OU T STD_LOGIC) ; ARCH IT ECT URE rtl OF mux4 IS BEGIN WIT H el SE LECT END rtl ; q < = i0 WH EN 00, i1 WH EN 01, i2 WH EN 10, i3 WH EN 11, X W H EN OT H ERS ; sel i0 i1 i2 i3 q,,, CASE 5. (Concurrent Procedure Call), ( ) ;, ; IN OU T INO UT, ;, : ARCH IT ECT URE BEGIN vector_to_int(z,x_flag, q) ; END ; vector_to_int z, q; x_flag,, 6. (COMPONENT),,,,

187 174 AVR SoC FPSLIC V H DL, : COM PONENT GENERIC ( ) ; POR T ( ) ; END COM PONEN T [ ] ; : : [ GENERIC MAP ( ) ] PORT MA P ( ) ;, GENE RIC ; PORT,,,, V HDL : 1) POR T MAP COMPO NENT, U1 a int1; b int2; c out EN TI TY example IS PORT(in1, in2 : IN STD_LOGIC; out : OU T STD_LOGIC) ; END example ; ARCH IT ECT URE structure OF example IS COMPONENT and2 GENERIC( delay: time) ; PORT (a : IN STD_LOGIC; b :IN STD_LOGIC; c: IN STD_LOGIC) ; END COMPONENT ; BEGIN U1 : and2 GENE RIC(10 ns) PORT MAP (in1, in2,out) ; END structure ; 2) POR T MAP,, :

188 5 FPGA System Designer ARCH IT ECT URE structure OF example IS COMPONENT BEGIN and GENERIC( delay: time) ; PORT (a : IN STD_LOGIC; b :IN STD_LOGIC; END COMPONENT ; U1 : and2 END structure ; c: IN STD_LOGIC) ; GENE RIC(10 ns) PORT MAP (a = > in1, b = > in2, c = > out) ; 7. (ASSERT),, ASSER T [ RE POR T ] [ SEVERITY ] ;,,,, : EN TI TY d_ff IS PORT( d, clk,preset, clear: IN BIT ; END d_ff; q, nq: OU T BIT) ; ARCH I T ECT UR E desc rib3_dff OF d_ff IS BEGIN ASSERT NOT( ( preset = 0 ) AND( clear = 0 ) ) REPO RT Control error SEVERITY Error ; P ROCESS ( preset, clear, clk) BEGIN IF ( preset = 0 ) AND ( clear = 1 ) T HEN q < = 1 ; nq < = 0 ; ELSIF ( preset = 1 ) AND (clear = 0 ) T H EN q < = 0 ; nq < = 1 ; ELSIF (clk = 1 ) AND (clk EVEN T) T H EN q < = d; nq < = NO T d; END IF ; END P ROCESS ; END describ3_dff; ASSE RT

189 176 AVR SoC FPSLIC 8. (BLOCK),,, BLOCK [ : ] BLOCK [ ] [ ] [ ; ] ] ; [ ] [ ; ] ] ; [ ] ; BEGIN { }; END BLOCK[ ] ; : ; GENERIC GENE RIC MA P POR T P OR T MAP,, USE EN TI TY add IS PORT( : IN STD_LOGIC; END add ; B:IN Cin: IN Co: OU T STD_LOGIC; STD_LOGIC; STD_LOGIC; S : OU T STD_LOGIC) ; ARCH IT ECT URE da taflow OF add IS BEGIN ex : LOCK PO RT ( _A : IN a_b: IN STD_LOGIC; STD_LOGIC; a_cin : IN STD_LOGIC ; a_co: OUT STD_LOGIC; a_s: OU T STD_LOGIC) ; PO RT MAP( a_ A = > A, a_b = > B, a_cin = > Cin, a_co = > Co, a_s = > S) ; SIGNAL BEGI N t mp1, t mp2 :STD_LOGIC; lable1 : PROCESS( a_ A, a_b) BEGIN tmp1 < = a_ A XOR a_b; EN D PROCESS lable1 ; lable2 : PROCESS( tmp1, a_cin) BEGIN tmp2 < = tmp1 AND a_cin ;

190 5 FPGA System Designer EN D PROCESS lable lable3 : PROCESS( tmp1, a_cin) BEGIN a_s < = tmp1 XOR a_cin; EN D PROCESS lable3 ; lable4 : PROCESS( a_ A, a_b, t mp2 ) BEGIN a_co < = tmp2 O R ( a_ A AND a_b) ; EN D PROCESS lable4 ; END BLOCK ex ; END dataflow ;, 4 4,,,, 9. (GENERATE),, V HDL [ : ] GENERAT E ; END GENERATE [ ] ; :,, V HDL : FOR IF FOR ; IF 1) FOR F OR [ : ] FOR IN GENERAT E ; END GENERATE [ ] ;,,, ; GENERA TE ; F OR END GENERATE [ ] GENE RATE 4, FOR,,

191 178 AVR SoC FPSLIC D 4, 4, Q ENT I TY shift_reg IS PORT( d1 :IN STD_LOGIC; cp :IN STD_LOGIC; d0: OU T STD_LOGIC) ; ARCH ITE T URE structure OF shift_reg IS BEGI N COM PO NENT dff PO RT( d: IN STD_LOGIC; clk: IN STD_LOGIC ; q: OU T STD_LOGIC) ; END COMPONENT ; D 4 SIGNAL q: STD_LOGIC_VECTOR (4 DOWNTO 0 ) ; q(0 ) < = d1; lable1: FOR i IN 0 TO 3 GE NERA T E dffx :dff PORT MAP ( q( i), cp, q(i + 1 ) ) ; END GENERA TE lable1; d0 < = q( 4) ; END structure ;, F OR, FOR q d1 d0 ; F OR 4 2) IF I F [ : ] IF GENE RATE ; END GENERATE [ ] ; I F,,, :,

192 5 FPGA System Designer ,,,, q d1 d0, d1 d0 F OR IF ENT I TY shift_reg IS PORT( d1 :IN STD_LOGIC; cp :IN STD_LOGIC; d0: OU T STD_LOGIC) ; ARCH ITE T URE structure OF shift_reg IS BEGI N COM PO NENT dff PO RT( d: IN STD_LOGIC; END COMPONENT ; clk: IN STD_LOGIC; q : OU T STD_LOGIC) ; SIGNAL q: STD_LOGIC_VECTOR (3 DOWNTO 1 ) ; lable1: FOR i IN 0 TO 3 GE NERA T E IF ( i = 0) GENER AT E dffx: dff PORT MAP( d1, cp, q(i + 1 ) ) ; END GENERA TE ; IF ( i = 3) GENER AT E dffx: dff PORT MAP( q(i), cp,d0 ) ; END GENERA TE ; IF ( i/ = 0 ) OR( i/ = 3 ) GENERAT E dffx: dff PORT MAP( q(i), cp,q(i + 1) ) ; END GENERA TE ; END GENERA TE lable1; END structure ;, F OR IF i = 0 i = 3, D, d1 POR T MAP ;, d0 POR T MA P 5.3 System Designer 3.0 V HDL, System Designer 3.0

193 180 AVR SoC FPSLIC 3.2.3, FPG A, Text Editer ( ), V H DL, Figaro, H DL Planner, 1. HDL 1) Text Editor, V H DL,,, : ntity name : Archit ecture: behaviour, Port name: I/ O Mode: I/ O, I/ O in, out, inout Type : I/ O : std_logic std_logic_vector integer character Boolean bit bit_vector, Add Port, Ports,, Ports, Remove Port, Creat, 5.3.1, HDL Planner,

194 5 FPGA System Designer , Cancel, H DL Planner :, Entity Name andgat e, Architecture behaviour : Port Name a ; Mode in; Type std_logic, Add Port, Ports a : in std_logic, a b a c Mode, out Creat, H DL : LIBRAR Y ieee ; USE ieee.std_logic_1164.all ; - - Do not delete following library and use clauses. library work; use work.components.all; use work.at94k_pkg.all ; ENTITY andga te IS PORT ( a : in st d_logic; b : in st d_logic;

195 182 AVR SoC FPSLIC c ou t st d_logic ) ; END andgate ; ARCH ITECT URE behaviour of andgate - - Add SIGNAL definitions here BEGI N - - Enter Architectural definition here END behaviour; IS BEGIN END behaviour c < = a and b; ;, atmel.vh d,,, 2) Figaro IDS, FPGA FPGA (1 ) FPGA Files Settings User Library Settings Files Set tings : pen EDIF Netlist : Browse,.edf ; Open Saved FPG A design file(.fgd) :.fgd Browse

196 5 FPGA System Designer fgd.fgd, Run FPGA place & route tool in st and alone mode: FPG A Figaro, ; : F PGA, ;, User Library Settings, (2 ) HDL, Files Settings Run FPGA place & route tool in stand alone mode, OK, Figaro, Figaro, Figaro File Design Setup,, New Design,, 5.3.5, / F PSLIC, Configuration A T94K; Tools Flow Exemplar MTI; Files of Type EDIF N etlist( *.edf) OK,, 5.3.4, OK, ; (3 ) Figaro HDL, Tools H DL Planner, H DL 1 ( ) ;

197 184 AVR SoC FPSLIC.3.5, atmel.vhd 2. System Design 3.0, Palnner : H DLPlanner,, ; EasyPlanner,,,, 1) HDLPlanner H DLPlanner, HDLPlanner

198 5 FPGA System Designer H DL,,, V HDL Verilog, H DLPlanner,,, (1 ) HDL Planner ile Edit : : ( Save as ) ( Open ) ( N ew ) ( P rint ) ( Updat e) ( Exit) : ( Cut) ( Copy ) ( Paste) ( Find ) ( Replace) ( Undo) ( Redo) File Edit, : Go To Line( ) :,, ; Scroll to Start( ) :, ; Scroll to End ( ) :, HDL V H DL,, V HDL, V H DL ool T ool : Invoke Macro generators :,,,,.fgd ; Report Macro information:,, / ; Options:, xemplar: Synthesis Tip : ; Integrate a use Macro: Views Reports H elp (2 ) HDL Planner, ; ;,, ;,, (3 ) HDL Planner 5.3.6

199 186 AVR SoC FPSLIC ext :, small medium large default; Category: ; Component : ; Define :, Component, ; Instance:, ; Define, Instance 2) EasyPlanner EasyPlanner,,,,, ;,,, HDLPlanner EasyPlanner, EasyPlanner (1 ),, (Design ) : N ew : ; Open: ;

200 5 FPGA System Designer Save ; Open Log Window : ; Exit : EasyPlanner ( Option ) : Open U ser Library: ; Generat e Design Notes: html ; Generat e In stantiated Macros: Figaro ( View) : Clear View : CIV ( Help) : H elp Contents: ; About : (2 ) ( LCV) :,,,,, ( CIV ) :,, CIV (DA V) :,, LCV CIV, DAV (3 ) : LCV CIV, DA V, : CIV,, Inspect, OK, : CIV, Delet e, CIV DAV HDLPlanner,,,, H DL Planner 1. ( ) (1 ) System Design 3.0, ( 2) Figaro IDS, FPGA ( 5.3.3), Files Set ting R un FPG A place & route tool in st and alone mode, U ser Library Set ting s user94k.lib, OK (3 ) Figaro H DL Tool H DLPlanner, H DL

201 188 AVR SoC FPSLIC V HDL library, : LIBRARY libraryname ; USE libraryname.packagename.all ; libraryname ieee ; library.packagename.all ieee.std_logic_1164.all (5 ), V H DL Enitity, U SE : - - Do not delete following libr ary and use clauses. - - library work; use work.components.all ; ENTIT Y entity Name IS PORT ( InPor t1, InPort2 : IN type; OutPort1, OutPort2 : OUT type ) ; END e ntityname; EN TITY andgate IS PO RT ( a,b : in std_logic; c: out std_logic ) ; END andga te; (6 ), V H DL Architecture, : ARCHITECTURE archname OF entityname IS Add SIG NAL definitions he re - - BEGIN Enter A rchitectural definition here - - END behaviour; ARCHITECTURE behaviour OF andgate IS BEGIN c < = a and b ; END behaviour; (7 ) File Save As, VHDL

202 5 FPGA System Designer File Name andgate.vhd, Directory, OK,,.vhd : andgate.vhd; atmel.vhd 2.,, ;,, : (1 ) 3 (2 ) : Category Counter, Component CounterUp Cou nter, counting Upward; Define, : library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_ arit h.all; use ieee.std_logic_unsigned.all; EN TITY counteru p_prl IS generic ( WIDT H : integer = 4) ; port( RN : IN std_logic ; CLK : IN st d_logic ; Q : OU T std_logic_vector ( WIDT H - 1 downto 0 ) ; RCO : OU T std_logic ) ; END counteru p_prl ; ARCH IT ECT URE behv OF counter Up_prl IS constant clockedge : std_logic = 1 ; constant setorresetlevel : std_logic = 0 ; constant setorreset : integer = 0; SIGNAL Qt mp : std_logic_vector( WIDT H - 1 downto 0 ) ; begin process( CLK, RN ) begin if( RN = seto rresetlevel) t hen Qtmp < = CONV_STD_LOGIC_VECTOR ( setorreset, WIDT H ) ; elsif (CLK = clocke dge a nd CLK even t) t hen Qtmp < = Qtm p + 1 ; end if; if ( Qtmp = CONV_STD_LOGIC_ VECT OR( - 1, WIDT H ) ) then RCO < = 1 ; else RCO < = 0 ;

203 190 AVR SoC FPSLIC end if end process ; Q < = Qtmp; end behv; (3 ) end behv,, : LIBRARY ieee; USE ieee.std_logic_1164.all ; library work; use work.components.all ; ENTITY entityname IS PORT ( RESE T : IN std_logic ; CLOCK : IN std_logic ; COUNT : OUT std_logic_vector( 3 downto 0 ) ; RCOU T : OUT std_logic ) ; END entityname ; ARC H IT ECT URE behaviour OF entityname IS BEGIN END behaviour; ( 4) BEGIN, Instance, Instance Name ; Entity ; WIDT H ; Assigned to... 4, RN RESET, CLK CLOCK, Q CO UN T, RCO RCOU T ( 5 ) OK, , ( 6),, Declare Skip, (7 ), (

204 5 FPGA System Designer ) : library ieee ; use ieee.std_ logic_1164.all; use ieee.std_logic_arith.all ; use ieee.std_ logic_unsigned.all ; ENTITY counteru p_prl IS generic (WIDT H : integer = 4 ) ; port( RN : IN st d_logic; CLK : IN std_logic ; Q : OU T std_logic_vector ( WIDT H - 1 downto 0 ) ; RCO : OU T std_logic ) ; END counteru p_prl ; ARCH ITECT URE behv OF counteru p_prl IS constant clockedge : std_logic = 1 ; constant setorresetlevel : std_logic = 0 ; constant setorreset : integer = 0; SIGNAL Qt mp : std_logic_vector( WIDT H - 1 downto 0 ) ; begin process( CLK, RN ) begin if( RN = setorr esetlevel) th en Qtmp < = CONV_STD_LOGIC_VECTO R( seto rreset, WIDT H ) ; elsif ( CLK = clockedge and CLK event) then Qtmp < = Q tmp + 1 ; end if; if ( Qtmp = CONV_STD_LOGIC_VECTO R( - 1, WIDT H ) ) then

205 192 AVR SoC FPSLIC RCO else RCO < = 0 ; end if ; end process ; Q < = Qtmp; end behv; LIBRAR Y ieee ; USE ieee.std_logic_1164.all ; library work; use work.com ponents.all; ENTITY entityname IS PORT ( RESE T : IN std_logic ; CLOCK : IN std_logic ; COUNT : OUT std_logic_vector( 3 downto 0 ) ; RCOU T : OUT std_logic ) ; END entityname ; ARCH ITECT URE behaviour OF entityname IS component counteru p_prl GENERIC (WIDT H : integer = 4) ; PORT ( RN : I N std_logic ; CLK : IN std_ logic ; Q : OUT std_logic_vector( WIDT H - 1 downto 0 ) ; RCO : OU T st d_logic ) ; END component ; BEGIN InstName : coun ter Up_prl GENERIC MAP ( WIDT H = > 4 ) PORT MAP ( Q = > COUN T, RCO = > RCO UT, CLK = > CLOCK, RN = > RESE T ) ; END behaviour; 3.,,, Figaro

206 5 FPGA System Designer ,, 1), Figaro Tool Entity Generator, AT94K, : (1 ) AT94K , : Arithmetic CacheLogic Counter DSP I/ O Logic Memory Regist er (2 ), (3 ) H elp (4 ) Macro Name (5 ) Pin Map File Name

207 194 AVR SoC FPSLIC User Libra ry, ,, Browse, Figaro, ibrary Search Path:, Add Before... Add After... ;, Remove Library Names: Add..., ; Crea t...,, Library Names ; Remove, ; O K,,, :, Library Setup Path Add Before...,, , d: \ training\ fpgaalone, user94k.lib, OK,, Add All, ( ) Library Search Path, Library N ames, Library Search Path,, Library Names Crea t,, Library Names, test, OK test ( ) Library N ames OK, ( ) User Library

208 5 FPGA System Designer (7 ) Options H ard Macro (8 ) Gener ate,,,

209 196 AVR SoC FPSLIC *.vht, *.vhd.vht,, :,,.vht 2) Ram, : (1 ) (2 ) Figaro, File Design Setup (3 ) Figaro Tool Generator (4 ) Memory; Ram Dual Port ;, Address WIDT H 6, WIDT H 16, External decoding Cluster, RAM Type Synchronous; Macro Nam ramblock (5 ), H ard Macro (6 ) Generator (7 ) H DLPlanner ( ),, Category U SER: user94k, Component ramblock, Instance (8 ) O K, ramblock (9 ) : LIBRAR Y ieee ; USE ieee.std_logic_1164.all ; library work; use work.components.all; ENTITY entityname IS PORT ( dataout : out std_logic_vector(15 downto 0 ) ; addressin: in std_logic_vector (5 dow nto 0) ; addressout :out std_logic_vector (5 dow nto 0) ; clk : in std_logic ; datain : in std_logic_vector( 15 downto 0) ; read : in std_logic ; write : in std_logic ) ; END entityname ; ARCH ITECT URE archname OF entityname IS co mponen t ramdesign port ( DOUT : out std_logic_vector( 15 downto 0) ; AIN : in std_logic_vector (5 downto 0) ; AOUT : in std_logic_vector(5 downto 0) ;

210 5 FPGA System Designer CLK in std_logic ; DIN : in std_logic_vector (15 downto 0) ; OEN : in std_ logic ; WEN : in st d_logic ) ; end component ; BEGI N InstName : r amdesign_pr l PO RT MAP ( DOUT = > Sig_DOUT, AIN = > Sig_AIN, AOUT = > Sig_AOUT, CLK = > Sig_CLK, DIN = > Sig_DIN, OEN = > Sig_OEN ; WEN = > Sig_W EN ) ; END behaviour; : component ramdesign end component DO UT = > Sig_DOU T WEN = > sig_wen *.vht, : DO UT = > dat aout ; AIN = > addressin ; AO UT = > addressout ; CLK = > clk ; DIN = > datain ; OEN = > read ; W EN = > write 4. EasyPlanner 1) (1 ) (2 ), untitle.vhd (3 ),,, CIV, (4 ) 2) RAM ( V H DL ) : (1 ) P roject Open EasyPlanner,, , V H DL O K, EasyPlanner ( 5.3.7) (2 ), Designs New Design,,,,

211 198 AVR SoC FPSLIC,, Memory, ram rom ram, 4 sdram,,, ( ), (4 ) Design Save Design,.vhd

212 FPGA System Designer System Designer 3.0 System Designer 3.0 ModelSim Mentor ModelSim 5.6e, ModelSim 5.6e 1.,,, HDL (1 ),, ModelSim ; ;, (2 ),, (3 ), (4 ), ; X, 2. V H DL Verilog V HDL : IEEE ; ; ; ; 3. Tcl ModelSim 5 : IEEE Verilog V H DL Vital 2000 Tcl/ Tk 8.3, ModelSim 5.6e

213 200 AVR SoC FPSLIC ModelSim ModelSim, ModeslSim :, ModelSim, ModelSim ModelSim 1. : / 1) View Hide/ Show Workspace, / 3 : P roject Library tructure Structure, 2) / /,, VSIM >,,, :, ModelSim.tcl, ModelSim.ini,, transcript,

214 6 FPGA System Designer File T ranscript Save Transcript As, FileT ranscript Save T ranscript, 3), ModelSim 4) ModelSim 5), 2. 1) File N ew : Folder: folder Source : V HDL Verilog P roject : Library: Open: File: HDL P roject : *.mpf Da taset : Close: P roject : Da taset : Import : Library: FPGA Save: Da taset : Delet e: P roject : Change Directory: Tran script : Save T ranscript : Save T ranscript As : Clear Transcript : Add to project : File: Simulation Configuration: Folder: Recent Directory Recent P roject : Quit : ModelSim.

215 202 AVR SoC FPSLIC Edir 3) View All Windows : ModelSim Da taflow : Da taflow List : List P rocess: Process Signals : Signals Source : Source Structure: Structure V ariable: Variable Wave: Wave Da tasets: Datasets H ide/ Show Workspace: / Encoding:, P roperties: 4) Compile Compile: HDL Compile Options: V H DL Verilog Compile All: Compile Order: Compile Report : Compile Summary: 5) Simulate Simulate load: Simulation Options : Run: Run:,, Simulate Simulation Options Run All:, stop Continue: Run-Next : Step: Step Over: Restart : 0 Break : End Simula tion: 6) Tools Waveform Compare:

216 6 FPGA System Designer Breakpoints: Option: Tran script File: Save File: Saves Lines: Line Prefix: Update Rate : ModelSim Prompt : ModelSim VSIM P rompt : VSIM H TML :, Edit P references : Save Preferences: ModelSim Tcl 7) Windows Help Windows H elp 6.1.3, ModelSim,,,,,,,,,,,,,, 4 : (1 ).mpf (2 ) H DL,,, (3 ),, ModelSim (4 ) HDL,,.mpf,.mpf : HDL README ( test ) : (1 ) ModelSim System Designer 3.0, Model- Sim :, Tools, run H DL Simula-

217 204 AVR SoC FPSLIC tor ModelSim, Simula tor, ModelSim 5.6e, ModelSim 5.6e (2 ) Jumpstart M, ModelSim, ModelSim

218 6 FPGA System Designer : Creat a Project, Open a Project Open Documents ModelSim PDF (3 ) Creat New File,, : P roject Name roject Loca tion, Browser efault Library N ame, wor k, Project N ame test, D: \ training \ fpgaalone, work, OK (4 ) Item, : Item reat New File, ( V HDL Viewlog TCL text ),, Add Existing File Creat Simulation,,,,,, Creat New Folder,,,,,

219 206 AVR SoC FPSLIC 2, Add Existing File (5 ), File Name, Browser... Add file as type default Folder, : eference form current location, Copy to project directory, 2 ;, 1 Browser... test.vhd, OK, ModelSim, ModelSim ( 6 ) Compile Compile All,, Status? ;, Simulator Simulate,, (7 ) work,, Load ModelSim 2 ( Project Library) 3 ( Sim),

220 6 FPGA System Designer ModelSim > VSIM >, (8 ), Simulator End Simulate, ModelSim > (9 ), File Close P roject,, Yes ; No, VHDL, V HDL, ModelSim

221 208 AVR SoC FPSLIC : \ Syste mdesigner \ modeltech \ examples \ coun ter.vhd 1., work H DL, 2.,,, : File Add to Project File,, HDL, \ SystemDesigner \ modeltech\ examples \ counter.vhd OK Compile Compile selected, 3.,, Simulate Simula te, Design, work,,, Load,, ModelSim VSIM > 4., ModelSim View, View All : Signals Wave

222 6 FPGA System Designer Signals, View Signals, Signals, Signals 1) Signals (1 ) : ( Structure ), ;, Wave,, Source,, List Wave, ; (2 ) H DL HDL : V HDL ; V erilog ; ( ) V H DL Verilog ;, (3 ) Signals Edit Force,,,, Edit No Force : Signal Name V alue, ind F reeze:, Verilog V H DL, modelsim.ini Drive:,, V HDL, V HDL Deposite :,,

223 210 AVR SoC FPSLIC Delay For: Cancels Aft er: HDL Wave List WLF Add : Selected Signals Signal ; Signals in Region Structure ; Signals in Design / VSIM >, Wave List WLF : add list add wave add log < > < >, add list add wave add log *, add list add wave add log r / * : ;, Insert Breakpoint, Edit Clock,, :, :, 0 1, 1, 0 ;, View Wave, Wave Wave ) Wave (1 ) Wave H DL Wave, : : ASCII Simulation Simulation Options Signals,

224 6 FPGA System Designer Wave :, 20,,, :, (2 ) H DL V HDL ( ) : V erilog ( ) : ( ) : ( ) (3 ) Wave,,, List Wave, Wave HDL : List Process Signals Source Structure Variables, HDL, : VSIM > add wave < > < >

225 212 AVR SoC FPSLIC VSI M add wave * VSIM > add wave r / *,, : Wave ; ; Wave File Save Format,,, : do, VSIM > do < > File Load Format :, Wave Insert Divider,,,, N ew Divider, ( ) To move a divider: To change a divider s name and size :, To delete a divider:, Delete, Delet e, Insert Window Pane,,, sim, gold,, Tools Combine Signals, Combine Selected Signals : Name Order if Indexs, 0;,, Remove select ed signals after combining,

226 6 FPGA System Designer , 3 : Show Drivers Show Drivers Dataflow, H DL HDL,,, ; View Signal P roperties For mat, 3, View Format Compare View : Display Name ( ) Radix, Wave Color, ;, Name Color Format : Format Literal :, Logic:, U X 0 1 Event :, Analog Analog step: Analog Interpola ted: Analog backstep:, Offset and Scale :, : V HDL ( ) Verilog H eight Compare Wave,,,, Insert Breakpoint,,,, Insert cursor,

227 214 AVR SoC FPSLIC Edit Delete Cursor, View Cursor ;,, ModelSim delta,, ;,, Tools WindowsP references :,,,, Examine, Signals Wave, Signal Add Wave Signals In Region, Wave 3, counter count clk reset Wave Wave 3) (1 ) clk : force clk r 100 : clk force, 50 ns 1, 50 ns 100 ns 0, r 100 ns Signals ( ) clk, Edit Clock,, Clock Name : Offset :

228 6 FPGA System Designer Duty Period: Cancel : Logic Value : First Edge : Offset 0, Duty 50, Period 100, 1, 0, OK, clk Signals ( ) reset,,, 0; Edit Force,, Signal Name: Value: Kind: Delay For: Cancel After:, V alue 0, Freeze, Delay For 0 OK, reset, Wave,, (2 ) Run Run, Wave Wave Run, Simulate Simula te Options, 100 ns, Run R un All, Wave R un All,

229 216 AVR SoC FPSLIC.1.16, Wave Break count, Radix count,,, Radix Decimal,

230 6 FPGA System Designer , 127 1, - 128,, count, Radix Unsigned,, , 1, count,, format Analog,, Analog Step ( ), Pixels - 200( 200), 0.5 ( 0.5 ) OK, cou nt,

231 218 AVR SoC FPSLIC (3 ),, Source Source H DL, Source,, : ; Process ;, ; ; :, Source,,, ;,,, RemoveBreakpoint Disable/ Enable breakpoint Edit breakpoint, Edit all breakpoints HDL Source HDL :, T ools Examine Tools Describe ;, Source 18, Source,,, (, )

232 6 FPGA System Designer ,,,, Remove Breakpoint 18 : / ; Source, /, Edit Read Only, (4 ) : Run, Source, H DL ( Break,, ) Continue Ru n,, ;, Source, Source Step,, Variable, : quit force VHDL V H DL : / ; ; ; Variable ; 1., V HDL ( \ SystenDesign \ modeltech \ Examples \ gates. vhd adder.vhd testadder.vhd ),, test _ adder _ structural,,, ns, Sum ,

233 220 AVR SoC FPSLIC (1 ) : Model Sim ( ) Simulate Simulation Options, Assertion,, Break on Assertion Error, OK, H DL (2 ) : Simulate Run Restart, : restart f Source,,, Variable, Variable V ariables : H DL ;, HDL :

234 6 FPGA System Designer V HDL ; V erilog V H DL, Verilog ;, V H DL Verilog,, Variable Edit Change,, :, V H DL Verilog ; ; ( ) V ariable P rocess (3 ), Variable, i = 6,, test_ patt erns, 10, test_ patt erns (6 ), a b cin sum cout s um , Signals sum ,,,, (4 ), Variable, Process test, V ariable, test (5 ) Vraiable, test_patterns(6), sum, Edit Change,, Value , Change

235 222 AVR SoC FPSLIC :, (6 ), ModelSim, 9, ModelSim 1. Dataflow Da taflow ( ), 1) : ; Navigat e ; Add dataflow ; 2) (1 ) Da taflow,,,, (2 ), Edit Erase highlight (3 ) Dataflow View Show Wave,,,,, (4 ) Da taflow,, Dataflow,,

236 6 FPGA System Designer , Dataflow (, ),, Trace T race next event, Trace T race next event, Trace T race set,, ;, Trace Trace reset (5 ) X Da taflow X, :, Dataflow, T race TraceX Trace ChaseX : Trace T racex ; Trace ChaseX 2. List List,, delt a 1) HDL, H DL Verilog HDL, : V HDL ; V erilog ; 2) List HDL List : (1 ) Signal Source P rocess Variable Wave Structure, List (2 ) :

237 224 AVR SoC FPSLIC add list > < > : add list * : add list r / * 3) (1 ) List H DL List H DL, : List List Edit, List : List, View Signal Properties,, : Signal Display Name List Radix,, List ( ) Simulation Sim-

238 6 FPGA System Designer ulation Option Modlesim ini DefaultRadix ASCII, Width Trigger Triggers line:, List, ; Does not trigger line:, List (2 ), List, Tools Combine Signals,, : ame Order of Indexes Ascending, 0; Descending, Remove selected signals after combining (3 ) Edit Add Marker ,, Edit Delete Marker;, View Goto 3. Process 1) P rocess View Active,, View In Region, HDL 3 : eady delta Wait V H DL V erilog, Done Process, Ready,,, 6.1.1

239 226 AVR SoC FPSLIC.1.1 Dat aflow Sign als Source St ruc ture Varia bles V HD L Verilog 4. Structure Structure,, View Structure 1) HDL HDL ( V H DL Verilog ) : HDL ( ) ; Vreilog ( ) ; ( ) + -,, Structure : instantiation label ; entity or model ; architecture Str ucture,, Source Signals,,, Process, In Region, Process, Variable 2) Structure,, : iew Source Source ; Add Dataflow List Wave, ; Sort H DL ; Find ; Expand Selected HDL ; Collap se Selected H DL ; Expand All HDL ; Collap se All H DL ; Save List HDL ; Save Dataset WLF ;

240 6 FPGA System Designer End Simula tion, ; Close < da taset name >,,,,, System Designer 3.0, : pre_layout coverification post_layout coverification post_layout coverification 1.,, Sy st emdesign post_layout coverification,, Browser, Edit Testbench , * _posttb.vhd AT94K,, : FPGA A VR,,, F PGA, A VR, AVR,, Edit Testbench, FPGA, A VR, : Post Layou t Test Bench File Design : adder P rogram : Figaro Version : Atmel ids7.6.7

241 228 AVR SoC FPSLIC Vendor Atmel Created : September 25, 2003 at : 3 :39 :09 pm library IEEE ; use I EEE.STD_ LOGIC_1164.all; use IEEE.VIT AL_timing.all ; library AT94K ; library user94k; use AT94K.VCOMPONEN TS.all; entit y post_ test_bench is end post_test_bench ; architecture arch_test_bench of post_test_bench is component entityname port ( ) ; A : in STD_LOGIC_VECTO R(3 downto 0) : = " XXXX" ; B : in STD_LOGIC_V ECTO R(3 downto 0) : = "XXXX" ; Q : out STD_LOGIC_ VECTOR( 3 downto 0 ) end component ; signal sig_q : STD_LOGIC_VECTOR (3 downto 0) ; signal sig_b: STD_LOGIC_VECTOR (3 dow nto 0) ; signal sig_a : STD_LOGIC_VECTOR (3 downto 0) ; signal one : STD_LOGIC : = 1 ; signal zero : STD_LOGIC : = 0 ; BEGI N inst_adder : entit yname port map ( A = > sig_ A, B = > sig_b, Q = > sig_ Q ) ; stim ulus_process : process begin * * * * Add your stimulus values here * * * * end process stimulus_process ; end arch_ test_bench ;,,,,,, : stim ulus_proces s : process begin sig_ A < = "1111 " ; sig_b < = "0000 " ;

242 6 FPGA System Designer wait for ns ; sig_b < = "1111 " ; wait for 100ns; * * * * Add your stimulus values here * * * * end process stim ulus_process ; 2.,, OK, ModelSim post_test_bench,, OK,, , typical , O K,, / VSIM > 3. View Signals, Signals, Signals sig_a sig_b sig_q, Add Wave Select ed Signals, , run 200ns

243 230 AVR SoC FPSLIC ,,, sig_q, XXXX,, ;,, 5. quit f 6.2 System Designer 3.0,, System Designer 3.0 MentorGraphic LeonardoSpectrum FPG A ( F PSLIC ) ASIC LeonardoSpectrum, ;,,, ( ), ( ) ;,,,

244 6 FPGA System Designer LeonardoSpectrum V H DL Verilog H DL LeonardoSpectrum HDLInventor,, H DLInventor, H DL, LeonardoSpectrum 3 : ( Quick Setup ) ; ; ( Advanced Flow tab ) ( Quick Setup ), ,,,,,

245 232 AVR SoC FPSLIC Ru n Flow echnology: F PGA, Working Directory: LeonardoSpectrum, Tcl, src,,,,, src smallest, Opening Files: LeonardoSpectrum H DL,, EDIF,, Open files,, OK, V HDL,, Clock:, LeonardoSpectrum ;,,,, Option Effort : LeonardoSpectrum, Output : LeonardoSpectrum,, EDIF ( *.edf),, Run Flow :,,,, 4, : Wizard ; Tools Synthesis Wizard, ; ; ; 5, : library ieee ; use ieee.std_ logic_1164.all; entity counter is port(clock, reset : in std_logic ; add, sub: in std_logic ;

246 6 FPGA System Designer counter out integer range 0 to 31 ) ; end counter; architecture behaviour of counter is begin process( clock, reset, add, sub) variable temp : integer range 0 to 31 ; begin if( reset = 1 ) then temp : = 0 ; else if(clock = 1 ) and (clock event) then if(add = 1 ) then if( temp = 31) then else temp : = 0 ; temp : = temp + 1; end if; elsif( sub = 1 ) then if( temp = 0 ) then else temp : = 31; temp : = temp - 1; end if; end if; end if; end if; counter < = temp; end process ; end behaviour; (1 ), Sy st em Designer 3.0, H DL Synthesis,, Add design files,, coutnt er.vhd,,,,, (2 ) System Designer 3.0 ( ) Synthesis Tools, Tools r un H DL Synthesis, (3 ) ( 6.2.1) Tools run Synthesis Wizard,, AT94K ( 4),, Open files,, count er.vhd,, 6.2.4, counter.vhd,

247 234 AVR SoC FPSLIC

248 6 FPGA System Designer (5 ),,, 6.2.6, 1 0, (6 ),,, Filename :, Format :

249 236 AVR SoC FPSLIC

250 6 FPGA System Designer Write vendor constraints file: Downto:, counter.edf,,,, 6.2.3,, A, Tools FlowTabs FlowTab s, Input, Flow Tabs, Run Flow, 1. ( Technology) : Technology Set ting FPSLIC AT94K dvanced Settings LeonardoSpectrum,,

251 238 AVR SoC FPSLIC Input,, :, V H DL,,,, Read, LeonardoSpectrum, H DL V H DL Verilog SDF XNF EDI F V HDL EDIF V H DL V HDL, Input : op Entity,

252 6 FPGA System Designer Architectur ( ),, Generic, < generic > = < value > < generic > = < value > V HDL Style V H DL VHDL EDI F EDIF,, Design *.edf EDIF 3. LeonardoSpectrum, 80 %

253 240 AVR SoC FPSLIC,,,, ( Constraints) Global Clock Input Output Signal Module Path Report, Global, Path, 7 1) Clock( ) Reference Clock P roperties: F requency:, M Hz Period:, n s Offset : ns,, Pulse Width: n s, Duty Cycle:, Pin:

254 6 FPGA System Designer Pad Type, V H DL BU FF ER_SIG elet e Constraints :, Delete Con straints, Apply, 2) Input( ) Input Constraint :, 0 ns Arrival : ns Infinite Drive: 0 ns 0, Input Drive:,,, Max Input :, pf,,, Max Input :, Max Rise( n s) :, Max Fall( ns) :,

255 242 AVR SoC FPSLIC Pin Pad Type: elet e Con straints:, Delete Con straints, Apply, 3) Output( ) Output Constraints:, Required: Load:,,, Fanout : Max Rise( n s) :, Max Fall( ns) :, Pin: Pad Type: elet e Con straints:, Delete Con straints, Apply,

256 6 FPGA System Designer Signal( ) Signal Con straints: P reserve Signal:, Max Fanout: elete Constraints:, Delete Constraints, Apply, 5) Module( )

257 244 AVR SoC FPSLIC Module Constraints : 4 Don t Touch :,, No Opt :, Optimize : area, ; delay, area Effort : quick, ; standard, quick elet e Con straints:, Delete Constraints, Apply, 6) Path( ) Form:, Inputs: Registers :,, o:

258 6 FPGA System Designer Outputs Registers :,, False Path: ulticycle Path(cycles ) :, 1 000, Add,, Delete, Change, F rom: To: Add Delete Change Apply 7) Reprot( ) , 4. LeonardoSpectrum : ( Optimize), LeonardoSpectrum 4,, 1 : Optimize ( ) Advanced Set tings ( )

259 246 AVR SoC FPSLIC Optimize( ) Select Design to: Current Path: Target : un type: Optimize :,, Remap :,, ptimize:, ; ;, Extended Optimization Effort :, LeonardoSpectrum 3 ( ), R un type Optimize 4

260 6 FPGA System Designer ptimize for : 3 Auto: LeonardoSpectrum Delay:, Area :, ierarchy : 3 Auto:, 50 P reserve : Flatten: dd I/ O Pads : LeonardoSpectrum, I/ O, 2) Advanced Settings( ) Advanced Optimization Options: 5 Do not u se wire delay during delay calculations : ;, Allow converting internal tri state:,

261 248 AVR SoC FPSLIC Allow transforming Set/ Reset on DF Fs and Latches:, Break combinational loops statically during timing analysis:,,, Bubble T ristates:, ;, perator Options ( V HDL V erilog ) : Use technology specific module generation library:, Operator select( V H DL Verilog ) : Auto:, ;, Smallest : Small : Fast : Fastest : Extract Clock Enable : Extract Decoders: Extract ROMs: ROM Extract Count ers: Extract RAM s: RAM Optimization CP U : 0 Auto Dissolve Limit : F PGA 50 Apply, H elp 5. Run Flow,, Run Flow, Apply ( Output) : EDI F SDF Verilog V H DL 1) Output Files( ) Filename( - ) :, < > ormat : Auto: EDI F V HDL : V H DL Verilog: V erilog >. <

262 6 FPGA System Designer EDIF : EDIF SDF ( ) : SDF, SDF XNF ( Mentor Graphics ) : LeonardoSpectrum, : XN F, rite vendor constraints file: ownto: 2 Technology Cells: P rimitives: Apply 2) EDIF Out Options(EDIF ) EDIF, EDIF DIF G ND: GND,

263 250 AVR SoC FPSLIC EDIF EDI F Power: VCC, Allow Write Buses:, Write out power and ground as undriven nets with special name : Writ e the contents of cells marked Don t touch: don t_touch noopt, don t_touch 3) SDF Out Options(SDF ) : SDF, SDF

264 6 FPGA System Designer DF N ame Style: SDF V H DL Verilog V HDL : V HDL SDF Verilog: Verilog SDF None: V HDL SDF Write flat netlist:, 4) VHDL Out Options( VHDL ) VHDL ype used for bit by V H DL writer: std_logic 9 ( 0, 1, X, L, H, W, U,, Z), bit 0 1 V HDL vector type: std_logic_vector, bit_vector Allow Writing Buses: Write V HDL 87: LeonardoSpectrum 87 V H DL, 93 V H DL 6.2.4,, : ;,,, ( ) ( ) : LIBRARY ieee; USE ieee.std_logic_1164.all ; ENTITY adder IS

265 252 AVR SoC FPSLIC PORT ( A, B : IN integer range 0 to 31 ; Q : OUT integer range 0 to 31 ) ; END adder; ARC H IT ECT URE behaviour OF adder IS BEGIN Q < = A + B; END behaviour; 1) adder.vhd,, F PGA Synthesis Tool,,

266 6 FPGA System Designer Technology AT94K ; Open files, adder.vhd ;, Clock ; Optimize Effort ; Output FPG A, I/ O pads, A,, Optimize Optimize Add I/ O Pad, R un Flow, I/ O 2),, Add I/ O Pad I/ O, Apply, - > set macro TR UE - > set chip F ALSE Run Flow

267 254 AVR SoC FPSLIC I/ O 6.3,,, PCB EDA, PCB,, Sy st em Designer 3.0, Atmel Figaro Figaro Figaro F PGA, Figaro, : ( ) Figaro ECO,, FPGA,,

268 6 FPGA System Designer FPGA,, ( check ), Figaro :, ;,, Figaro, Figaro 3, Figaro : Browser ; Parts I/ O ; Compile, Figaro FPGA, Compile, Figaro Figaro ( ),,,, I/ O Pad, 1.,, F PGA, : ; ; ;,, : ; ; ;,, Figaro File Save, Figaro < >.FGD, < >. RCT,,, ECO, FPG A PCB,,, I/ O

269 256 AVR SoC FPSLIC , 6.3.2, 6.3.2

270 6 FPGA System Designer :,, check,,, : : Figaro File Open As Design, File Open As Macro,,, ;,, Figaro,,, Add I/ O Pad; ;, Figaro, 6.3.3, counter.edf, Figaro, ;, Figaro : Figaro IDS, FPGA, 3 R un F PGA place& route tool in stand alone mode, Figaro Figaro, File Design Setup,, Design Name: onfiguration:, AT 40K AT 6K AT 40K AT 40KAL AT 6K mapped to

271 258 AVR SoC FPSLIC A T K Design Directory: Tools Flow :, Exemplar M TI N ew Design...:,, Remove...:,,,, New Design...,, Design Name:, dummydes, Files of Type:, *.edf *.fgd *.xnf 3 Design Directory: 3, ( ), Design Name counter, Files of Type EDIF N etlist( *.edf), Design Directory d: \ training\ fpgaalone \ lab1 OK,,,, O K,,, Figaro

272 6 FPGA System Designer ,, File : Open as Design Open as Macro, Open, Open,, Design,, 6.3.5, Design Directory: ; Design Name: ; Tools Flow : ; Files of T ype:, *.fgd *.edf *.xnf, *.fgd; Configuration: ; Existing Design File :, Files of Type, Files of Type EDIF Netlist( *.edf), Existing Design File counter.edf, OK, Browser 2. Design Browser( ),,,,

273 260 AVR SoC FPSLIC, ( ),,,,,,,, Expanding Collap sing,,, Mapping Mapping ( Map ) :, (, ),,,, ; ; 2. Mapping,,,,, Map,,, Figaro Map Browser,, Mapping, Mapping : ; ; : Option s, Figaro Option s Options, Mapping, Figaro File Import Constraints,, *.map Mapping, 1,,, Figaro Edit Constraints, Map Browser

274 6 FPGA System Designer , Sub_Design Browser,, 4, : Multi Core Macros Multi Output Macros ; Design H ierarchy ; Design H ierarchy ;, :,, ;,, 3. Map Browser, Figaro Map Browser ( ),,,,, Window New Map Browser 6.3.6, Parts,,, 1. Parts Parts ( ) PCB, I/ O, I/ O :,, Parts Parts I/ O, I/ O ; I/ O, I/ O Parts :,,,

275 262 AVR SoC FPSLIC, I/ O 2. 1), :, Parts,, Archit ecture: Package : Application: Speed: art Name:, Part N ame, Add,,, AT94K40 25DQC,,, Add, Parts, O K OK,,,, Enough, ;,, Add, O K 2) Parts,, Figaro Edit Change Parts Speed or Application,, 6.3.8

276 6 FPGA System Designer Application: Speed: Part Name: OK,, Edit Switch Part 3),, Figaro File Import Constraints, *.ptn, Options Options, Partition, :, Parts,, ; Parts Partition, Figaro Edit Auto Partition Design,, ;, Figaro Window New Sub_Design Browser, Sub_Design Browser, : Pad 4) I/ O Parts,, I/ O, PCB, I/ O, PCB, ; FPGA,,,,, PCB, Compile : Parts,, Compile,

277 264 AVR SoC FPSLIC,, Compile,, Figaro Parts, : clock A.4, reset A.5, add A.8, s ub A.9, counter( 0) A.10 counter( 1) A.11, counter( 2) A.12, count er( 3) A.13, counter A.16 : Parts, Figaro Edit Assign Pin Locks,, Design I/ Os: I/ O Parts,, Usable Pin s < purpose > : A, 1 A.1 < >, ( ), I/ O,, < < Lock > > : I/ O, Unlock: I/ O,, Lock All:, Usable Pins < purpose >,, Figaro Unlock All:, U sable Pins < p urpose > Save File:,, *.pin Import File:, Design I/ O s I/ O (clock) U sable Pins < purpose > A.4 < GCK1 > < < Lock > >,, I/ O

278 6 FPGA System Designer OK,, Save File,, , O K : Figaro File Import Con straints, *.pin; Import File,, Compile( ),, ( Figaro Flow Compile Auto Compile A ll, Compile ), Compile,,,, : ; ; ; ; ; Figaro Window New Compile Window Compile,

279 266 AVR SoC FPSLIC Parts Figaro View Push Window Compile,,, Figaro, Figaro Flow Compile, Figaro Edit 2. :, ;, ; Compile, :, Figaro Flow Compile Parts All Steps Compile,,,,, 3. Open Map Part, Figaro, 3, ; Compile,,, Compile ( I/ O Pads, ), Figaro Window New Compile Window, Compile, Compile

280 6 FPGA System Designer ,, ;,, 1) Init Place FPGA, ;,,,,, I/ O (, Figaro ) ,, Figaro Edit,,,,,, Map 2) Opt Place, ; ; ;,, Compile,,,, :,,, 3) Init Route,,

281 268 AVR SoC FPSLIC.3.14,,,, (, Show Rounted Net, ) 4) Opt Route,

282 6 FPGA System Designer : Figaro Edit Route Select ed N ets, ; Edit Discard Route ( Measure Delay ),, ;, Figaro 5) Bit Str,, CPS,, 6.3.8, :, Optimize Optimize Add I/ O Pad Figaro, ; File Open As Macro, counter.edf ; Open Map Part, Compile , Ini Place Opt Place Ini Route Opt Rout e,, 4,

283 270 AVR SoC FPSLIC yes,, no, ; Library, Library Setup,,, yes, no OK,,,

284 AVR Studio A VR Studio 4 A VR ( IDE ) AVR 8 RISC F PSLIC AVR Studio : (1 ) ModelSim / ; (2 ) AVR ; (3 ) F PSLIC A VR A VR 2. ModelSim ModelSim ModelSim ModelSim V HDL V erilog,,,

285 272 AVR SoC FPSLIC, ModelSim V H DL Verilog, R TL ModelSim ASIC FPGA, System Designer, System Designer, HDL F PGA A VR C, System Designer Advanced Flow( ), P re layout Coverify Post layout Coverify, FPSLIC System Level Integration, MS DOS ModelSim AV R Studio, 7.2.2,,,,, ModelSim run all, AVR

286 , ModelSim,, A VR Studio,,,, ModelSim AVR Studio AVR Studio, AVR Studio Welcome, 7.2.4, A VR Studio, A VR ;, ; Open,

287 274 AVR SoC FPSLIC AVR Studio Welcome Next, 7.2.5, Debug Platform Fpslic CoSimulator Device Fpslic CoSimulator Fpslic_avr_core Finish, , AVR Studio, 7.2.1

288 Mod elsim Int erac tive ModelSim, Waiting Mod elsim, Running Mod elsim, Uninitialised E r ror/ No St a te AV R Studio No targ et L oa ded Stop p ending,, 3 s, Running, Stopp ed Busy AVR Studio A VR Studio, ; A VR Studio, ( 1 ) F PSLIC FPSLIC AVR Studio (2 ), ModelSim (3 ), A VR Studio (4 ),, Automatic H w Break/ Continue( / ), AVR Studio ; step Step Over,, ModelSim 7.2.7

289 276 AVR SoC FPSLIC (5 ), 7.2.8, Tools FPSLIC ModelSim ModelSim add wave r / *,, ModelSim, ModelSim run all, A VR Studio A VR Studio, ModelSim, Interactive ModelSim Interactive, : (1 ) Exit A VR Studio; (2 ) ModelSim Restart, ModelSim A VR Studio; (3 ) AVR Studio Welcome

290 7 277 AVR FPGA AVR FPGA 1, A T94K FPSLIC I/ O A VR FPG A AV R FPG A 0, A VR 3, AVR , A VR F PGA F PGA I/ O System Designer, \ SystemDesigner \ Examples \ A T94K \ Coverify \ doc2325.zip A T94KD EF.I NC At mel AVR F PSLIC D1 A T M L.A SM At mel AVR 1 D1 CVA VR.C Cod evision A VR 1 D1 I AR.C IAR Sys tems 1 D1 ICC.C Ima gecraft 1 CO U N T ER.V CO U N T ER.V H D Verilog V HD L HDL COU NTE R.V COU NT ER.V H D 0x00 0x3F 8 EN ABLE RESE T RCO AVR INT A0 A VR

291 278 AVR SoC FPSLIC INTA0 ( ISR ), A VR INTA0, 8 A VR FPGA, A VR ( FPGA awe ) FPG A I/ O SELECT 0 ( FPGA LOAD ), A VR FPG A LOAD awe, (0 x3f ), RCD, AVR, ( ISR ), A tmel System Designer, HDL V H DL : stim ulus : process begin sig_reset < = 0 ; sig_en able < = 0 ; wait for 100 ns ; sig_reset < = 1 ; wait for 100 ns ; sig_reset < = 0 ; sig_en able < = 1 ; wait for 200 us ; end process stimulus ; Verilog : initial begin sig_reset = 1 b0 ; sig_en able = 1 b0; # 100 sig_reset = 1 b1 ; # 100 sig_reset = 1 b0 ; sig_en able = 1 b1; # ; end AVR FPGA SRAM AV R FPG A 0, A VR 3, AVR 7.3.2

292 , A VR F PGA F PGA I/ O SRAM System Designer, \ SystemDesigner \ Examples \ A T94K \ Coverify \ doc2326.zip A T94K DEF.I NC At mel AVR F PSLIC D2 A T M L.ASM At mel AVR 2 D2 CV AVR.C Cod evision A VR 2 D2 I AR.C IAR Sys tems 2 D2 ICC.C Ima gecraft 2 v150 a t94k 32.x cl IAR Sys tems v1.50 X LI NK v200 a t94k 32.x cl IAR Sys tems v2.00 X LI NK CO U N T E R.V CO U N T E R.V HD Verilog V HD L HDL COU NTE R.V COU NT ER.V H D 0x00 0x3F 8 EN ABLE RESE T RCO AVR INT A0 A VR, INTA0 ( ISR ), A VR INTA0

293 280 AVR SoC FPSLIC SRAM, 0x0F9B, ISR 8 AV R FPGA, A VR ( FPGA awe ) FPGA I/ O SELEC T 0 ( FPG A LOAD ), A VR FPGA LOAD awe, (0 x3f ), RCD, AVR, ( ISR ), A tmel System Designer, HDL V H DL : stim ulus : process begin sig_reset < = 0 ; sig_en able < = 0 ; wait for 100 ns ; sig_reset < = 1 ; wait for 100 ns ; sig_reset < = 0 ; sig_en able < = 1 ; wait for 200 us ; end process stimulus ; Verilog : initial begin sig_reset = 1 b0 ; sig_en able = 1 b0; # 100 sig_reset = 1 b1 ; # 100 sig_reset = 1 b0 ; sig_en able = 1 b1; # ; end AVR FPGA , SRAM AV R FPG A 0, A VR 3, AVR , A VR F PGA

294 FPGA I/ O SRAM System Designer, \ SystemDesigner \ Examples \ A T94K \ Coverify \ doc2327.zip A T94K DEF.I NC At mel AVR F PSLIC D3 A T M L.ASM At mel AVR 3 D3 CV AVR.C Cod evision A VR 3 D3 I AR.C IAR Sys tems 3 D3 ICC.C Ima gecraft 3 v150 a t94k 32.x cl IAR Sys tems v1.50 X LI NK v200 a t94k 32.x cl IAR Sys tems v2.00 X LI NK

295 282 AVR SoC FPSLIC.3.3 CO U N T E R.V CO U N T E R2.V CO U N T E R3.V CO U N T E R.V HD CO U N T E R2.V H D CO U N T E R3.V H D 1 Verilog 2 Verilog Verilog 1 V HD L 2 V HD L V HD L HDL CO U NTE R3.V COU NT ER3.V HD 8, 0x00 0x3F 0x00 0x1F ENABLE RESE T AVR INTA0 INTA1 A VR 1, INT A0 ( ISR ), A VR INTA0, SRAM, 0x0F9B, ISR 8 AVR FPGA, A VR ( FPGA awe ) F PGA I/ O SELEC T 0 ( FPG A LOAD ), AVR FPGA A VR 2, INT A1 ( ISR ), A VR INTA1, SRAM, 0x0F9C, ISR 8 AV R FPG A, AVR ( F PGA awe ) FPG A I/ O SELECT 1 ( FPGA LOAD ), SRAM ( 0 x0f9c) LOAD awe,, RCD, A VR, ( ISR), A tmel System Designer, HDL V H DL : stim ulus : process begin sig_reset < = 0 ; sig_en able < = 0 ; wait for 100 ns ; sig_reset < = 1 ; wait for 100 ns ; sig_reset < = 0 ; sig_en able < = 1 ; wait for 200 us ; end process stimulus ;

296 7 283 Verilog initial begin sig_reset = 1 b0 ; sig_en able = 1 b0; # 100 sig_reset = 1 b1 ; # 100 sig_reset = 1 b0 ; sig_en able = 1 b1; # ; end AVR FPGA , SRAM AV R FPG A 0, A VR 3, AVR , A VR F PGA F PGA I/ O SRAM A VR System Designer, \ SystemDesigner \ Examples \ A T94K \ Coverify \ doc2328.zip A T94K DEF.I NC At mel AVR F PSLIC D4 A T M L.ASM At mel AVR 4 D4 CV AVR.C Cod evision A VR 4 D4 I AR.C IAR Sys tems 4 D4 ICC.C Ima gecraft 4 v150 a t94k 32.x cl IAR Sys tems v1.50 X LI NK v200 a t94k 32.x cl IAR Sys tems v2.00 X LI NK CO U N T E R.V CO U N T E R2.V CO U N T E R3.V CO U N T E R.V HD CO U N T E R2.V H D CO U N T E R3.V H D 1 Verilog 2 Verilog Verilog 1 V HD L 2 V HD L V HD L

297 284 AVR SoC FPSLIC HDL CO U NTE R3.V COU NT ER3.V HD 8, 0x00 0x3F 0x00 0x1F ENABLE RESE T AVR INTA0 INTA1 A VR 1, INT A0 ( ISR ), A VR INTA0, SRAM, 0x0F9B ISR, SRAM ( 0x0F9D 0x0F9E ), ISR 8 AV R FPG A, AVR ( F PGA awe ) FPGA I/ O SE- LECT 0 ( FPGA LOAD ), A VR F PGA A VR 2, INT A1 ( ISR ), A VR INTA1, SRAM

298 x0F9C, ISR 8 AV R FPG A, AVR ( F PGA awe ) FPG A I/ O SELECT 1 ( FPGA LOAD ), SRAM ( 0 x0f9c) LOAD awe,, RCD, A VR, ( ISR), A tmel System Designer, HDL V H DL : stim ulus : process begin sig_reset < = 0 ; sig_en able < = 0 ; wait for 100 ns ; sig_reset < = 1 ; wait for 100 ns ; sig_reset < = 0 ; sig_en able < = 1 ; wait for 200 us ; end process stimulus ; Verilog : initial begin end sig_reset = 1 b0 ; sig_en able = 1 b0; # 100 sig_reset = 1 b1 ; # 100 sig_reset = 1 b0 ; sig_en able = 1 b1; # ; AVR FPGA U AR T / AV R FPG A 0, A VR 3, AVR , A VR F PGA F PGA I/ O SRAM A VR A VR U AR T

299 286 AVR SoC FPSLIC System Designer, \ SystemDesigner\Examples\ AT 94K\ Coverify\ doc2329.zip A T94K DEF.I NC At mel AVR F PSLIC D5 A T M L.ASM At mel AVR 5 D5 CV AVR.C Cod evision A VR 5 D5 I AR.C IAR Sys tems 5 D5 ICC.C Ima gecraft 5 v150 a t94k 32.x cl IAR Sys tems v1.50 X LI NK

300 v200 a t94k 32.x cl IAR Sys tems v2.00 X LI NK CO U N T E R.V CO U N T E R2.V CO U N T E R3.V CO U N T E R.V HD CO U N T E R2.V H D CO U N T E R3.V H D 1 Verilog 2 Verilog Verilog 1 V HD L 2 V HD L V HD L HDL COUNTER3.V COUNTER3.V HD 8, 0x00 0x3F 0x00 0x1F ENABLE RESET AVR INTA0 INTA1 A VR 1, INT A0 ( ISR ), A VR INTA0, SRAM, 0x0F9B ISR, SRAM ( 0x0F9D 0x0F9E ) U AR T0 UAR T1, SRAM ( 0x0F9F 0 x0fa0 ),, SRAM 0 x0fa1 1, ISR 8 A VR F PGA, AVR ( FPGA awe ) F PGA I/ O SELECT 0 ( FPG A LOAD ), A VR FP- GA A VR 2, INT A1 ( ISR ), A VR INTA1, SRAM, 0x0F9C, ISR 8 AV R FPG A, AVR ( F PGA awe ) FPG A I/ O SELECT 1 ( FPGA LOAD ), SRAM ( 0 x0f9c) LOAD awe,, RCD, A VR, ( ISR), A tmel System Designer, HDL V H DL : stim ulus : process begin sig_reset < = 0 ; sig_en able < = 0 ; wait for 100 ns ; sig_reset < = 1 ;

301 288 AVR SoC FPSLIC wait for ns ; sig_reset < = 0 ; sig_en able < = 1 ; wait for 200 us ; end process stimulus ; initial begin end Verilog : sig_reset = 1 b0 ; sig_en able = 1 b0; # 100 sig_reset = 1 b1 ; # 100 sig_reset = 1 b0 ; sig_en able = 1 b1; # ; AVR FPGA AVR I/ O ( POR TD POR TE) AV R FPG A 0, A VR 3, AVR , A VR F PGA F PGA I/ O SRAM AVR A VR UA RT s A VR I/ O System Designer, \ SystemDesigner \ Examples \ A T94K \ Coverify \ doc2330.zip A T94K DEF.I NC At mel AVR F PSLIC D6 A T M L.ASM At mel AVR 6 D6 CV AVR.C Cod evision A VR 6 D6 I AR.C IAR Sys tems 6 D6 ICC.C Ima gecraft 6 v150 a t94k 32.x cl IAR Sys tems v1.50 X LI NK v200 a t94k 32.x cl IAR Sys tems v2.00 X LI NK

302 CO U N T E R.V CO U N T E R2.V CO U N T E R3.V CO U N T E R.V HD CO U N T E R2.V H D CO U N T E R3.V H D 1 Verilog 2 Verilog Verilog 1 V HD L 2 V HD L V HD L HDL CO U NTE R3.V COU NT ER3.V HD 8, 0x00 0x3F 0x00 0x1F ENABLE

303 290 AVR SoC FPSLIC RESE T AVR INTA INTA1 A VR 1, INT A0 ( ISR ), A VR INTA0, SRAM, 0x0F9B ISR, SRAM ( 0x0F9D 0x0F9E ) U AR T0 UAR T1, SRAM ( 0x0F9F 0 x0fa0 ),, SRAM 0 x0fa1 1, ISR 8 A VR F PGA, AVR ( FPGA awe ) F PGA I/ O SELECT 0 ( FPG A LOAD ), A VR FP- GA A VR 2, INT A1 ( ISR ), A VR INTA1, SRAM, 0x0F9C, ISR POR TE, AV R ( FPGA awe ) FPG A I/ O SELECT 1 ( F PGA LO AD ), SRAM ( 0x0F9C) LOAD awe,, RCD, A VR, ( ISR), A tmel System Designer, HDL V H DL : stim ulus : process begin sig_reset < = 0 ; sig_en able < = 0 ; wait for 100 ns ; sig_reset < = 1 ; wait for 100 ns ; sig_reset < = 0 ; sig_en able < = 1 ; wait for 200 us ; end process stimulus ; Verilog : initial begin sig_reset = 1 b0 ; sig_en able = 1 b0; # 100 sig_reset = 1 b1 ;

304 7 291 end sig_r eset = 1 b0 ; sig_en able = 1 b1; # ; ,,, F PGA AVR, RAM Advanced Flow Device Programming, F PSLIC, FPSLIC F PSLIC 3 : File Settings FPSLIC FPSLIC CR Set tings FPGA F PGA CR Settings ile Settings / FPGA Bitstream: F PGA ( *.b st), Include FPGA Bitstream, Browse A VR Hex: AVR ( *.hex ), Include AVR H ex File, Browse Data RAM: SRAM ( *.hex *.atf),

305 292 AVR SoC FPSLIC Load Data RAM during configuration Browse ; Data Ram File Format RAM, Atmel Text Format( ATF) Intel H ex Output Bitstream File: ( *.b st) F PSLIC CR Set tings FPSLIC F PGA CR Settings FPG A OK, Bitstream Download Program Configurator, A T17 ( CPS ),, Bitstream Download Density, FP- GA EE PROM EEPROM System Designer 3.0 Atmel AT17 CPS, FPSLIC EE PROM Atmel CPS8.01, A tmel AT17 CPS, Atmel CPS

306 7 293 rocedure :, : / P: Partition, program and verify from an Atmel file: *.bst A T17,,, / R : Read dat a from device and save to an A tmel file:, *. bst / V : Verify device against an Atmel file :, / X : Verify device reset polarity: FPGA, / M : E nable AT17C512A/ 010A/ 020A/ 002A internal clock: AT17C512A/ 010A/ 020A/ 002A / M : Disable AT17C512A/ 010A/ 020A/ 002A internal clock: AT17C512A/ 010A/ 020A/ 002A / CP : Convert, partition, program and verify from a Cypress file: Cypress.hex AT17 / CB: Convert and partition a Cypress file : Cypress.hex.bst ile: /, : Input File: Out File :, < CPS path > \out.bst Checksum: ptions:, : Family: Device: Reset Polarity:,, COMM Port : Data Rate: PC, 100 kh z;, k Hz A2 Bit Level : A2, EE PROM, EEPROM A2 Bit Level EEPROM A2 Bit Level EE PROM A2 AT17C/ LV020 ( A) ( 2 Mb), A2 VC C nfo: Console:,, CF.LST

307 294 AVR SoC FPSLIC Strat P rocedure :,, Restore Defaults:, Procedure / P: Partition, program and verify from an A tmel file View Log File...:, CF.LST, A tmel ADT H2200 ADTH2200 :, AT17 ADT H2200, PC, ADT H2200 PC, PC ADT H2200 AT17, 7.5 FPSLIC FPSLIC FPSLIC, A tmel FPSLIC A T94K Start er Kit ( ATSTK94) F PSLIC, F PSLIC, ATSTK94,, FPSLIC ATSTK94 A TS TK94 ATSTK94 9 V A TS TK94 : F PSLIC AT94K40AL; F PSLIC AT17; LED ; RS ; 232 ; A VR F PSLIC ; F PSLIC ; A TS TK94 Atmel FPSLIC, AVR Studio CPS ( Configurator Programming Sy stem ) LeonardoSpectrum ModelSim, ATSTK94, ATS TK , ATSTK94 FPSLIC EEPROM AT17 PC, F PSLIC,

308 7 295 ATSTK94 1. FPSLIC PROG,,, CPS ( Configurator Programming System ) RU N, FPSLIC, F PSLIC, JP19 RU N, FPSLIC 2. ISP F PSLIC : A VR RESE T, AVR, ; RESE T, SW12, JP19 A VR, 7.5.1, SW12,

309 296 AVR SoC FPSLIC SW SW8 FPSLIC FPGA I/ O, I/ O RESET R ESE T S W J19 R ESET ( ) A VR RESET S W12 48 J19 A VR REST 3., LED;, A A VR, F FPGA SW1 SW4 AVR,, SW1 F PG A I/ O 202 F SW2 F PG A I/ O 198 F SW3 F PG A I/ O 192 F SW4 F PG A I/ O 188 F SW5 F PG A I/ O 180 F SW6 F PG A I/ O 176 F SW7 F PG A I/ O 172 F SW8 F PG A I/ O 168 F SW1 A VR I N T P0 135 A SW2 A VR I N T P1 145 A SW3 A VR I N T P2 146 A SW4 A VR I N T P3 152 A SW5 A VR PE0 109 A SW6 A VR PE1 110 A SW7 A VR PE2 113 A SW8 A VR PE3 122 A 4. LED LED, LED, LED LED, 7.5.3, LED LED

310 7 297 LED LED L1 F PG A I/ O 200 F L2 F PG A I/ O 196 F L3 F PG A I/ O 190 F L4 F PG A I/ O 186 F L5 F PG A I/ O 178 F L6 F PG A I/ O 174 F L7 F PG A I/ O 170 F L8 F PG A I/ O 166 F L1 AV R P D0 111 A L2 AV R P D1 112 A L3 AV R P D2 114 A L4 AV R P D3 120 A L5 AV R P D4 121 A L6 AV R P D5 126 A L7 AV R P D6 127 A L8 AV R P D7 134 A , LED1 LED0, F PGA AT40K AL I/ O, 7.5.4,0 1 FPG A I/ O ;,2 3 FPG A I/ O 1/ 10, 0.1 m s RS 232 UART RS 232 RS 232 UA RT, FPSLIC F PSLIC PC U AR T F PSLIC, 7.5.5

311 298 AVR SoC FPSLIC.5.4 LE D0 LE D1 A F PGA I/ O 94 B F PGA I/ O 98 C F PGA I/ O 97 D F PGA I/ O 93 E F PGA I/ O 81 F F PGA I/ O 82 G F PGA I/ O 87 H F PGA I/ O 89 J F PGA I/ O 91 K F PGA I/ O 88 L F PGA I/ O 86 M F PGA I/ O 83 N F PGA I/ O 92 P F PGA I/ O 84 D.P. F PGA I/ O 95 1 F PGA I/ O 85 2 F PGA I/ O 96 A FP GA I/ O 73 B FP GA I/ O 80 C FP GA I/ O 76 D FP GA I/ O 72 E FP GA I/ O 59 F FP GA I/ O 60 G FP GA I/ O 66 H FP GA I/ O 69 J FP GA I/ O 70 K FP GA I/ O 68 L FP GA I/ O 65 M FP GA I/ O 61 N FP GA I/ O 71 P FP GA I/ O 63 D.P FP GA I/ O 74 1 FP GA I/ O 64 2 FP GA I/ O UART U AR T / U AR T 0 RX0 140 U A R T0 U AR T 0 TX0 141 U A R T0 U AR T 1 RX1 149 U A R T1 U AR T 1 TX1 150 U A R T MHz FPGA 2 A VR 32, 768 kh z( ) 4 MHz M Hz F PGA, ( GCLK5 GCLK6 ) AVR, GCLK6 / , F PSLIC AT17LV010 A T94K Kb, 200 Kb, FPSLIC FPSLIC

312 7 299 LED F PG A GCL K7 162 ( SW9 ) F PG A GCL K1 F PG A GCL K2 F PG A GCL K3 F PG A GCL K4 F PG A GCL K7 F PG A GCL K k Hz A VR T OSC : JP17 4 M Hz AV R 138, J P18 3 : J P17, J P18 2 : JP M Hz AV R 138, J P18 3 : J P17, J P F P SL IC I/ O 1 NC 2 G ND G ND 3 NC 4 GCK1( I/ O ) 5 I/ O 6 I/ O 7 I/ O 8 I/ O 9 I/ O 10 I/ O 11 I/ O 12 I/ O 13 I/ O 14 G ND G ND 15 FCK1 ( I/ O ) 16 I/ O 17 I/ O

313 300 AVR SoC FPSLIC.5.7 F P SL IC I/ O 18 I/ O 19 I/ O 20 I/ O 21 I/ O 22 I/ O 23 I/ O 24 I/ O 25 G ND G ND 26 Vcc Vcc 27 I/ O 28 I/ O 29 I/ O 30 I/ O 31 I/ O 32 I/ O 33 I/ O 34 I/ O 35 I/ O 36 FCK2 ( I/ O ) 37 G ND G ND 38 I/ O 39 I/ O 40 I/ O 41 I/ O 42 I/ O 43 I/ O 44 I/ O 45 I/ O 46 O TS ( I/ O) 47 GCK2( I/ O ) 48 A VR RESE T AV R R ESE T J P19, SW12 49 G ND G ND 50 M0 G ND 51 NC 52 NC 53 NC

314 F P SL IC I/ O 54 NC 55 Vcc 56 M2 G ND 57 GCK3( I/ O ) 58 H DC( I/ O) 59 I/ O 1 E L ED 1 E 60 I/ O 1 F LED 1F 61 I/ O 1 M LE D 1M 62 L DC( I/ O ) 63 I/ O 1 P LE D 1P 64 I/ O 1 1 LE D I/ O 1 L L ED 1 L 66 I/ O 1G LE D 1G 67 G ND G ND 68 I/ O 1 K LE D 1K 69 I/ O 1 H L ED 1 H 70 I/ O 1 J LE D 1J 71 I/ O 1 N LE D 1N 72 I/ O 1D LE D 1D 73 I/ O 1 A LE D 1A 74 I/ O 1D P LE D 1DP 75 I/ O 1 2 LE D I/ O 1C L ED 1C 77 I NI T ( I/ O) IN I T A T 17 R ESE T/ OE 78 Vcc Vcc 79 G ND G ND 80 I/ O 1B LED 1B 81 I/ O 0 E L ED 0 E 82 I/ O 0 F LED 0F 83 I/ O 0 M LE D 0M 84 I/ O 0 P LE D 0P 85 I/ O 0 1 LE D I/ O 0 L L ED 0 L 87 I/ O 0G LE D 0G 88 I/ O 0 K LE D 0K 89 I/ O 0 H L ED 0 H

315 302 AVR SoC FPSLIC.5.7 F P SL IC I/ O 90 G ND G ND 91 I/ O 0 J LE D 0J 92 I/ O 0 N LE D 0N 93 I/ O 0D LE D 0D 94 I/ O 0 A LE D 0A 95 I/ O 0D P LE D 0DP 96 I/ O 0 2 LE D I/ O 0C L ED 0C 98 I/ O 0B LED 0B 99 I/ O 100 GCK( I/ O ) GCL 4 M Hz 4 MHz 101 G ND G ND 102 NC 103 CON A T17/ CE 104 NC 105 NC 106 Vcc Vcc 107 NC 108 R ESE T FP SLIC R ESE T J P19, SW PE0 E 0 J P13 A 110 PE1 E 1 J P14 A 111 PD0 D0 J P1 A 112 PD1 D0 J P2 A 113 PE2 E 2 J P15 A 114 PD2 D2 J P3 A 115 NC 116 NC 117 NC 118 NC 119 NC 120 PD3 D3 J P4 A 121 PD4 D4 J P5 A 122 PE3 E 3 J P16 A 123 CS0 124 SD A 2 A T SCL 2 A T 17

316 F P SL IC I/ O 126 PD5 D5 J P6 A 127 PD6 D6 J P7 A 128 PE4 E PE5 E Vcc Vcc 131 G ND G ND 132 PE6 E PE7 E PD7 D7 J P8 A 135 IN TP0 0 J P9 A 136 NC 137 NC 138 X T A L1 AVR J P17, Y1 139 X T A L2 AVR J P18, Y1 140 RX0 U A R T0 U AR T T X0 U A R T0 U AR T G ND G ND 143 NC 144 NC 145 IN TP1 1 J P10 A 146 IN TP2 2 J P11 A 147 T OSC1 Y2 148 T OSC2 Y2 149 RX1 U A R T1 U AR T T X1 U A R T1 U AR T D0 A T IN TP3 3 J P12 A 153 CC LK A T Vcc 155 NC 156 NC 157 NC 158 NC 159 I/ O 160 G ND 161 I/ O0

317 304 AVR SoC FPSLIC.5.7 F P SL IC I/ O 162 GCK7( I/ O ) GCK7 M AN CL K ( SW ) 163 I/ O 164 I/ O 165 I/ O 166 I/ O LE D8 JP8 F 167 I/ O 168 I/ O 8 JP16 F 169 I/ O 170 I/ O LE D7 JP7 F 171 G ND 172 I/ O 7 JP15 F 173 I/ O 174 I/ O LE D6 JP6 F 175 I/ O 176 I/ O 6 JP14 F 177 I/ O 178 I/ O LE D5 JP13 F 179 I/ O 180 I/ O 5 JP13 F 181 I/ O 182 G ND 183 Vcc 184 I/ O 185 I/ O 186 I/ O LE D4 JP4 F 187 I/ O 188 I/ O 4 JP12 F 189 I/ O 190 I/ O LE D3 JP3 F 191 I/ O 192 I/ O 3 JP11 F 193 I/ O 194 G ND 195 I/ O 196 I/ O LE D2 JP2 F 197 I/ O

318 F P SL IC I/ O 198 I/ O 2 JP10 F 199 I/ O 200 I/ O LE D1 JP1 F 201 I/ O 202 I/ O 1 JP9 F 203 I/ O 204 GCK8( I/ O ) 205 Vcc 206 NC 207 NC 208 NC ATSTK94 ATSTK94, : 1), C: \ SystemDesigner Sy st em Designer 3.0,, : (1 ) System Designer 3.0; (2 ) licen se ; (3 ) CPS; (4 ) C: \ Syst emdesigner\ Examples \ at94k \ ATSTK94 Design s \ test_ bitstream fp slic_test_ bitstream.bst C: \ training\ fpslic\ lab1 2),, : (1 ) ATD H2225, 10 ATDH93S TKB J1 ; (2 ) P3 ; (3 ) LED, LED1 LED8 SW1 SW4 A VR, SW5 SW8 FPGA (4 ) SW10 PROG, SW14 ON, LED 3), : (1 ), Atmel A tmel CPS 8.0x, Atmel CPS, (2 ) Procedure IP Partition, Program and Verify from an Atmel File

319 306 AVR SoC FPSLIC Atmel CPS (3 ), C: \ training\ fpslic \ lab1 fpslic_test_bitstream.bst (4 ), C: \ training\fpslic \ lab1 out.bst (5 ) Family AT 40K/ Cypress, Device AT 17LV010 (A) (1M) (6 ) (7 ) Start P rocedure, Start 7.5.4, Clock Calibration, 7.5.4, (8 ) Yes, Calibration Accuracy Low Medium H igh, Calibrate Calibrate Now,, out.bst 7.5.5,, (9 ), Prog Run,

320 7 307 CPS 0 9 A Z, LED, JP19 RESET, SW12 FPSLIC; Checksum test_fpslic.bst, 4) : Error message Expected 1 but found 0 No Power to the board Prog/ Run in the w rong position : FA TAL_ERROR :CMD ack_sense timed out Double check the orientation of cable connected to evalua tion board :, Figaro,,,, A VR FPG A CPS

321 308 AVR SoC FPSLIC.5.8 / J P1 16 J P17 LE D A, LE D A VR ; F F PG A 2,, 4 M Hz ; 18 M Hz 3,, 4 M Hz ; 18 M Hz J P18 J P19 J P20 J P21 J P22 ON/ O F F ( S W14 ) Run/ P rog R ESE T ;, A T17 SE R_ E N A VR PE 7, 2 ;, CE O/ A2 V CC ;, A T17 V CC, Off, Prog ATST94K 1. FPGA AVR I/ O F PSLIC F PGA AVR I/ O, 1) 8, A VR I/ O ( FIOR EA ) FPGA I/ O Select, FPGA : C: \ SystemDesigner \ examples \ AT94K > Design s \ PortIO \ Input \ FPG A, A VR FPG A ATSTK94, IDS A TS TK94 LED ( Ln ) A, ( SW n ) F FPG A

322 7 309 AVR FPGA T ab ( ) AV R AV RIOSe lects en able IO SE L A0 Dat at oa VR da ta out ( 0) ADO U T A0 Dat at oa VR da ta out ( 1) ADO U T A1 Dat at oa VR da ta out ( 2) ADO U T A2 Dat at oa VR da ta out ( 3) ADO U T A3 Dat at oa VR da ta out ( 4) ADO U T A4 Dat at oa VR da ta out ( 5) ADO U T A5 Dat at oa VR da ta out ( 6) ADO U T A6 Dat at oa VR da ta out ( 7) ADO U T A7 A VR Contols fiorea FIO RE A F PG ACloc ks clock GC LK FPGA I/ O S W1 P INx ( 0) 202 S W2 P INx ( 1) 198 S W3 P INx ( 2) 192 S W4 P INx ( 3) 188 S W5 P INx ( 4) 180 S W6 P INx ( 5) 176 S W7 P INx ( 6) 172 S W8 P INx ( 7) 168 A VR F PGA I/ O FPGA FPG A I/ O Select 0 F PGA I/ O, XFIS1 XFIS0 A VR FPGA I/ O AV R FPGA, R16 ldi 16, ( ( 0 < < XFIS1) + ( 0 < < XF IS0 ) ) out FISCR, R16 ; in R16, FISUA ; 7.5.7

323 310 AVR SoC FPSLIC library IE EE ; FPG A I O portin.vhd: use IEE E.STD_LOGIC_1164.all ; entity PORTIN is port( ) ; end PORTIN ; CLOCK : in std_logic ; ENABLE : in std_logic ; FIOREA : in std_logic ; PIN x: inout std_logic_vector (7 dow nto 0) ; DAT AOU T : out std_logic_vector (7 downto 0) ; architecture BE HAV of PORTIN is begin process( CLOCK, ENABL E, FIOREA, PINx) begin if end BEH AV ; 2) CLOCK event and CLOCK = 0 then if ( ENABLE = 1 and F IOREA = 1 ) then end else end if; end proces s; DAT AOUT < = PINx; PINx < = ZZZZZZZZ ; DAT AOUT < = ZZZZZZZZ ; if;, 8 A VR I/ O Write Enable( FIOWEA) FPGA I/ O Select, : C: \ SystemDesigner\ examples\ AT 94K > Designs\ PortIO\ Output \ F PGA, System Designer AVR F PGA Interface

324 AVR FPGA T ab ( ) A VR AVRIO Selec ts loa d IOSEL A0 Da taf rom A VR d at ain ( 0) ADI NA0 Da taf rom A VR d at ain ( 1) ADI NA1 Da taf rom A VR d at ain ( 2) ADI NA2 Da taf rom A VR d at ain ( 3) ADI NA3 Da taf rom A VR d at ain ( 4) ADI NA4 Da taf rom A VR d at ain ( 5) ADI NA5 Da taf rom A VR d at ain ( 6) ADI NA6 Da taf rom A VR d at ain ( 7) ADI NA7 A VRContols Fiowea F IOWEA F PG AC loc ks Clo ck GCL K5, ATSTK94, IDS, ATS TK94,, LED ( Ln) F, ( SWn) A LED FPGA LED FPGA F PG A L1 POR T x (0 ) 200 L2 POR T x (1 ) 196 L3 POR T x (2 ) 190 L4 POR T x (3 ) 186 L5 POR T x (4 ) 178 L6 POR T x (5 ) 174 L7 POR T x (6 ) 170 L8 POR T x (7 ) 166, A VR FPGA I/ O Select 0 FPGA FPGA I/ O, XFIS1 XFIS0 AVR FPGA I/ O A VR FPGA, R17 ldi 16, ( ( 0 < < XFIS1) + ( 0 < < XF IS0 ) ) out FISCR, R16 ; out FISUA, R17 ;

325 312 AVR SoC FPSLIC.5.9 F PGA I/ O portout.vh d : library IE EE ; use IEE E.STD_LOGIC_1164.all ; entity PORTOU T is port( ) ; end PORTOU T ; CLOCK : in std_logic ; LOAD: in std_logic ; FIOWEA : in std_logic; DAT AIN : in std_ logic_vector(7 down to 0) ; PORTX: out std_logic_vector(7 downto 0) ; architecture BE HAV of PORTOU T is begin process( CLOCK, LOAD, FIOWEA,DATA IN) begin variable PORTXINT : std_logic_vector( 7 downto 0 ) ; if ( rising_edge(clock) and CLOCK = event ) th en end if ( LOAD = 1 and FIOWEA = 1 ) then end if; if; PORTX < = PO RT XIN T ; end process ; end BEH AV ; 2. PORTXIN T < = DATA IN; ATSTK94, FPGA, LED AVR D A VR 8 F PGA,, AVR 7, ROM

326 C: \ Syst emdesigner\ example \ AT94K \ atstk94 designs\ scrolling : (1 ) Scrolling.vhd (2 ) Scroll.c (3 ) F PGA A VR, : SPACE, SPACE F PGA AVR, *.ict, FPGA AVR FP GA AV R Ta b ( ) L oad (0 ) < < Conn ect > > IO SE LA0 AVR IO Select s L oad (1 ) < < Conn ect > > IO SE LA1 AVR IO Select s L oad (2 ) < < Conn ect > > IO SE LA2 AVR IO Select s L oad (3 ) < < Conn ect > > IO SE LA3 AVR IO Select s D ( 0) < < Conn ect > > ADIN A0 Dat a from A VR D ( 1) < < Conn ect > > ADIN A1 Dat a from A VR D ( 2) < < Conn ect > > ADIN A2 Dat a from A VR D ( 3) < < Conn ect > > ADIN A3 Dat a from A VR D ( 4) < < Conn ect > > ADIN A4 Dat a from A VR D ( 5) < < Conn ect > > ADIN A5 Dat a from A VR D ( 6) < < Conn ect > > ADIN A6 Dat a from A VR Io_ writ e < < Conn ect > > F IOWEA A VR Cont rol C lk < < Conn ect > > GCL K5 F PGA Clock s (4 ), FIGARO IDS ROM : Tools Entry Generator s Memory ROM 7 15 rom7 15, generate, Open EDIF netlist Figaro IDS

327 314 AVR SoC FPSLIC File import(constraints ), scrolling.pin, F PGA (6 ), scrolling.bst ICC scroll.hex (7 ) System Designer 3.0 CPS ( Configurator Programming System ) A TS TK94 (8 ) LED A, A VR D LED (9 ) PROG R UN, FPSLIC ST ART ER KIT IS HE RE, LED A VR ( 10 ) J19 AVRRESE T, RESE T SW12,, LED (11) SW12, LED (12), JP19 R ESET, RES ET SW12 (13), unsigned char alphastring[ ] = FPSLIC STA RTER K IT IS H ERE ; (14) A VR : / * Output string_characters on FPGA I/ O address line * / for(counter = 0 ; counter < width; counter + + ) {FISCR = counter ; } if( ( nextpointer < width) & & (counter > nextpointer) ) F ISUA = ; else FISUA = alphastring[ nextpointer counter] ; (15) C (16) (17) EE PROM,,, : (1 ),, 1;, 0 TCCRIB = 0x00 ;/ / stop TCCRIB = 0x03 ;/ / start Timer / / TCCR0 = 0x00 ;/ / stop / / TCCR0 = 0x01 ;/ / start Timer

328 , LED, (3 ), 1 (4 ),, : PROG RU N ; ; ; CPS, FPSLIC, Atmel ATSTK94,,