Microsoft PowerPoint - MR413_Lec3.pptx

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1 模拟集成电路课程设计 ( 版图 ) Layout in Analog Integrated Circuits Assist. Prof. Jian Zhao Prof. Guoxing Wang Shanghai Jiao Tong University School of Microelectronics zhaojianycc@sjtu.edu.cn

2 Time Instructors Lecture: Tuesday 14:00 to 15:00 Lab: Tuesday 15:00~17:30, Friday 14:00~17:30 Lecturer Assist. Prof. Jian Zhao ( 赵健 ) & Prof. Guoxing Wang School of Microelectronics, Room 427 zhaojianycc@sjtu.edu.cn Teaching Assistant Dr. Luo Jing ( 罗京 ) School of Microelectronics, Room 404. luojing@sjtu.edu.cn Slide 1

3 Syllabus (New) L1: Introduction L2: Process, Active & Passive Components L3: Process variation & Matching Issues ( 匹配问题 ) L4: Noise & Shield L5: Floor planning & Package L6: Design for Manufacture (Prof. Li Yongfu) L7: Tracy (Advanced EDA tools by cadence) L8: Project Review Slide 2

4 Review of Lecture #1 & #2 Introduction of layout What is layout? Why we need layout? CMOS process brief Introduction of design rules Intra layer rules; Inter layer rules Layout of basic cells Active (Transistor), Passive (Resistor, Capacitor) Layout design flow Layout, DRC, LVS, PEX Slide 3

5 Outline of Lecture #3 Source of Variations Corner Analysis ( 工艺角分析 ) Random Var., Mismatch ( 失配 ) & Monte-carlo Deterministic Mismatch Intrinsic & Extrinsic Mismatch Matching for MOSFET (Current & Voltage) Matching for Resistor & Capacitor Slide 4

6 Process Variability Process variability become increasingly significant Shrinking devices (W, L, t ox ) Thin Gate Oxide, Fewer Dopants, sensitive to geometry Higher integrity (Number of devices) Billions of devices per die, higher chance of failure Ultra-low voltage ( V th ) Vth is not scaling by Vdd, Less headroom, more sensitive to V th Slide 5

7 Process variation Global: die-to-die, waferto-wafer t ox (thickness of oxide) Transistor W & L N/Pwell doping (V th ) Stress induced effects (V th ) Local: within the die variations Transistor W & L V th mismatch Slide 6

variations are uncorrelated Small transistors more

8 Width and length variations (Geometry) Caused by variations in the lithographic process Width and Length variations are uncorrelated Small transistors more sensitive to W/L changes Intel 65nm 6T SRAM cell 65nm CMOS NAND cell Slide 7

9 V th Variation Random fluctuations due to relatively small number of dopants ( 掺杂 ) in the channel. V th variance is inversely proportional to transistor area Pelgrom's Law: Slide 8

10 Temperature Environmental variations Ambient temperature ranges On-die temperature elevated by chip self-power consumption Thermal distribution of a tablet Thermal distribution of an CPU Slide 9

11 Variation classifications According to the features Deterministic & Random According to the consequence: Common-mode & Mismatch Global variation Var. Process Var. (Device, interconnect) 1. Lithography 2. Deposition 3. Doping Deterministic Commonmode Variations Environmental Var. (Vdd, Temp) 1. Temp. 2. Supply. Random Mismatch Slide 10

12 Process Variation & Matching Issue Source of Variations Corner Analysis 工艺角分析 (PVT analysis) Random Var., Mismatch & Monte-carlo Deterministic Mismatch Intrinsic & Extrinsic Mismatch Matching for MOSFET (Current & Voltage) Matching for Resistor & Capacitor Slide 11

13 Corner analysis for Common-mode Var. Model extremes of process variations in simulation Corners Typical (T) Fast (F) Slow (S) Factors nmos speed pmos speed C&R (wire) Voltage Temp. Continuous & Linear Assumption! Slide 12

14 Corner analysis for Common-mode Var. Circuits are simulated in different corners to verify different performance and correctness specifications Process (P) Temperature (T) Voltage (V) Slide 13

15 FEOL & BEOL Corners FEOL Front-end of line 前端工艺 BEOL Back-end of line 后端工艺 Slide 14

16 FEOL & BEOL Corners 前端工艺角 FEOL Corner For MOSFET only 3 Corners: Fast, Typical, Slow 后端工艺角 BEOL Corner For Interconnections For smaller tech. nodes Process, Voltage, Temperature (PVT) RC_best, RC_worst Slide 15

17 An example of Corner Analysis Common source amplifier with diode-type load Differential circuit is more sensitive to mismatch! DC-Bias (V) TT FF SS FS SF DC-Bias (V) PM (10deg) TT FF SS FS SF PM (10deg) P & N Mismatch DC-Gain (db) TT FF SS FS SF DC-Gain GBW (MHz) TT FF SS FS SF GBW (MHz) Slide 16

18 An example of Corner Analysis Common source amplifier with diode-type load Differential circuit is sensitive to mismatch! Corner can help to check whether all the devices are correctly biased Single-end Differential-end Slide 17

19 Process Variation & Matching Issue Source of Variations Corner Analysis Random Var., Mismatch & Monte-carlo Deterministic Mismatch Intrinsic & Extrinsic Mismatch Matching for MOSFET (Current & Voltage) Matching for Resistor & Capacitor Slide 18

20 Application of CMOS cap. Capacitor array is widely used (ADC, Switch Cap ) Capacitor array requires accurate ratio Capacitors in SAR-ADC Capacitors in S-C circuit Slide 19

21 Variation classifications According to the features Deterministic & Random According to the consequence: Common-mode & Mismatch Variations Deterministic Commonmode Variations Mismatch Random Intrinsic Extrinsic Pelgrom s Law V th, W/L, T ox Slide 20

22 Random Mismatch Same with random variations Geometry & V th mismatch decrease with area V th : Geometry: uncertainty Small area Large area Slide 21

23 Statistical Models More realistic than corner models (Corner to bad) Especially when the number of devices is very large Can work without linearcontinuous assumption Suitable for nonlinear or complex circuit Possible to evaluate the mismatch issue 99.73% in 3 region Slide 22

The result is a distribution plot of design constraints,

24 General Concept Monte Carlo involves simulating a circuit over a wide range of randomly chosen devices parameters The result is a distribution plot of design constraints, e.g., delay or noise margin (need enough samples) Slide 23

25 Variation classifications Common mode variations, mismatch According to the consequence: Common-mode & Mismatch Variations Deterministic Commonmode Variations Mismatch Corner Analysis Monte-carlo Intrinsic Extrinsic Random Monte-carlo Slide 24

26 Process Variation & Matching Issue Source of Variations Corner Analysis Random Var., Mismatch & Monte-carlo Deterministic Mismatch Intrinsic & Extrinsic Mismatch Matching for MOSFET (Current & Voltage) Matching for Resistor & Capacitor Slide 25

27 Extrinsic mismatch Extrinsic-Anisotropic Annealing (Asymmetry Fabrication) Etching (Undercut, Nonlinear Fabrication) Slide 26

28 Extrinsic mismatch Extrinsic-Anisotropic Annealing (Asymmetry Fabrication) Etching (Undercut, Nonlinear Fabrication) Slide 27

29 Extrinsic mismatch Extrinsic-Surroundings Annealing Mismatch (Solution: Direction+Dummy) Etching (Solution: Dummy) Same Direction Dummy Block All devices within the die should be in the same direction! Slide 28

30 Source of deterministic process error Polishing seriously affects t ox (within wafer) Photolithography are not uniform (within die) t ox 1-D case x x-location Single chip t ox x Slide 29

31 deterministic error cancelling in Layout 1 st order error cancelling 1D case: symmetrical placement Slide 30

32 deterministic error cancelling in Layout 1 st order error cancelling 1D case: symmetrical placement 2D case: centroid placement & Coincidence Example: A:B:C:D=4:2:1:1 Small t ox large t ox Slide 31

33 Source of deterministic process error Polishing seriously affects t ox (within wafer) Photolithography are not uniform (within die) t ox x Slide 32

34 deterministic error cancelling in Layout 2 nd order error reduction (difficult to be cancelled) Dispersion ( 交错排列 ) Compactness ( 紧凑排列 ) Large distance = large error! D max =4.12 D max =2.8 Compact Dispersion Slide 33

35 Intrinsic Mismatch (Environmental) Temperature effect is similar to process var. Single source generates 1 st order var., Multi-source generates higher order var. Slide 34

36 Process Variation & Matching Issue Source of Variations Corner Analysis Random Var., Mismatch & Monte-carlo Deterministic Mismatch Intrinsic & Extrinsic Mismatch Matching for MOSFET (Current & Voltage) Matching for Resistor & Capacitor (Additional) Few examples Slide 35

37 Symmetry Rule of thumb in Analog layout Axial symmetry (1-D), Centroid (2-D), dummy, direction Dispersion Interdigitated Compact Slide 36

38 Interdigitated Layout for Transistors & Res. Interdigitated components for better matching Schematic Layout Slide 37

39 Dummy for active & passive devices Dummy block for to achieve identical surroundings. Without dummy With dummy Slide 38

40 Example layout (1D matching) Interdigitating with dummy for better matching. Ex. Commonmode feedback circuit Symmetry? Dispersion? Compact? Slide 39

41 Example layout (1D matching) Interdigitating with dummy for better matching. Ex. Input pair of an opam Symmetry? Dispersion? Compact? Slide 40

42 Example layout (2D matching) Centroid layout can cancel the 1 st order deterministic error. Ex. Input pair of an opam However it introduces the complexity of wiring. Symmetry? Dispersion? Compact? Slide 41

43 Wiring for centroid MOSFETs Wiring for centroid MOSFETs is difficult Extra- overlaps in the connector and base wiring (dummy) Same length, same metals, same overlaps Each transistor has 4 leads! Slide 42

44 Layout and wiring for cap. array Centroid + dummy cap. to cancel the deterministic error. Ex. SAR ADC cap. array Symmetry? Dispersion? Compact? 1 layer of dummy is not enough in advanced technology!!! Slide 43

45 Source of Variations Summary Geometry, V th, Environment Corner Analysis Random Var., Mismatch & Monte-carlo Deterministic Mismatch Intrinsic & Extrinsic Mismatch Examples for layout matching Better understanding requires more practice!!! Slide 44

46 Variation classifications Common mode variations, mismatch According to the consequence: Common-mode & Mismatch Variations Deterministic Commonmode Variations Mismatch Corner Analysis Monte-carlo Intrinsic Extrinsic 3 key approaches Random Monte-carlo Slide 45

47 Homework #1 Due on May 7 th Homework #2 Reminder for next week Corner of monte-carlo simulation (pre-layout, postlayout) Slide 46

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