( CCS ) CCS CCS CCS (FFT) (IIR) (FIR) 51 5 FIR..
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- 辞杂 那拉
- 9 years ago
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1
2 ( CCS ) CCS CCS CCS (FFT) (IIR) (FIR) 51 5 FIR ] A/D D/A TMS320C5410 DSP TMS320C54X
3 TI TMS320C5410 TMS320C5416 TMS320LF2407 DSP DSP TMS320C5410 TI 54 DSP DSP DSP TMS320C5416 TI 54 DSP 5410 HPI( ) 16BIT ( 5416 ) 5410 ( 5416 ) USB A/D D/A USB PHILIPS ISP1362 USB2.0 OTG(on The Go USB A/D D/A A/D D/A 5410( 5416) A/D D/A MP3 TMS320LF2407 DSP UART - - 2
4 CPLD 5410 ( 5416 ) 2407 ( 1-1-1) 1 TMS320C5410 ( 5416 ) 2 TMS320LF CPLD ( ) 4 A/D D/A 5 A/D D/A
5 7 USB2.0 OTG (USB2.0 ) 8 UART ( ) DSPII
6 V ±12V 5V 3.3V 2.5V 5V 2. DSP USB DSP JTAG 14 DSP 3. DSP DSP DSP CCS M 100M 800*600 USB DB9 RJ USB - - 5
7 1.TMS320C TMS320C5410 DSP CY7C K 16 SRAM TE39LV800 8M FLASH ( 1-3-1) JTAG DSP 6 HPIENA( ),BIO(IO ),MP/MC( ),CLKMD3( 3),CLKMD2( 2),CLKMD1( 1), ON 1 OFF
8 ( 1-3-2)
9 TMS320C5416 DSP TMS320C5416 CY7C K 16 SRAM( ) TE39LV800 8M FLASH( ) ( 1-3-3)
10 2.TMS320LF2407 TMS320LF2407 DSP CY7C K 16 SRAM ( 1-3-4) JTAG DSP - - 9
11 - - 10
12 ( 1-3-5)
13 3.CPLD Xilinx XC95144 CPLD / CPLD CPLD CPLD
14 4.USB2.0 OTG( ) USB (IPS1362) USB (H-A) OTG( ) OTG( ) Host( ) OTG-B Device( ) OTG-A ( 1-3-6) USB ( 1-3-7) USB CON302 (1) D+ ( ) (2) D-( ) (3) H_OC2( 1) CON304 (1) OTG_DP ( ) (2) OTG_DM( ) (3) H_OC1( 1) CON306 (1) OTG_D+ ( ) (2) OTG_D-( ) (3) V_BUS( ) TP301 CLKOUT( )
15 USB 5. A/D D/A AIC23 A/D D/A Line-In( ) Line-Out( ) Mic-In( ) Phone-Out( ) ( 1-3-8) ( 1-3-9)
16 TPb01 Signal Power ( ) TPb02 VDD( ) TPb11 CLKOUT( ) TPb12 Lineout right( ) TPb13 Lineout left( ) TPb14 Phone right( ) TPb15 Phone left( ) TPb16 Linein right( ) TPb17 linein left( ) 6. A/D D/A AD50CDW / ( ) ( ) 7.UART UART SC16C550 MAX
17 ( ) UART TP401 CLK ( ) UART 8. UART Ethernet( ) RTL8019AS RJ-45( 45)
18 ( ) ( ) UART( )
19 ( ) 1.RW ( ) 2.CS ( ) 3.IOR(I/O ) 4.IOW(I/O ) 5.IOCHRDY(I/O ) 6.INT0( 0) 7.CLK( ) 9. ICL8038 ( ) DSP
20 LCD 16 ( ) LCD 12. LCD
21 13. 8 LED (CS) ( ) ( ) 15. :
22 CPLD
23 ( CCS ) 2.1 CCS CCS Code Composer Studio TMS320 CCS CCS1.1 CCS1.2 CCS2.0 CC2000 ( C2XX ) CCS5000 ( C54XX ) CCS6000 ( C6X ) CCS CCS5000 TI CCS5000 Windows C DSP C DSP CCS5000 C DOS CCS5000 (PDM) MS CCS5000 Windows95 Windows-me PDM( ) FFT( ) DSP CCS5000 PC CCS5000 ( ) DOS CCS5000 DOS CCS5000 CCS5000 CCS5000 C
24 C DSP DSP (GEL) CCS
25 2.2 CCS CCS 1 DSP 2 DSP C2000V2.2 CCS2000 C5000V2.2 CCS5000 EPP USB 3 CCS2000 C2000V2.2 SETUP INSTALL CODE COMPOSER STUDIO ( ) CCS2000 ADOBE ACROBAT READER ( ) CCS
26 YES I DO accept all the terms of the preceding License Agreement ( ) Next CCS2000 CODE COMPOSER STUDIO Online Manuals Select All ( ) Next Browse ( ) CCS5000 D:\TI\2000 CCS5000 Next
27 Finish Yes I want to restart my computer now FINISH CCS5000 CCS2000 CCS5000 D:\TI\5000 CCS2000 EPP
28 CCS EPP EPP EPP_Driver C2000DRV CCS2000 CCS5000DRV CCS5000 CCS2000 SETUPCC2XX BROWSE ( ) CCS2000 CCS2000 D:\TI\2000\ CCS5000 CCS5000 D:\TI\5000\ NEXT NT( WINDOWS ) NT CCS5000 CCS2000 EPP CCS CCS CCS2 `2000 CCS2 `5000 SETUP CCS2 `
29 SETUP CCS2 `5000 CCS CCS CCS SETUP CODE COMPOSER STUDIO CCS2000 CCS (Setup CCS2( C2000)) Install a Device Driver( ) Drivers( ) Sdgo2XX.drv
30 OK Available Board /Simulator Type SYSTEM CONFIGURATION( ) BOARD PROPERTIES( ) sdgo2xx Uninstall ( ) Add to System ( ) Add to System ( )
31 Board Name & Data File( ) Next I/O I/O 0X240 0X378 Next Processor Configuration ( ) Processor Configuration( ) Available Processor( ) TMS320C2400 CCS5000 TMS320C5400 Add Single( ) CPU_
32 Next CPU
33 CPU F2407A.GEL Drivers( ) Finish EPP CCS5000 CCS2000 CCS5000 Sdgo5XX.drv Sdgo5XX CPU C5410.GEL C5410A.GEL Drivers( ) 14P 1 2 CCS CCS2000 CCS5000 DSP USB USB EPP USB_Driver SETUP.EXE C /TI CCS
34 Browse CCS CCS2000 D:\TI\2000 CCS CCS5000 D:\TI\5000 USB CCS USB CCS EPP SETUP CODE COMPOSER STUDIO( ) CCS5000 CCS Setup CCS2( C5000) Install a Device Driver ( ) Drivers D \TI\5000\Drivers\... tixds54x. dvr
35 OK Available Board /Simulator Type System Configuration ( ) Board Properties ( ) Auto-generate board data file with extra configuration ( ) Configuration File ( ) Browse ( )
36 ICETEK.cfg CCS Drivers( ) (D \TI\5000\Drivers\...) Next I/O 0X240 0X000 Next Processor Configuration ( ) Processor Configuration( ) Available Processor( ) TMS320C5400 CCS2000 TMS320C2400 Add Single( ) CPU_
37 Next CPU CPU C5410.gel C5410A.gel Drivers Finish USB CCS2000 CCS5000 CCS2000 TIXDS24X.DVR tixds24x CPU f2407a.gel Drivers( ) USB USB USBDevice(USB ) mdpjtag.inf
38 C5410 CCS SETUP CODE COMPOSER STUDIO CCS (Setup CCS2( C5000)) C5410 Device Simulator Import( ) DSP
39 2.3 CCS CCS5000 ( 2-3-1) CCS Volume1 1 CCS \myprojects volume1 CCS \tutorial\sim54xx\volume1 7 volume.c load.asm vectors.asm volume.h volume.cmd sine.dat volume.gel C C GEL 2 CCS Project ( ) new open new
40 ( 2-3-2) 3 CMD 1 Project Add Files to Project volume1 volume.c volume.pjt Add Files volume1 Asm Source Files *.a*;*.s* load.asm vectors.asm C volume.c 2 ( 2-3-3) *.cmd volume.cmd Link Command File(*.cmd) 3 C Run Time Support Library rts.lib CCS \c5400\cgtools\lib Object Library Files *.o*,*.l* 4 volume.pjt Scan All Dependencies volume.c volume.h Iclude Build CCS
41 volume.c CCS 1 "volume example started " dataio() processing() 2 processing() gain load() processing() processingload 3 dataio() 5 Building Project Rebuild All CCS CCS.out volume1 debug ( ) File Load Program volume1 debug volume.out CCS DSP Dissassembly CCS stdout ( 2-3-4) Debug Go Main main C C View Mixed Source/ASM
42 ( 2-3-5) C Debug Run stdout volume example started Debug Run 6 CCS View CPU Registers View Memory Add to Watch Window Watch Watch
43 View Graph / Time/Frequency Graph Property DSP
44 C DSP 1. CCS 2. DSP TMS320C DSP y n ( n) = h( m ) x( n m ) m = 0 1 y (n) 2 n m CCS Ex4_1.pjt 3..out (.out ) DSP 4. x, h y Watch Add Watch Window
45
46 2 (FFT) 1. FFT 2. C DSP 1. CCS 2. DSP TMS320C DSP DFT FFT, FFT DFT N 2 ( N/2 )log 2 N x(n) X ( k) N = 1 N = 0 x[ n] nk W N W N = e j2π / N W N FFT DIT DIF FFT N x(n) x(0), x(2), x(4),, x(n-2) x(1), x(3), x(5),, x(n-1) x(n) N DFT X ( k) = W N X ( k) = 2 N N / 2 1 n= 0 x N / 2 1 2nk ( 2n) W + x( 2n 1) N + n= 0 W = = N / 2 1 n= 0 j(2π ) / N 2 j2π /( N / 2) [ e ] = e WN / 2 x W N / 2 1 nk k ( 2n) W + W x( 2n ) N / 2 + 1W N n= 0 (2n+ 1) k N nk N / 2 X ( k) = Y k ( k) + W Z( k) N Y(k) Z(k) N/2 W N W k + N / 2 N = W k N X ( k + N / 2) = Y k ( k) W Z( k) N
47 Y(k) Z(k) N DFT 2 DFT 2 FFT log 2 (N) N/2 2 FFT N 8 FFT x(0) X(0) x(4) W 0 X(1) x(2) x(6) W 0 W 0 W 2 W 0 X(2) X(3) x(1) W 1 X(4) x(5) x(3) x(7) W 0 W 0 W 0 W 2 W 2 W 3 X(5) X(6) X(7) FFT FFT 2. CCS Ex4_3.pjt 3..out (.out ) DSP
48 4. 5. view->graph->time/frequency : Start Address x_re Acquisition buffer size Display Data size 64 DSP Data Type 32-bit floating point DFT y_re Start Address y_re 5 Watch i, j, k, m, n, a, b,c Debug Restart Go main FFT
49 6. N x N TMS320C5000 FFT 3. FFT
50 3 (IIR) 1. IIR 2. C DSP 1. CCS 2. DSP TMS320C DSP x[k] y[k] z N y[ k] = a x[ k i] + b y[ k i] H ( z ) M i i i= 0 i= 1 M k b k z Y ( z ) k = 1 = = N X ( z ) k 1 + a k z k = 0 IIR IIR s z H(s) H(z) 1 z s = c 1+ z CCS Ex4_6.pjt 2..out (.out ) DSP
51 3. 4. Watch H(z) ptr_b ptr_a 5. view->graph->time/frequency : Start Address hwdb Acquisition buffer size Display Data size 50 DSP Data Type 32-bit floating point ( ) 5. fp fr fs ap ar ( )
52 4 (FIR) 1. FIR 2. C DSP 1. CCS 2. DSP TMS320C DSP DSP y N 1 N 1 ( n) = a x( n k) + b y( n k) k= 0 k k k= 0 X(n) Y(n) A k B k N B k A k h k, y N 1 () n h x( n k) = k k= 0 FIR FIR h(n) FIR x(n) (z 1 ) y(n) FIR h(n) Hd (w) Hd(n) w(n) FIR h(n) FIR h(n) 1. FIR 2. CCS Ex4_5.pjt
53 3..out (.out ) DSP ( ) 6. view->graph->time/frequency : Start Address hd Acquisition buffer size Display Data size 21 n=21 DSP Data Type 32-bit floating point 7. w h db Start Address w h db 21 n db 300 l m=1 (w)
54 (h) db m=2 (w) (h) db
55 m=3 w h db
56 m=4 w h db m=5 w
57 h db m
58 5 FIR 1 FIR 2. CCS. DSP. DSP MATLAB( ) MATLAB Toolbox Toolbox signal MATLAB FIR 1 FIR Hamming B=FIR1(N,Wn) N Wn 0.0<Wn< B N+1 2 FIR Hamming B=FIR1(N,Wn, high ) N Wn 3 FIR Hamming B=FIR1(N,Wn) Wn Wn=[W1,W2] W1 W2 MATLAB MATLAB Filter Design & Analysis Tools
59 Fliter Type Design Method IIR FIR Fliter Order Windows Specifications Hamming 16K Design Fliter 3K File->Export to C Header File
60 Export as 16 OK /* * Filter Design and Analysis Tool - Generated Filter Coefficients - C Source * Generated by MATLAB - Signal Processing Toolbox */ /* General type conversion for MATLAB generated C-code */ #include "tmwtypes.h" /* /* * Expected path to tmwtypes.h * D:\MATLAB6p1\extern\include\tmwtypes.h */ * Warning - Filter coefficients were truncated to fit specified data type! * The resulting response may NOT match generated theoretical response. * Use the Filter Design & Analysis Tool to design accurate fixed-point * filter coefficients! */ const int NL = 64; const int16_t NUM[64] = { -15, -28, -6, 31, 37, -10, -64, -44, 54, 115, 28, -140, -166, 46, 269, 178, -206, -422, -97, 477, 551, -149, -872, -576, 679, 1429, 345, -1842, -2412, 803, 6794, 11599, 11599, 6794, 803, -2412, -1842, 345, 1429, 679, -576, -872, -149, 551, 477,
61 -97, -422, -206, 178, 269, 46, -166, -140, 28, 115, 54, -44, -64, -10, 37, 31, -6, -28, -15 }; const int DL = 1; const int16_t DEN[1] = { }; const int16_t NUM[64] 1 DSP AD50 AD50 AD50 2 RPC03 Uc02 (3 5 )[ ] 2.5V JC05 3.3V,AD50 Master 3.\ad50fir\ad50.pjt Type LowPass HighPass Type BandPass 4 DSP
62 6. R338 AD50 3K, 1K 1K~3K
63 6 A/D D/A 1. DSP MCBSP 2. D/A A/D 3. MCBSP AIC23 4. AIC23 MCBSP. CCS. DSP. DSP AIC23 MCBSP 1 AIC23 AIC23 TI A/D D/A 3.3V 1.5V 48kHz A/D 100dB SPI 2-wire I 2 S SPI USB Ω 30mW (power-down) 15uW 2 AIC23 AIC23 1 AIC23 CS( ) SDIN( ) SCLK( MODE( ) AIC23 LRCIN( ) DIN( ) LROUT( ) DOUT( ) BLCK( AIC23 2 AIC23 RLINEIN( ) LLINEIN( ) 1VRMS MICIN( ) MIC 1 5 0~20dB LINEIN A/D RHPOUT( ) LHPOUT( ) 3.3V 32Ω 30mW +6dB~-73dB D/A MIC Bypass ROUT( ) LOUT( ) AIC23 D/A 1V 1Vrms
64 AIC23 AIC23 A/D D/A AIC23 XTI( ) XTO( ) AIC23 MIC MIC AIC23 3 AIC23 1 AIC23 AIC23 SPI (2-wire) MODE SPI MODE 2-wire SPI 2 AIC
65 LRS / 0 1 LIM 0 1 LIV4~ ±12dB dB 1.5dB/LSB X LSR / 0 1 LZC 0 1 LHV 6~ dB =-73dB DACM D/A
66 DEEMP kHz 10 44kHz 11=48kHz ADCHP A/D 0 1 OFF 0 1 CLK 0 1 OSC 0 1 OUT 0 1 DAC D/A 0 D/A 1 D/A ADC A/D 0 A/D 1 A/D MIC 0 1 LINE 0 1 MS / 0 1 LRSWAP D/A 0 1 LRP D/A IWL FOR DSP CLKOUT 0 1 CLKIN 0 1 SR BOSR USB/Normal 0 1 USB
67 12MHz USB ACT 0 1 RES 4 MCBSP MCBSP 1 MCBSP DSP AC97 I 2 S SPI / A u 2 MCBSP MCBSP RSR RBR DRR XSR DXR compand A u MCBSP DR DX MCBSP CLKX CLKR MCBSP FSX FSR MCBSP CLKS XINT RINT CPU MCBSP SPSAx MCBSP 0039H 0 1 SPCR1 0000H 2 SPCR2 0001H PCR 000EH 1 XCR1 0004H 2 XCR2 0005H
68 1 SPCR 1~2 XRST RRST FRST 0 MCBSP 2 3 MCBSP 4 DXR 5 SPCR 1~2 XRST RRST FRST 1 MCBSP 6 MCBSP
69 AIC23 Bypass LINEIN AIC23 Bypass AIC23 D/A DSP AIC23 D/A HPOUT MCBSP0 AIC23 AIC23 DSP MCBSP0 AIC Bypass DSP 1 AIC23 AIC23 MODE SPI 2 CPLD AIC23 DSP MCBSP0 DSP 3 AIC23 ADC DAC 3 AIC23 (LINEIN) AIC23 (PHONE) AIC23 PHONE, 4.\aic23bypassda\aic pjt DSP
70
71 TMS320 DSP 1 TMS320C5410 DSP 1982 TI TMS320 DSP DSP TMS32010 TMS320 DSP C1x C2x C2xx C5x C54x C62x DSP C3x C4x C67x DSP C8x DSP TMS320C54x TMS320C54x CPU C54x : 1. TMS320C54x CPU TMS320C54x ALU *17 40 / MAC CSSU / ARAU
72 192K 64K 64K 64K I/O ROM / RAM DARAM RAM SARAM C54X DARAM DARAM 2 CPU DARAM DARAM TMS320C54x TMS320C54x DSP TMS320C54x DSP C54x / 4 PB 3 CB DB EB CPU CB DB EB 4 PAB CAB DAB EAB C54x ARAU0 ARAU
73 PB / MVPD READA 3 C54x CPU DB EB. C54x 192K 3 64K 64K 64K I/O C54x RAM ROM RAM RAM SARAM RAM DARAM C54x 26 CPU RAM C54X 3 I/O RAM ROM EPROM EEPROM 3 192K I/O C54x DARAM SARAM ROM RAM ROM 2. C54x 64K ROM RAM DARAM RAM SARAM PAGEN FF80H 128 ROM C54x ROM 28K 48K 2K ROM 2K ROM F800h~FFFFh TI 3. C54X 64K RAM SARAM DARAM C54x ROM RAM ROM 4.I/O
74 C54x I/O 64K 0000h~FFFFh PORTR PORTW I/O. C54x CPU CPU 40 ALU ~30 / CSSU CPU 1. C54x 40 ALU 40 A B ALU A B 40 ALU 16 ALU 16 ALU X DB ALU Y 4 A B CB T ALU 40 A B 2. A B ALU / ALU A / C54x CPU CPU C54x I/O BIO XF
75 1. I/O C54x 64K I/O 2 BIO XF BIO BIO XF 2. 3 TIM PRD TCR h 0025h 0026h TIM PRD TCR C54x 4 16 CLOCKOUT 0 3. C54x PLL PLL CPU CPU 4. HPI 8 HPI HPI CPU C54x HPI HPI 8 HD 7 0 HPI 8 16 C54x
76 2 TMS320C54X TMS320C54X A ACC ACCA ACCB ALU ARx ARP ASM B BRAF BRC BITC C16 C CC CMPT CPL Cond [d], [D] DAB DAR dmad Dmem DP dst dst_ EAB EAR extpmad FRCT hi (A) A A B 0 x 7 ST0 3 AR ST ASM 15 B ST1 4 ST1 16 / ST0 2 0 CC 3 ST1 ST1 D DAB 16 0 dmad ST0 9 0 DP 511 A B E EAB 23 ST1 A
77 HM IFR INTM K K3 K5 K9 lk Lmem mmr MMR MMRx MMRy n N OVA OVB OVdst OVdst_ Ovsrc OVM PA PAR PC pmad Pmem PMST prog [R] md RC RTN REA RSA SBIT SHFT SHIFT ST1 ST K K K AR0 AR7 SP XC n=1 2 RSBX SSBX XC (ST0 ST1) ST0 A ST0 B A B A B A B ST PA pmad RETF[D] 4 RSBX SSBX XC (0 SBIT 15) 4 0 SHFT SHIFT
78 Sind Smem SP src ST0 ST1 SXM T TC TOS TRN TS uns XF XPC Xmem Ymem 16 A B 0 1 ST1 ST0 / T TS 31 ST (1) ADD Smem, src ADD Smem, TS, src ADD Smem, 16, src[,dst] ADD Smem, [,SHIFT], src[,dst] ADD Xmem, SHFT, src ADD Xmem, Ymem, dst ADD # lk [,SHFT], src [,dst] ADD # lk, 16, src[,dst] ADD src, [,SHIFT][,dst] ADD src, ASM[,dst] ADDC Smem, src ADDM # lk, Smem ADDS Smem, src ACC ACC 16 ACC ACC ACC 16 ACC 16 ACC ASM 2 SUB Smem, src SUB Smem, TS, src SUB Smem, 16, src[,dst] ACC 16 ACC
79 SUB Smem, [,SHIFT], src[,dst] SUB Xmem, SHFT, src SUB Xmem, Ymem, dst SUB # lk [,SHFT], src [,dst] SUB # lk, 16, src[,dst] SUB src, [,SHIFT][,dst] SUB src, ASM[,dst] SUBB Smem, src SUBC Smem, src SUBS Smem, src ACC ACC 16 ACC 16 ACC ASM 3 MPY Smem, dst MPYR Smem, dst MPY Xmem, Ymem, dst MPY Smem, # lk, dst MPY # lk, dst MPYA dst MPYA Smem MPYU Smem, dst SQUR Smem, dst SQUR A, dst T T T ACCA T ACCA T ACCA 4 MAC Smem, src MAC Xmem, Ymem src[,dst] MAC # lk, src[,dst] MAC Smem, # lk, src[,dst] MACR Smem, src MACR Xmem, Ymem,src [,dst] MACA Smem, [,B] MACA T, src[,dst] MACAR Smem[,B] MACAR T, src[,dst] T ACC ACC T ACC ACC T ACC ( ) ACC ( ) ACCA ACCB T ACCA ACC ACCA ACCB ( ) T ACCA ACC ( ) MACD Smem, pmad, src MACP Smem, pmad, src MACSU Xmem, Ymem, src
80 MAS Smem, src MASR Smem, src MAS Xmem, Ymem, src[,dst] MASR Xmem, Ymem, src[,dst] MASA Smem [,B] MASA T, src[,dst] MASAR T, src[,dst] SQURA Smem, src SQURS Smem, src T ACC T ACC ( ) ACC ACC ACCB ACCA src ACCA T src ACCA T ( ) 5 DADD Lmem, src[,dst] DADST Lmem, dst DRSUB Lmem, src DSADT Lmem, dst DSUB Lmem, src DSUBT Lmem, dst T 16 T ACC / 16 T 6 ABDST Xmem, Ymem ABS src[,dst] CMPL src[,dst] DELAY Smem EXP src FIRS Xmem, Ymem, pmad LMS Xmem, Ymem MAX dst MIN dst NEG src[,dst] NORM src[,dst] POLY Smem RND src[,dst] SAT src SQDST Xmem, Ymem ACC 2 1 AND Smem, src AND # lk[,shft], src[,dst] ACC ACC
81 AND # lk, 16, src[,dst] AND src[,shift] [,dst] ANDM # lk, Smem 16 ACC 2 OR Smem, src OR # lk[,shft], src[,dst] OR # lk, 16, src[,dst] OR src[,shift] [,dst] ORM # lk, Smem ACC ACC 16 ACC 3 XOR Smem, src XOR # lk[,shft], src[,dst] XOR # lk, 16, src[,dst] XOR src[,shift] [,dst] XORM # lk, Smem ACC ACC 16 ACC 4 ROL src ROL TC src ROR src SFTA src, SHIFT[,dst] SFTC src SFTL src, SHIFT[,dst] TC 5 BIT Xmem, BITC BITF Smem, # lk BITF Smem CMPM Smem, # lk CMPR CC, ARx T ARx AR0 3 1 B[D] pmad BACC[D] src BANZ[D] pmad, Sind BC[D] pmad, cond[,cond[,cond]] FB[D] extpmad FBACC[D] src AR 0 ACC
82 2 CALA[D] src CALL[D] pmad CC[D] pmad,cond[,cond[,cond]] FCALA[D] src FCALL[D] extpmad ACC 3 INTRK TRAPK 4 FRET[D] FRETE[D] RC[D] cond[,cond[,cond]] RET[D] RETE[D] RETF[D] 5 RPT Smem RPT # k RPT # lk RPTB[D] pmad RPTZ dst, # lk ACC 0 6 FRAME K POPD Smem POPM MMR PSHD Smem PSHM MMR 7 IDLE k MAR Smem NOP RESET RSBX N, SBIT SSBX N, SBIT XC n, cond[,cond[,cond]]
83 4 1 DST src, Lmem ST T, Smem ST TRN, Smem ST # lk, Smem STH src, Smem STH src, ASM, Smem T TRN ACC ASM STH src, SHFT, Xmem STH src[,shift], Smem STL src, Smem STL src, ASM, Smem ACC ACC ACC ASM STL src, SHFT, Xmem STL src[,shift], Smem STL M src, MMR STM # lk, MMR ACC ACC 2 DLD Lmem, dst LD Smem, dst LD Smem, TS, dst LD Smem, 16, dst LD Smem[,SHIFT], dst LD Xmem, SHFT, dst LD # K, dst LD # lk[,shft], dst LD # lk, 16, dst LD src, ASM[,dst] LD src[, SHIFT], dst LD Smem, T LD Smem, DP LD # k9, DP LD # k5, ASM LD # k3, ARP LD Smem, ASM ACC 16 ACC ACC Xmem ACC ACC ACC 16 ACC ASM T DP 9 DP 5 3 ARP 4 0 ASM
84 LDM MMR, dst LDR Smem, dst LDU Smem, dst LTD Smem ACC T 3 CMPS src, Smem SACCD src, Xmem, cond SRCCD Xmem, cond STRCD Xmem, cond T 4 ST src, Ymem ACC LD Xmem, dst ST src, Ymem ACC T LD Xmem, T 5 LD Xmem, dst / MAC Ymem, dst_ LD Xmem, dst / MACR Ymem, dst_ LD Xmem, dst / MAS Ymem, dst_ LD Xmem, dst / MASR Ymem, dst_ 6 ST src, Ymem ACC ADD Xmem, dst ST src, Ymem ACC ADD Xmem, dst 7 ST src, Ymem / MAC Xmem, dst ST src, Ymem / MACR Xmem, dst ST src, Ymem / MAS Xmem, dst ST src, Ymem /
85 MASR Xmem, dst ST src, Ymem MPY Xmem, dst 8 MVDD Xmem, Ymem MVDK Smem, dmad MVDM dmad, MMR MVDP Smem, pmad MVKD dmad, Smem MVMD MMR, dmad MVMM MMRx, MMRy MVPD pmad, Smem PORTR PA, Smem PORTW Smem, PA READA Smem ACCA WRITA Smem ACCA 5 1 FIRS MACD MACP MVDK MVDM MVDP MVKD MVMD MVPD READA WRITA MMR MMR 2 RPT RPTZ ADDM ANDM B[D] BACC[D] BANZ[D]
86 BC[D] CALA[D] CALL[D] CC[D] CMPR DST FB[D] FBACC[D] FCALA[D] FCALL[D] FRET[D] FRETE[D] IDLE INTR LD ARP LD DP MVMM ORM RC[D] RESET RET[D] RETF[D] RND RPT RPTB[D] RPTZ RSBX SSBX TRAP XC XORM 32 IDLE MMR
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