查询 MSP430F1111A 供应商 捷多邦, 专业 PCB 打样工厂,24 小时加急出货 SLAS241G SEPTEMBER 1999 REVISED AUGUST 2003 Low Supply Voltage Range 1.8 V 3.6 V Ultralow-Power Consump

Transcription

1 查询 MSP43FA 供应商 捷多邦, 专业 PCB 打样工厂,24 小时加急出货 Low Supply Voltage Range.8 V 3.6 V Ultralow-Power Consumption Active Mode: 6 µa at MHz, 2.2 V Standby Mode:.7 µa Off Mode (RAM Retention):. µa Wake-Up From Standby Mode in less than 6 µs 6-Bit RISC Architecture, 25 ns Instruction Cycle Time Basic Clock Module Configurations: Various Internal Resistors Single External Resistor 32-kHz Crystal High-Frequency Crystal Resonator External Clock Source 6-Bit Timer_A With Three Capture/Compare Registers Slope A/D Converter With External Components On-Chip Comparator for Analog Signal Compare Function or Slope A/D Conversion Serial Onboard Programming, No External Programming Voltage Needed Programmable Code Protection by Security Fuse Family Members Include: MSP43C: KB ROM, 28B RAM MSP43C: 2KB ROM, 28B RAM MSP43C2: 4KB ROM, 256B RAM MSP43FA: KB + 28B Flash Memory 28B RAM MSP43FA: 2KB + 256B Flash Memory 28B RAM MSP43F2A: 4KB + 256B Flash Memory 256B RAM Available in a 2-Pin Plastic Small-Outline Wide Body (SOWB) Package, 2-Pin Plastic Small-Outline Thin Package, 2-Pin TVSOP (FxA only) and 24-Pin QFN For Complete Module Descriptions, Refer to the MSP43xxx Family User s Guide, Literature Number SLAU49 description The Texas Instruments MSP43 family of ultralow power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 6-bit RISC CPU, 6-bit registers, and constant generators that attribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6µs. The MSP43xx series is an ultralow-power mixed signal microcontroller with a built-in 6-bit timer, versatile analog comparator and fourteen I/O pins. Typical applications include sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system. Stand alone RF sensor front end is another area of application. The I/O port inputs provide single slope A/D conversion capability on resistive sensors. TA PLASTIC 2-PIN SOWB (DW) AVAILABLE OPTIONS PACKAGED DEVICES PLASTIC 2-PIN TSSOP (PW) PLASTIC 2-PIN TVSOP (DGV) PLASTIC 24-PIN QFN (RGE) MSP43CIRGE MSP43CIRGE MSP43C2IRGE MSP43FAIRGE MSP43FAIRGE MSP43F2AIRGE MSP43CIDW MSP43CIDW MSP43CIPW MSP43CIPW MSP43FAIDGV 4 C to 85 C MSP43C2IDW MSP43C2IPW MSP43FAIDGV MSP43FAIDW MSP43FAIPW MSP43F2AIDGV MSP43FAIDW MSP43FAIPW MSP43F2AIDW MSP43F2AIPW Product Preview Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright Texas Instruments Incorporated

2 DW, PW, or DGV PACKAGE (TOP VIEW) RGE PACKAGE (TOP VIEW) TEST V CC P2.5/R osc V SS XOUT XIN RST/NMI P2./ACLK P2./INCLK P2.2/CAOUT/TA P.7/TA2/TDO/TDI P.6/TA/TDI P.5/TA/TMS P.4/SMCLK/TCK P.3/TA2 P.2/TA P./TA P./TACLK P2.4/CA/TA2 P2.3/CA/TA NC V SS XOUT XIN RST/NMI P2./ACLK P2.5/R OSC V CC TEST P.7/TA2/TDO/TDI P.6/TA/TDI NC P.5/TA/TMS P.4/SMCLK/TCK P.3/TA2 P.2/TA P./TA P./TACLK P2./INCLK P2.2/CAOUT/TA NC P2.3/CA/TA P2.4/CA/TA2 NC functional block diagram Note: Power pad and NC pins not internally connected XIN XOUT V CC V SS RST/NMI P. 7 8 Rosc Oscillator System Clock ACLK SMCLK /2/4 KB ROM/ Flash+26/256B Flash INFO C : ROM F : Flash 28/256B RAM Power-on- Reset Outx CCIxA TACLK SMCLK I/O Port P 8 I/O s, All With Interrupt Capabililty JTAG MCLK MAB, 6 Bit MAB, 4 Bit CPU Incl. 6 Reg. Test JTAG MDB, 6 Bit Bus Conv. MCB MDB, 8 Bit TEST ACLK SMCLK Watchdog Timer 5/6 Bit Timer_A 3 CC Register CCR//2 x =,, 2 TACLK or INCLK CCI Outx CCIx CCIx Comparator-A Input Multiplexer RC Filtered O/P Internal Vref Analog Switch INCLK CCI Out CCI I/O Port P2 6 I/O s All With Interrupt Capabililty ACLK DCOR 6 P2. 2.5

3 NAME TERMINAL DW, PW, or DGV NO. RGE NO. Terminal Functions I/O DESCRIPTION P./TACLK 3 3 I/O General-purpose digital I/O pin/timer_a, clock signal TACLK input P./TA 4 4 I/O General-purpose digital I/O pin/timer_a, capture: CCIA input, compare: Out output/bsl transmit P.2/TA 5 5 I/O General-purpose digital I/O pin/timer_a, capture: CCIA input, compare: Out output P.3/TA2 6 6 I/O General-purpose digital I/O pin/timer_a, capture: CCI2A input, compare: Out2 output P.4/SMCLK/TCK 7 7 I/O General-purpose digital I/O pin/smclk signal output/test clock, input terminal for device programming and test P.5/TA/TMS 8 8 I/O General-purpose digital I/O pin/timer_a, compare: Out output/test mode select, input terminal for device programming and test P.6/TA/TDI 9 2 I/O General-purpose digital I/O pin/timer_a, compare: Out output/test data input terminal P.7/TA2/TDO/TDI 2 2 I/O General-purpose digital I/O pin/timer_a, compare: Out2 output/test data output terminal or data input during programming P2./ACLK 8 6 I/O General-purpose digital I/O pin/aclk output P2./INCLK 9 7 I/O General-purpose digital I/O pin/timer_a, clock signal at INCLK P2.2/CAOUT/TA 8 I/O General-purpose digital I/O pin/timer_a, capture: CCIB input/ comparator_a, output/bsl receive P2.3/CA/TA I/O General-purpose digital I/O pin/timer_a, compare: Out output/ comparator_a, input P2.4/CA/TA2 2 I/O General-purpose digital I/O pin/timer_a, compare: Out2 output/ comparator_a, input P2.5/Rosc 3 24 I/O General-purpose digital I/O pin/input for external resistor that defines the DCO nominal frequency RST/NMI 7 5 I Reset or nonmaskable interrupt input TEST 22 I Selects test mode for JTAG pins on Port. The device protection fuse is connected to TEST. VCC 2 23 Supply voltage VSS 4 2 Ground reference XIN 6 4 I Input terminal of crystal oscillator XOUT 5 3 I/O Output terminal of crystal oscillator TDO or TDI is selected via JTAG instruction.

4 short-form description CPU The MSP43 CPU has a 6-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 6 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. instruction set The instruction set consists of 5 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table shows examples of the three types of instruction formats; the address modes are listed in Table 2. Program Counter Stack Pointer Status Register Constant Generator General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register PC/R SP/R SR/CG/R2 CG2/R3 R4 R5 R6 R7 R8 R9 R R R2 R3 R4 R5 Table. Instruction Word Formats Dual operands, source-destination e.g. ADD R4,R5 R4 + R5 > R5 Single operands, destination only e.g. CALL R8 PC >(TOS), R8 > PC Relative jump, un/conditional e.g. JNE Jump-on-equal bit = Table 2. Address Mode Descriptions ADDRESS MODE S D SYNTAX EXAMPLE OPERATION Register MOV Rs,Rd MOV R,R R > R Indexed MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) > M(6+R6) Symbolic (PC relative) MOV EDE,TONI M(EDE) > M(TONI) Absolute MOV &MEM,&TCDAT M(MEM) > M(TCDAT) Indirect M(R) > M(Tab+R6) Indirect autoincrement M(R) > R R + 2 > R Immediate MOV #X,TONI MOV #45,TONI #45 > M(TONI) NOTE: S = source D = destination

5 operating modes The MSP43 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: Active mode AM; All clocks are active Low-power mode (LPM); CPU is disabled ACLK and SMCLK remain active. MCLK is disabled Low-power mode (LPM); CPU is disabled ACLK and SMCLK remain active. MCLK is disabled DCO s dc-generator is disabled if DCO not used in active mode Low-power mode 2 (LPM2); CPU is disabled MCLK and SMCLK are disabled DCO s dc-generator remains enabled ACLK remains active Low-power mode 3 (LPM3); CPU is disabled MCLK and SMCLK are disabled DCO s dc-generator is disabled ACLK remains active Low-power mode 4 (LPM4); CPU is disabled ACLK is disabled MCLK and SMCLK are disabled DCO s dc-generator is disabled Crystal oscillator is stopped

6 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the memory with an address range of FFFFh FFEh. The vector contains the 6-bit address of the appropriate interrupt handler instruction sequence. INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power-up, external reset, watchdog NMI, oscillator fault, flash memory access violation WDTIFG (Note) KEYV (Note ) NMIIFG (Notes and 4) OFIFG (Notes and 4) ACCVIFG (Notes and 4) Reset FFFEh 5, highest (non)-maskable, (non)-maskable, (non)-maskable FFFCh 4 FFFAh 3 FFF8h 2 Comparator_A CAIFG maskable FFF6h Watchdog Timer WDTIFG maskable FFF4h Timer_A TACCR CCIFG (Note 2) maskable FFF2h 9 Timer_A TACCR and TACCR2 CCIFGs, TAIFG maskable FFFh 8 (Notes and 2) FFEEh 7 FFECh 6 FFEAh 5 FFE8h 4 I/O Port P2 (eight flags see Note 3) P2IFG. to P2IFG.7 (Notes and 2) maskable FFE6h 3 I/O Port P (eight flags) PIFG. to PIFG.7 (Notes and 2) maskable FFE4h 2 FFE2h NOTES: FFEh, lowest. Multiple source flags 2. Interrupt flags are located in the module 3. There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2. 5) implemented on the Cx and FxA devices. 4. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot. Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.

7 special function registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. interrupt enable and 2 Address h WDTIE: OFIE: NMIIE: ACCVIE: Address h ACCVIE NMIIE OFIE WDTIE rw- rw- rw- rw- Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in interval timer mode. Oscillator fault enable (Non)maskable interrupt enable Flash access violation interrupt enable interrupt flag register and 2 Address 2h WDTIFG: OFIFG: NMIIFG: Address 3h NMIIFG OFIFG WDTIFG rw- rw- rw- Set on Watchdog Timer overflow (in watchdog mode) or security key violation. Reset on V CC power-up or a reset condition at RST/NMI pin in reset mode. Flag set on oscillator fault Set via RST/NMI-pin Legend rw: rw-: Bit can be read and written. Bit can be read and written. It is reset by PUC. SFR bit is not present in device.

8 memory organization FFFFh FFEh FFDFh F8h MSP43C Int. Vector 2 KB ROM FFFFh FFEh FFDFh Fh MSP43C2 Int. Vector 4 KB ROM FFFFh FFEh FFDFh FCh FFh 8h FFFh Ch MSP43FA Int. Vector KB Flash Segment, 28B Flash SegmentA KB Boot ROM FFFFh FFEh FFDFh F8h FFh h FFFh Ch MSP43FA Int. Vector 2 KB Flash Segment,3 2 28B Flash SegmentA,B KB Boot ROM FFFFh FFEh FFDFh Fh FFh h FFFh Ch MSP43F2A Int. Vector 4 KB Flash Segment B Flash SegmentA,B KB Boot ROM Main Memory Information Memory 27Fh 2h FFh h FFh h Fh h 28B RAM 6b Per. 8b Per. SFR 2FFh 2h FFh h FFh h Fh h 256B RAM 6b Per. 8b Per. SFR 27Fh 2h FFh h FFh h Fh h 28B RAM 6b Per. 8b Per. SFR 27Fh 2h FFh h FFh h Fh h 28B RAM 6b Per. 8b Per. SFR 2FFh 2h FFh h FFh h Fh h 256B RAM 6b Per. 8b Per. SFR bootstrap loader (BSL) The MSP43 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP43 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the Application report Features of the MSP43 Bootstrap Loader, Literature Number SLAA89. BSL Function DW, PW, & DGV Pin RGE Pin Data Transmit 4 - P. 4 - P. Data Receive - P P2.2 flash memory The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: Flash memory has n segments of main memory and two segments of information memory (A and B) of 28 bytes each. Each segment in main memory is 52 bytes in size. Segments to n may be erased in one step, or each segment may be individually erased. Segments A and B can be erased individually, or as a group with segments n. Segments A and B are also called information memory. New devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory prior to the first use.

9 flash memory (continued) FFFFh FEh FDFFh FCh FBFFh FAh F9FFh F8h F7FFh F6h F5FFh F4h F3FFh F2h FFFh Fh FFh 8h 7Fh h Segment w/ Interrupt Vectors Segment Segment2 Segment3 Segment4 Segment5 Segment6 Segment7 SegmentA SegmentB Flash Main Memory Information Memory NOTE: All segments not implemented on all devices.

10 peripherals Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, refer to the MSP43xxx Family User s Guide, literature number SLAU49. oscillator and system clock The clock system is supported by the basic clock module that includes support for a Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The basic clock module provides the following clock signals: Auxiliary clock (ACLK), sourced from a Hz watch crystal or a high frequency crystal. Main clock (MCLK), the system clock used by the CPU. Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. digital I/O There are two 8-bit I/O ports implemented ports P and P2 (only six P2 I/O signals are available on external pins): All individual I/O bits are independently programmable. Any combination of input, output, and interrupt conditions is possible. Edge-selectable interrupt input capability for all the eight bits of port P and six bits of port P2. Read/write access to port-control registers is supported by all instructions. watchdog timer NOTE: Six bits of port P2, P2. to P2.5, are available on external pins but all control and data bits for port P2 are implemented. The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. comparator_a The primary function of the comparator_a module is to support precision slope analog to digital conversions, battery voltage supervision, and monitoring of external analog signals.

11 timer_a3 Timer_A3 is a 6-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Timer_A3 Signal Connections Input Pin Number Device Input Signal Module Input Name Module Output Signal Output Pin Number DW, PW, DGV RGE DW, PW, DGV RGE 3 - P. 3 - P. TACLK TACLK ACLK ACLK SMCLK SMCLK NA 9 - P P2. INCLK INCLK 4 - P. 4 - P. TA CCIA 4 - P. 4 - P. - P P2.2 TA CCIB 8 - P P.5 TA DVss GND DVCC VCC 5 - P P.2 TA CCIA - P2.3 - P2.3 CAOUT (internal) CCIB 5 - P P.2 TA DVss GND 9 - P P.6 DVCC VCC 6 - P P.3 TA2 CCI2A 2 - P2.4 - P2.4 ACLK (internal) CCI2B 6 - P P.3 TA2 DVss GND 2 - P P.7 DVCC VCC

12 peripheral file map PERIPHERALS WITH WORD ACCESS Timer_A Reserved Reserved Reserved Reserved Capture/compare register Capture/compare register Capture/compare register Timer_A register Reserved Reserved Reserved Reserved Capture/compare control Capture/compare control Capture/compare control Timer_A control Timer_A interrupt vector Flash Memory Flash control 3 Flash control 2 Flash control TACCR2 TACCR TACCR TAR TACCTL2 TACCTL TACCTL TACTL TAIV FCTL3 FCTL2 FCTL 7Eh 7Ch 7Ah 78h 76h 74h 72h 7h 6Eh 6Ch 6Ah 68h 66h 64h 62h 6h 2Eh 2Ch 2Ah 28h Watchdog Watchdog/timer control WDTCTL 2h PERIPHERALS WITH BYTE ACCESS Comparator_A Comparator_A port disable Comparator_A control2 Comparator_A control CAPD CACTL2 CACTL 5Bh 5Ah 59h Basic Clock Port P2 Port P Special Function Basic clock system control2 Basic clock system control DCO clock frequency control Port P2 selection Port P2 interrupt enable Port P2 interrupt edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input Port P selection Port P interrupt enable Port P interrupt edge select Port P interrupt flag Port P direction Port P output Port P input SFR interrupt flag2 SFR interrupt flag SFR interrupt enable2 SFR interrupt enable BCSCTL2 BCSCTL DCOCTL P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN PSEL PIE PIES PIFG PDIR POUT PIN IFG2 IFG IE2 IE 58h 57h 56h 2Eh 2Dh 2Ch 2Bh 2Ah 29h 28h 26h 25h 24h 23h 22h 2h 2h 3h 2h h h

13 absolute maximum ratings Voltage applied at V CC to V SS V to 4. V Voltage applied to any pin (see Note) V to V CC +.3 V Diode current at any device terminal ±2 ma Storage temperature, T stg (unprogrammed device) C to 5 C Storage temperature, T stg (programmed device) C to 85 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse. recommended operating conditions Supply voltage during program execution, VCC (see Note ) MIN NOM MAX UNITS MSP43Cx MSP43FxA Supply voltage during program/erase flash memory, VCC MSP43FxA V Supply voltage, VSS V Operating free-air temperature range, TA MSP43xx(A) 4 85 C LFXT crystal frequency, f(lfxt) (see Note 2) Processor frequency f(system) (MCLK signal) LF mode selected, XTS= Watch crystal Hz XT mode selected, XTS= Ceramic resonator 45 8 Crystal 8 VCC =.8 V, MSP43xx(A) VCC = 3.6 V, MSP43xx(A) dc 4.5 dc 8 Flash timing generator frequency, f(ftg) MSP43FxA khz Cumulative program time, block-write, t(cpt) (see Note 3) Mass erase time, t(meras) (See also the flash memory, timing generator, control register FCTL2 section, see Note 4) VCC = 2.7 V/3.6 V MSP43FxA V khz MHz 4 ms VCC = 2.7 V/3.6 V 2 ms Low-level input voltage (TCK, TMS, TDI, RST/NMI), VIL (excluding XIN, XOUT) High-level input voltage (TCK, TMS, TDI, RST/NMI), VIH (excluding XIN, XOUT) VCC = 2.2 V/3 V VSS VSS+.6 V VCC = 2.2 V/3 V.8 VCC VCC V Input levels at XIN, XOUT VIL(XIN, XOUT) VIH(XIN, XOUT) VCC = 2.2 V/3 V VSS.8 VCC.2 VCC NOTES:. The LFXT oscillator in LF mode requires a resistor of 5. MΩ from XOUT to VSS when VCC < 2.5 V. The LFXT oscillator in XT mode accepts a ceramic resonator or a crystal frequency of 4 MHz at VCC 2.2 V. The LFXT oscillator in XT mode accepts a ceramic resonator or a crystal frequency of 8 MHz at VCC 2.8 V. 2. The LFXT oscillator in LF mode requires a watch crystal. The LFXT oscillator in XT mode accepts a ceramic resonator or a crystal. 3. The cumulative program time must not be exceeded during a block-write operation. 4. The mass erase duration generated by the flash timing generator is at least. ms. The cumulative mass erase time needed is 2 ms. This can be achieved by repeating the mass erase operation until the cumulative mass erase time is met (a minimum of 9 cycles may be required). VCC V

14 recommended operating conditions (continued) Maximum Processor Frequency MHz f (system) MSP43Cx and MSP43FxA Devices MHz at.8 V 2 3 VCC Supply Voltage V 8 MHz at 3.6 V NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.7 V. Figure. Frequency vs Supply Voltage 4

15 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) supply current (into V CC ) excluding external current PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Cx TA A = 4 C to + 85 C, VCC = 2.2 V 6 2 f(mclk) = f(smclk) = MHz, f(aclk) = 32,768 Hz VCC = 3 V C 85 C, VCC = 2.2 V.3 2 TA = to + f(mclk) = f(smclk) = f(aclk) = 496 Hz VCC = 3 V I(AM) Active mode TA = 4 C to + 85 C, VCC = 2.2 V 2 25 µa fmclk = f(smclk) = MHz, f(aclk) = 32,768 Hz, Program executes in flash VCC = 3 V 3 35 FxA TA A = 4 C to + 85 C, VCC = 2.2 V 3 5 Program executes in flash f(mclk) = f(smclk) = f(aclk) = 496 Hz V CC = 3 V 8 I(CPUOff) I(LPM2) I(LPM3) I(LPM4) Low-power mode, (LPM) Cx FxA Low-power mode, (LPM2) Low-power mode, (LPM3) Low-power mode, (LPM4) Cx TA A = 4 C to + 85 C, VCC = 2.2 V 3 4 f(mclk) =, f(smclk) = MHz, f(aclk) = 32,768 Hz VCC = 3 V 5 6 TA A = 4 C to + 85 C, VCC = 2.2 V f(mclk) =, f(smclk) = MHz, f(aclk) = 32,768 Hz VCC = 3 V 55 7 TA A = 4 C to + 85 C, VCC = 2.2 V 4 f(mclk) = f(smclk) = MHz, f(aclk) = 32,768 Hz, SCG = VCC = 3 V 7 22 TA A = 4 C to + 85 C, VCC = 2.2 V.2.7 f (MCLK) = f(smclk) = MHz, f(aclk) = 32,768 Hz, SCG = VCC = 3 V TA = 4 C.8.2 TA = 25 C T A = 85 C FxA T A = 4 C TA = 25 C TA = 85 C f(mclk) = MHz, f(smclk) = MHz, f(aclk) = 32,768 Hz, SCG = VCC = 2.2 V VCC = 3 V TA = 4 C..5 Cx TA = 25 C VCC = 2.2 V/3 V..5 TA = 85 C f(mclk) = MHz,.4.8 f(smclk) = MHz, TA = 4 C..5 f(aclk) = Hz, SCG = FxA TA = 25 C VCC = 2.2 V/3 V..5 TA = 85 C NOTE: All inputs are tied to V or VCC. Outputs do not source or sink any current. current consumption of active mode versus system frequency, C version, F version I AM = I AM[ MHz] f system [MHz] current consumption of active mode versus supply voltage, C version I AM = I AM[3 V] + 5 µa/v (V CC 3 V) current consumption of active mode versus supply voltage, F version I AM = I AM[3 V] + 2 µa/v (V CC 3 V).8.9 µa µa µa µa

16 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) Schmitt-trigger inputs Port P and Port P2; P. to P.7, P2. to P2.5 VIT+ VIT Vhys PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Positive-going input threshold voltage Negative-going input threshold voltage Input voltage hysteresis (VIT+ VIT ) outputs Port to P2; P. to P.7, P2. to P2.5 VOH VOH VOL NOTES: VCC = 2.2 V..5 VCC = 3 V.5.9 VCC = 2.2 V.4.9 VCC = 3 V.9.3 VCC = 2.2 V.3. VCC = 3 V.5 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT High-level output voltage Port and Port 2 (Cx) Port (FxA) High-level output voltage Port 2 (FxA) Low-level output voltage Port and Port 2 (Cx, FxA) I(OHmax) =.5 ma I(OHmax) = 6 ma I(OHmax) =.5 ma I(OHmax) = 6 ma I(OHmax) = ma I(OHmax) = 3.4 ma I(OHmax) = ma I(OHmax) = 3.4 ma I(OLmax) =.5 ma I(OLmax) = 6 ma I(OLmax) =.5 ma I(OLmax) = 6 ma VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V See Note VCC.25 VCC See Note 2 VCC.6 VCC See Note VCC.25 VCC See Note 2 VCC.6 VCC See Note 3 VCC.25 VCC See Note 3 VCC.6 VCC See Note 3 VCC.25 VCC See Note 3 VCC.6 VCC See Note VSS VSS+.25 See Note 2 VSS VSS+.6 See Note VSS VSS+.25 See Note 2 VSS VSS+.6. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±2 ma to hold the maximum voltage drop specified. 2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±48 ma to hold the maximum voltage drop specified. 3. One output loaded at a time. V V V V V V

17 outputs Ports P and P2 (continued) I OL Typical Low-Level Output Current ma TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE VCC = 2.2 V P. TA = 25 C TA = 85 C I OL Typical Low-Level Output Current ma TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE VCC = 3 V P. TA = 25 C TA = 85 C VOL Low-Level Output Voltage V VOL Low-Level Output Voltage V Figure 2 Figure 3 I OH Typical High-Level Output Current ma TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE VCC = 2.2 V P. TA = 85 C TA = 25 C VOH High-Level Output Voltage V Figure 4 I OH Typical High-Level Output Current ma TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE VCC = 3 V P. TA = 85 C TA = 25 C VOH High-Level Output Voltage V Figure 5 NOTE: One output loaded at a time.

18 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) leakage current Ilkg(Px.x) NOTES: PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Port P: P.x, 7 VCC = 2.2 V/3 V, ±5 (see Notes, 2) High-impedance leakage current na Port P2: P2.x, 5 VCC = 2.2 V/3 V, ±5 (see Notes, 2). The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. 2. The leakage of the digital port pins is measured individually. The port pin must be selected for input and there must be no optional pullup or pulldown resistor. optional resistors, individually programmable with ROM code (see Note ) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT R(opt) kω R(opt2) kω R(opt3) kω R(opt4) kω R(opt5) Resistors, individually programmable with ROM code, all port pins, kω R(opt6) values applicable for pulldown and pullup VCC = 2.2 V/3 V kω R(opt7) kω R(opt8) kω R(opt9) kω R(opt) kω NOTE : Optional resistors Roptx for pulldown or pullup are not available in standard flash memory device MSP43FxA. inputs Px.x, TAx t(int) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT External interrupt timing Port P, P2: P.x to P2.x, External trigger signal for the interrupt flag, (see Note ) 2.2 V/3 V.5 cycle 2.2 V 62 3 V 5 t(cap) Timer_A, capture timing TA, TA, TA2 (see Note 2) 2.2 V 62 f(taext) Timer_A clock frequency externally applied to pin TACLK, INCLK t(h) = t(l) f(taint) Timer_A clock frequency SMCLK or ACLK signal selected NOTES: ns 2.2 V/3 V.5 cycle 3 V V 8 3 V 2.2 V 8 3 V. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in MCLK cycles. 2. The external capture signal triggers the capture event every time the mimimum t(cap) cycle and time parameters are met. A capture may be triggered with capture signals even shorter than t(cap). Both the cycle and timing specifications must be met to ensure a correct capture of the 6-bit timer value and to ensure the flag is set. ns MHz MHz

19 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) outputs P.x, P2.x, TAx PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT f(p2) P2./ACLK, CL = 2 pf 2.2 V/3 V fsystem f(tax) t(xdc) Output frequency TA, TA, TA2, CL = 2 pf Internal clock source, SMCLK signal applied (see Note ) Duty cycle of O/P frequency P.4/SMCLK, CL = 2 pf 2.2 V/3 V dc fsystem fsmclk = flfxt = fxt 4% 6% fsmclk = flfxt = flf fsmclk = flfxt/n fsmclk = fdcoclk 2.2 V/3 V 5% 5 ns 35% 65% 2.2 V/3 V 5% 5%+ 5% 5 ns 5 ns fp2 = flfxt = fxt 4% 6% P2./ACLK, fp2 = flfxt = flf 2.2 V/3 V 3% 7% CL = 2 pf fp2 = flfxt/n 5% t(tadc) TA, TA, TA2, CL = 2 pf, duty cycle = 5% 2.2 V/3 V ±5 ns NOTE : The limits of the system clock MCLK has to be met. MCLK and SMCLK can have different frequencies. Comparator_A (see Note ) I(DD) I(Refladder/ RefDiode) V(IC) V(Ref25) V(Ref5) 5% 5%+ 5 ns PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Common-mode input voltage V node CC V CC node CC V CC CAON=, CARSEL=, CAREF= VCC = 2.2 V 25 4 VCC = 3 V 45 6 CAON=, CARSEL=, VCC = 2.2 V 3 5 CAREF=/2/3, no load at P2.3/CA/TA and P2.4/CA/TA2 VCC = 3 V 45 7 CAON = VCC = 2.2 V/3 V VCC V PCA=, CARSEL=, CAREF=, No load at P2.3/CA/TA and P2.4/CA/TA2 PCA=, CARSEL=, CAREF=2, No load at P2.3/CA/TA and P2.4/CA/TA2 VCC = 2.2 V/3 V VCC = 2.2 V/3 V PCA=, CARSEL=, CAREF=3, VCC = 2.2 V V(RefVT) See Figure 6 and Figure 7 No load at P2.3/CA/TA and P2.4/CA/TA2, TA = 85 C VCC = 3 V V(offset) Offset voltage See Note 2 VCC = 2.2 V/3 V 3 3 mv Vhys Input hysteresis CAON= VCC = 2.2 V/3 V.7.4 mv t(response LH) t(response HL) NOTES: TA = 25 C, Overdrive mv, without VCC = 2.2 V filter: CAF= VCC = 3 V TA = 25 C, Overdrive mv, with VCC = 2.2 V filter: CAF= VCC = 3 V TA = 25 C, Overdrive mv, without VCC = 2.2 V filter: CAF= VCC = 3 V TA = 25 C, Overdrive mv, with VCC = 2.2 V filter: CAF= VCC = 3 V The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification. 2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The two successive measurements are then summed together. MHz µa µa mv ns µs ns µs

20 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) VCC = 3 V VCC = 2.2 V V (REFVT) Reference Volts mv Typical V (REFVT) Reference Volts mv Typical TA Free-Air Temperature C Figure 6. V (RefVT) vs Temperature, V CC = 3 V TA Free-Air Temperature C Figure 7. V (RefVT) vs Temperature, V CC = 2.2 V V VCC CAON CAF Low Pass Filter To Internal Modules V+ V + _ CAOUT Set CAIFG Flag τ 2. µs Figure 8. Block Diagram of Comparator_A Module V Overdrive VCAOUT 4 mv V+ t(response) Figure 9. Overdrive Definition

21 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) PUC/POR PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t(por_delay) 5 25 µs TA = 4 C.4.8 V VPOR POR TA = 25 C..5 V VCC = 2.2 V/3 V TA = 85 C.8.2 V V(min).4 V t(reset) PUC/POR Reset is accepted internally 2 µs V VCC V POR V (min) POR No POR POR t Figure. Power-On Reset (POR) vs Supply Voltage V POR [V] Max Min C Temperature [ C] Figure. V POR vs Temperature

22 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) crystal oscillator,lfxt CXIN CXOUT NOTE : RAM PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input capacitance Output capacitance XTS=; LF mode selected. VCC = 2.2 V / 3 V XTS=; XT mode selected. VCC = 2.2 V / 3 V (Note ) XTS=; LF mode selected. VCC = 2.2 V / 3 V XTS=; XT mode selected. VCC = 2.2 V / 3 V (Note ) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. PARAMETER MIN NOM MAX UNIT V(RAMh) CPU halted (see Note ).6 V NOTE : This parameter defines the minimum supply voltage VCC when the data in the program memory RAM remains unchanged. No program execution should happen during this supply voltage condition pf pf

23 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) DCO PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f(dco3) Rsel =, DCO = 3, MOD =, DCOR =, TA = 25 C f(dco3) Rsel =, DCO = 3, MOD =, DCOR =, TA = 25 C f(dco23) Rsel = 2, DCO = 3, MOD =, DCOR =, TA = 25 C f(dco33) Rsel = 3, DCO = 3, MOD =, DCOR =, TA = 25 C f(dco43) Rsel = 4, DCO = 3, MOD =, DCOR =, TA = 25 C f(dco53) Rsel = 5, DCO = 3, MOD =, DCOR =, TA = 25 C f(dco63) Rsel = 6, DCO = 3, MOD =, DCOR =, TA = 25 C f(dco73) Rsel = 7, DCO = 3, MOD =, DCOR =, TA = 25 C f(dco77) Rsel = 7, DCO = 7, MOD =, DCOR =, TA = 25 C f(dco47) Rsel = 4, DCO = 7, MOD =, DCOR =, TA = 25 C VCC = 2.2 V/3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V.2.5 VCC = 3 V.3.5 VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V MHz MHz MHz MHz MHz MHz MHz MHz MHz FDCO4 FDCO4 FDCO4 MHz x.7 x2. x2.5 S(Rsel) SR = frsel+/frsel VCC = 2.2 V/3 V S(DCO) SDCO = fdco+/fdco VCC = 2.2 V/3 V Dt DV NOTE : Temperature drift, Rsel = 4, DCO = 3, MOD = VCC = 2.2 V (see Note ) VCC = 3 V Drift with VCC variation, Rsel = 4, DCO = 3, MOD = (see Note ) These parameters are not production tested. ratio %/ C VCC = 2.2 V/3 V 5 %/V Frequency Variance Max f(dcox7) Min Max f(dcox) Min ÎÎÎÎÎ ÎÎÎÎÎ fdcoclk 2.2 V 3 V VCC DCO Steps Figure 2. DCO Characteristics

24 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) principle characteristics of the DCO Individual devices have a minimum and maximum operation frequency. The specified parameters for f DCOx to f DCOx7 are valid for all devices. DCO control bits DCO, DCO, and DCO2 have a step size as defined in parameter S DCO. Modulation control bits MOD to MOD4 select how often f DCO+ is used within the period of 32 DCOCLK cycles. f DCO is used for the remaining cycles. The frequency is an average = f DCO (2 MOD/32 ). All ranges selected by Rsel(n) overlap with Rsel(N+): Rsel overlaps with Rsel,... Rsel6 overlaps with Rsel7. wake-up from lower power modes (LPMx) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t(lpm) VCC = 2.2 V/3 V t(lpm2) VCC = 2.2 V/3 V ns t(lpm3) Delay time (see Note ) f(mclk) = MHz, VCC = 2.2 V/3 V 6 f(mclk) = 2 MHz, VCC = 2.2 V/3 V 6 µss f(mclk) = 3 MHz, VCC = 2.2 V/3 V 6 f(mclk) = MHz, VCC = 2.2 V/3 V 6 t(lpm4) f(mclk) = 2 MHz, VCC = 2.2 V/3 V 6 µss f(mclk) = 3 MHz, VCC = 2.2 V/3 V 6 NOTE : Parameter applicable only if DCOCLK is used for MCLK. JTAG, program memory and fuse f(tck) TCK frequency, JTAG/test (see Note 3) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCC = 2.2 V dc 5 VCC = 3 V dc VCC(FB) Supply voltage during fuse blow condition TA = 25 C 2.5 V V(FB) Fuse blow voltage, C versions (see Notes and 2) V Fuse blow voltage, F versions (see Notes and 2) V I(FB) Supply current on TEST during fuse blow (see Note 2) ma t(fb) Time to blow the fuse (see Note 2) ms I(DD-PGM) Current during program cycle (see Note 4) VCC = 2.7 V/3.6 V, MSP43FxA MHz 3 5 ma I(DD-ERASE) Current during erase cycle (see Note 4) VCC = 2.7 V/3.6 V, 3 5 ma MSP43FxA Erase cycles MSP43FxA 4 5 t(retention) Data retention TJ = 25 C MSP43FxA Year NOTES:. The power source to blow the fuse is applied to the TEST pin. 2. Once the JTAG fuse is blown, no further access to the MSP43 JTAG/test feature is possible. The JTAG block is switched to bypass mode. 3. f(tck) may be restricted to meet the timing requirements of the module selected. 4. Duration of the program/erase cycle is determined by f(ftg) applied to the flash timing controller. It can be calculated as follows: t(word write) = 35 x /f(ftg) t(block write, byte ) = 3 /f(ftg) t(block write, byte 63) = 22 /f(ftg) t(block write end sequence) = 6 /f(ftg) t(mass erase) = 5297 x /f(ftg) t(segment erase) = 489 x /f(ftg)

25 APPLICATION INFORMATION input/output schematic Port P, P. to P.3, input/output with Schmitt-trigger PSEL.x PDIR.x Direction Control From Module POUT.x Module X OUT Pad Logic VCC (See Note ) (See Note 2) (See Note 2) P. P.3 PIN.x Module X IN EN D GND (See Note ) PIRQ.x PIE.x PIFG.x Q EN Set Interrupt Edge Select NOTE: x = Bit/identifier, to 3 for port P Interrupt Flag PIES.x PSEL.x PnSel.x PnDIR.x Direction control from PnOUT.x Module X OUT PnIN.x Module X IN PnIE.x PnIFG.x PnIES.x module PSel. PDIR. PDIR. POUT. VSS PIN. TACLK PIE. PIFG. PIES. PSel. PDIR. PDIR. POUT. Out signal PIN. CCIA PIE. PIFG. PIES. PSel.2 PDIR.2 PDIR.2 POUT.2 Out signal PIN.2 CCIA PIE.2 PIFG.2 PIES.2 PSel.3 PDIR.3 PDIR.3 POUT.3 Out2 signal PIN.3 CCI2A PIE.3 PIFG.3 PIES.3 Signal from or to Timer_A NOTES:. Optional selection of pullup or pulldown resistors with ROM (masked) versions 2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).

26 APPLICATION INFORMATION Port P, P.4 to P.7, input/output with Schmitt-trigger and in-system access features PSEL.x PDIR.x Direction Control From Module POUT.x Module X OUT Pad Logic VCC See Note See Note 2 See Note 2 P.4 P.7 See Note PIN.x TST GND Bus Keeper EN Module X IN D PIRQ.x PIE.x PIFG.x Q EN Set Interrupt Flag Interrupt Edge Select PIES.x PSEL.x Control By JTAG TST Fuse Fuse Blow TSTControl GND 6 kω Typical TEST P.x TDO Controlled By JTAG P.7/TDI/TDO Controlled by JTAG TDI TST P.x P.6/TDI NOTE: The test pin should be protected from potential EMI and ESD voltage spikes. This may require a smaller external pulldown resistor in some applications. TMS TST P.x x = Bit identifier, 4 to 7 for port P During programming activity and during blowing of the fuse, the pin TDO/TDI is used to apply the test input for JTAG circuitry. TCK TST P.5/TMS P.x P.4/TCK PnSel.x PnDIR.x Direction control from PnOUT.x Module X OUT PnIN.x Module X IN PnIE.x PnIFG.x PnIES.x module PSel.4 PDIR.4 PDIR.4 POUT.4 SMCLK PIN.4 unused PIE.4 PIFG.4 PIES.4 PSel.5 PDIR.5 PDIR.5 POUT.5 Out signal PIN.5 unused PIE.5 PIFG.5 PIES.5 PSel.6 PDIR.6 PDIR.6 POUT.6 Out signal PIN.6 unused PIE.6 PIFG.6 PIES.6 PSel.7 PDIR.7 PDIR.7 POUT.7 Out2 signal PIN.7 unused PIE.7 PIFG.7 PIES.7 Signal from or to Timer_A NOTES:. Optional selection of pullup or pulldown resistors with ROM (masked) versions 2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).

27 APPLICATION INFORMATION Port P2, P2. to P2.2, input/output with Schmitt-trigger P2SEL.x P2DIR.x Direction Control From Module P2OUT.x Module X OUT : Input : Output Pad Logic VCC See Note See Note 2 See Note 2 P2. P2.2 See Note GND Bus Keeper P2IN.x Module X IN EN D CAPD.X P2IRQ.x P2IE.x P2IFG.x Q EN Set Interrupt Edge Select NOTE: x = Bit Identifier, to 2 for port P2 Interrupt Flag P2IES.x P2SEL.x PnSel.x PnDIR.x Direction control from PnOUT.x Module X OUT PnIN.x Module X IN PnIE.x PnIFG.x PnIES.x module P2Sel. P2DIR. P2DIR. P2OUT. ACLK P2IN. unused P2IE. P2IFG. PIES. P2Sel. P2DIR. P2DIR. P2OUT. VSS P2IN. INCLK P2IE. P2IFG. PIES. P2Sel.2 P2DIR.2 P2DIR.2 P2OUT.2 CAOUT P2IN.2 CCIB P2IE.2 P2IFG.2 PIES.2 Signal from or to Timer_A NOTES:. Optional selection of pullup or pulldown resistors with ROM (masked) versions 2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).

28 APPLICATION INFORMATION Port P2, P2.3 to P2.4, input/output with Schmitt-trigger P2SEL.3 P2DIR.3 Direction Control From Module P2OUT.3 Module X OUT : Input : Output Pad Logic VCC See Note See Note 2 See Note 2 P2.3 See Note P2IN.3 EN Bus Keeper GND Module X IN D P2IRQ.3 P2IE.3 P2IFG.3 Q EN Set Interrupt Edge Select Interrupt Flag P2IES.3 P2SEL.3 CAPD.3 Comparator_A CAREF CAF P2CA CAEX CCIB + _ V Interrupt Flag P2IES.4 P2SEL.4 CAREF Reference Block P2IRQ.4 P2IFG.4 P2IE.4 Q Set EN Interrupt Edge Select CAPD.4 Module X IN D P2IN.4 EN Bus Keeper VCC See Note See Note 2 Module X OUT P2OUT.4 Direction Control From Module P2DIR.4 P2SEL.4 Pad Logic : Output : Input See Note 2 See Note GND P2.4 PnSel.x PnDIR.x Direction PnOUT.x Module X OUT PnIN.x Module X IN PnIE.x PnIFG.x PnIES.x control from module P2Sel.3 P2DIR.3 P2DIR.3 P2OUT.3 Out signal P2IN.3 unused P2IE.3 P2IFG.3 PIES.3 P2Sel.4 P2DIR.4 P2DIR.4 P2OUT.4 Out2 signal P2IN.4 unused P2IE.4 P2IFG.4 PIES.4 Signal from Timer_A NOTES:. Optional selection of pullup or pulldown resistors with ROM (masked) versions 2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).

29 APPLICATION INFORMATION Port P2, P2.5, input/output with Schmitt-trigger and R OSC function for the Basic Clock module P2SEL.5 P2DIR.5 Direction Control From Module P2OUT.5 Module X OUT : Input : Output Pad Logic VCC See Note See Note 2 See Note 2 P2.5 See Note GND P2IN.5 Bus Keeper EN Module X IN P2IRQ.5 D P2IE.5 P2IFG.5 Q EN Set Interrupt Edge Select VCC Internal to Basic Clock Module Interrupt Flag P2IES.5 DCOR P2SEL.5 CAPD.5 DC Generator NOTE: DCOR: Control bit from Basic Clock Module if it is set, P2.5 Is disconnected from P2.5 pad PnSel.x PnDIR.x Direction control from PnOUT.x Module X OUT PnIN.x Module X IN PnIE.x PnIFG.x PnIES.x module P2Sel.5 P2DIR.5 P2DIR.5 P2OUT.5 VSS P2IN.5 unused P2IE.5 P2IFG.5 P2IES.5 NOTES:. Optional selection of pullup or pulldown resistors with ROM (masked) versions 2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).

30 Port P2, unbonded bits P2.6 and P2.7 APPLICATION INFORMATION P2SEL.x P2DIR.x Direction Control From Module P2OUT.x Module X OUT : Input : Output P2IN.x Module X IN EN D Node Is Reset With PUC Bus Keeper P2IRQ.x P2IE.x P2IFG.x Q EN Set Interrupt Edge Select PUC Interrupt Flag NOTE: x = Bit/identifier, 6 to 7 for port P2 without external pins P2IES.x P2SEL.x P2Sel.x P2DIR.x Direction control from P2OUT.x Module X OUT P2IN.x Module X IN P2IE.x P2IFG.x P2IES.x module P2Sel.6 P2DIR.6 P2DIR.6 P2OUT.6 VSS P2IN.6 unused P2IE.6 P2IFG.6 P2IES.6 P2Sel.7 P2DIR.7 P2DIR.7 P2OUT.7 VSS P2IN.7 unused P2IE.7 P2IFG.7 P2IES.7 NOTE : Unbonded bits 6 and 7 of port P2 can be used as software interrupt flags. The interrupt flags can only be influenced by software. They work then as a software interrupt.

31 JTAG fuse check mode MSP43 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, I TF, of ma at 3 V, 2.5 ma at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. When the TEST pin is taken back low after a test or programming session, the fuse check mode and sense currents are terminated. Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated. The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see Figure 3). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). Time TMS Goes Low After POR TMS ITF ITEST Figure 3. Fuse Check Mode Current, MSP43FxA The JTAG pins are terminated internally, and therefore do not require external termination. NOTE: The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit bootloader access key is used. Also, see the bootstrap loader section for more information.

32 DW (R-PDSO-G**) 6 PIN SHOWN MECHANICAL DATA PLASTIC SMALL-OUTLINE PACKAGE.5 (,27).2 (,5).4 (,35). (,25) M (,65).4 (,5).299 (7,59).293 (7,45). (,25) NOM Gage Plane A 8 8. (,25).5 (,27).6 (,4).4 (2,65) MAX.2 (,3).4 (,) Seating Plane.4 (,) DIM PINS ** A MAX.4 (,4).5 (2,95).6 (5,49) A MIN.4 (,6).5 (2,7).6 (5,24) 44/ D 2/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed.6 (,5). D. Falls within JEDEC MS-3

33 PW (R-PDSO-G**) 4 PINS SHOWN MECHANICAL DATA PLASTIC SMALL-OUTLINE PACKAGE,3,65, M, ,5 4,3 6,6 6,2,5 NOM Gage Plane A 7 8,25,75,5,2 MAX,5,5 Seating Plane, DIM PINS ** A MAX 3, 5, 5, 6,6 7,9 9,8 A MIN 2,9 4,9 4,9 6,4 7,7 9,6 4464/F /97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed,5. D. Falls within JEDEC MO-53

34 DGV (R-PDSO-G**) 24 PINS SHOWN MECHANICAL DATA PLASTIC SMALL-OUTLINE,4,23,3,7 M 24 3,6 NOM 4,5 4,3 6,6 6,2 Gage Plane 2 A 8,25,75,5,2 MAX,5,5 Seating Plane,8 DIM PINS ** A MAX 3,7 3,7 5, 5, 7,9 9,8,4 A MIN 3,5 3,5 4,9 4,9 7,7 9,6, /E 8/ NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed,5 per side. D. Falls within JEDEC: 24/48 Pins MO-53 4/6/2/56 Pins MO-94

35 RGE (S-PQFP-N24) MECHANICAL DATA 4,5 3,85 PLASTIC QUAD FLATPACK 4,5 3,85 Pin Index Area Top and Bottom,,8,2 REF.,8,5, Seating Plane 24X,5,3 2,55 MAX SQ. 6, Exposed Thermal Die Pad (See Note D) 2,5 8 3,3 24X,8, 4244/B /2 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Quad Flatpack, No-leads, (QFN) package configuration. D. The package thermal performance may be enhanced by bonding the thermal die pad to an external thermal plane. E. Falls within JEDEC M-22.

36 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio Data Converters dataconverter.ti.com Automotive DSP dsp.ti.com Broadband Interface interface.ti.com Digital Control Logic logic.ti.com Military Power Mgmt power.ti.com Optical Networking Microcontrollers microcontroller.ti.com Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box Dallas, Texas Copyright 23, Texas Instruments Incorporated