B 6 A A N A S A +V B B B +V 2

B 6 A A N A S A +V B B B +V 2

V A A B B 3

C Vcc FT7 B B 1 C 1 V cc C 2 B 2 G G B 3 C 3V cc C B ND ND GND

V A A B B C 1 C 3 C 2 C V cc V cc V 220Ωx B 1 B 2 B 3 B GND GND

A B A B 1 1 0 0 0 2 0 1 0 0 3 0 0 1 0 0 0 0 1 6

7 /A EPM706S/LCC 6 8 3 I/GCLK1 STEP3 0 /B STEP0 STEP1 FT7 9 6 7 8 12 3 1 2 11 10 C3 B2 GND GND B3 B V+ B1 C1 C2 C V+ A CLOCK STEP2 MOTOR STEPPER 1 2 3 6 VCC B

11 entity stepmotor_fulla is 12 port( 13 clk : in std_logic; 1 step: out std_logic_vector(3 downto 0) 1 ); 16 end stepmotor_fulla; 17 18 architecture arch of stepmotor_fulla is 19 signal cnt : std_logic_vector(1 downto 0); 20 begin 21 22 ---------- process --------- 23 process(clk) 2 begin 2 if clk'event and clk='1' then 26 cnt <= cnt+1; 27 end if; 28 end process; 29 step <= "1000" when cnt=0 else 30 "0100" when cnt=1 else 31 "0010" when cnt=2 else 32 "0001"; 33 end arch; 8

13 entity clk_div_step is 1 generic(divisor:integer:=00000); 1 port( 16 clk_in : in std_logic; 17 clk_out: out std_logic 18 ); 19 end clk_div_step; 20 21 architecture arch of clk_div_step is 22 signal cnt2 : std_logic; 23 begin 2 ---------- clk divider ---------- 2 process(clk_in) 26 variable cnt1,divisor2 : integer range 0 to divisor; 27 begin 28 divisor2:=divisor/2; 29 ----- up counter ----- 30 if (clk_in'event and clk_in='1') then 31 if cnt1 = divisor then 32 cnt1 := 1; 33 else 3 cnt1 := cnt1 + 1; 3 end if; 36 end if; 37 ----- clk_out register clk generator ----- 38 if (clk_in'event and clk_in='1') then 39 if (( cnt1 = divisor2) or (cnt1 = divisor))then 0 cnt2 <= not cnt2 ; 1 end if; 2 end if; 3 clk_out <= cnt2 ; end process; end arch; 6 9

PIN_3 clock INPUT VCC clk_div _step Param eter Value divisor 3686 stepmotor_f ulla inst clk_in clk_out clk inst1 step[3..0] OUTPUT step[3..0] PIN_8 PIN_6 PIN_ PIN_ 10

A B A B 1 1 1 0 0 2 0 1 1 0 3 0 0 1 1 1 0 0 1 A 11

clock 28 Step(3) Step(2) Step(1) 2 Step(0) 22 12

13 /A EPM706S/LCC 6 8 3 I/GCLK1 STEP3 0 /B STEP0 STEP1 FT7 9 6 7 8 12 3 1 2 11 10 C3 B2 GND GND B3 B V+ B1 C1 C2 C V+ A CLOCK STEP2 MOTOR STEPPER 1 2 3 6 VCC B

12 entity stepmotor_fullb is 13 port( 1 clk : in std_logic; 1 step: out std_logic_vector(3 downto 0) 16 ); 17 end stepmotor_fullb; 18 19 architecture arch of stepmotor_fullb is 20 signal cnt : std_logic_vector (1 downto 0); 21 begin 22 23 ---------- process --------- 2 process(clk) 2 begin 26 if clk'event and clk='1' then 27 cnt <= cnt+1; 28 end if; 29 end process; 30 31 step <= "1100" when cnt=0 else 32 "0110" when cnt=1 else 33 "0011" when cnt=2 else 3 "1001"; 3 end arch; 1

13 entity clk_div_step is 1 generic(divisor:integer:= 00000); 1 port( 16 clk_in : in std_logic; 17 clk_out: out std_logic 18 ); 19 end clk_div_step; 20 21 architecture arch of clk_div_step is 22 signal cnt2 : std_logic; 23 begin 2 ---------- clk divider ---------- 2 process(clk_in) 26 variable cnt1,divisor2 : integer range 0 to divisor; 27 begin 28 divisor2:=divisor/2; 29 ----- up counter ----- 30 if (clk_in'event and clk_in='1') then 31 if cnt1 = divisor then 32 cnt1 := 1; 33 else 3 cnt1 := cnt1 + 1; 3 end if; 36 end if; 37 ----- clk_out register clk generator ----- 38 if (clk_in'event and clk_in='1') then 39 if (( cnt1 = divisor2) or (cnt1 = divisor))then 0 cnt2 <= not cnt2 ; 1 end if; 2 end if; 3 clk_out <= cnt2 ; end process; end arch; 6 1

PIN_3 clock INPUT VCC clk_div _step Param eter Value divisor 3686 stepmotor_f ullb inst clk_in clk_out clk inst1 step[3..0] OUTPUT step[3..0] PIN_8 PIN_6 PIN_ PIN_ 16

clock 28 Step(3) Step(2) Step(1) 2 Step(0) 22 17

A B A B 1 1 0 0 0 2 1 1 0 0 3 0 1 0 0 0 1 1 0 0 0 1 0 6 0 0 1 1 7 0 0 0 1 8 1 0 0 1 18

19 /A EPM706S/LCC 6 8 3 I/GCLK1 STEP3 0 /B STEP0 STEP1 FT7 9 6 7 8 12 3 1 2 11 10 C3 B2 GND GND B3 B V+ B1 C1 C2 C V+ A CLOCK STEP2 MOTOR STEPPER 1 2 3 6 VCC B

12 entity stepmotor_half is 13 port( 1 clk : in std_logic; 1 step: out std_logic_vector(3 downto 0) 16 ); 17 end stepmotor_half; 18 19 architecture arch of stepmotor_half is 20 signal cnt : std_logic_vector(2 downto 0); 21 begin 22 23 ---------- process --------- 2 process(clk) 2 begin 26 if clk'event and clk='1' then 27 cnt <= cnt+1; 28 end if; 29 end process; 30 31 step <= "1000" when cnt=0 else 32 "1100" when cnt=1 else 33 "0100" when cnt=2 else 3 "0110" when cnt=3 else 3 "0010" when cnt= else 36 "0011" when cnt= else 37 "0001" when cnt=6 else 38 "1001"; 39 end arch; 20

13 entity clk_div_step is 1 generic(divisor:integer:= 00000); 1 port( 16 clk_in : in std_logic; 17 clk_out: out std_logic 18 ); 19 end clk_div_step; 20 21 architecture arch of clk_div_step is 22 signal cnt2 : std_logic; 23 begin 2 ---------- clk divider ---------- 2 process(clk_in) 26 variable cnt1,divisor2 : integer range 0 to divisor; 27 begin 28 divisor2:=divisor/2; 29 ----- up counter ----- 30 if (clk_in'event and clk_in='1') then 31 if cnt1 = divisor then 32 cnt1 := 1; 33 else 3 cnt1 := cnt1 + 1; 3 end if; 36 end if; 37 ----- clk_out register clk generator ----- 38 if (clk_in'event and clk_in='1') then 39 if (( cnt1 = divisor2) or (cnt1 = divisor))then 0 cnt2 <= not cnt2 ; 1 end if; 2 end if; 3 clk_out <= cnt2 ; end process; end arch; 6 21

PIN_3 clock INPUT VCC Par am e t e r V alu e div is or 3686 clk_div _step inst clk_in clk_out clk inst1 OUTPUT step[3..0] PIN_8 PIN_6 PIN_ PIN_ 22

clk 28 Step(3) 8 Step(2) Step(1) 2 Step(0) 22 23

if clk'event and clk='1' then if dir='1' then cnt <= cnt+1; else cnt <= cnt-1; end if; end if; 2

2 EPM706S/LCC 6 8 3 37 I/GCLK1 FT7 9 6 7 8 12 3 1 2 11 10 C3 B2 GND GND B3 B V+ B1 C1 C2 C V+ DIR B STEP1 STEP3 MOTOR STEPPER 1 2 3 6 STEP0 A /B STEP2 0 CLOCK VCC /A SW1 VCC

11 entity stepmotor_dir is 12 port( 13 clk : in std_logic; 1 dir : in std_logic; 1 step: out std_logic_vector(3 downto 0) 16 ); 17 end stepmotor_dir; 18 19 architecture arch of stepmotor_dir is 20signal cnt : std_logic_vector(1 downto 0); 21 begin 22 23 ---------- process --------- 2 process(clk) 2 begin 26 if clk'event and clk='1' then 27 if dir='1' then 28 cnt <= cnt+1; 29 else 30 cnt <= cnt-1; 31 end if; 32 end if; 33 end process; 3 3 step <= "1000" when cnt=0 else 36 "0100" when cnt=1 else 37 "0010" when cnt=2 else 38 "0001"; 39 end arch; 26

13 entity clk_div_step is 1 generic(divisor:integer:= 00000); 1 port( 16 clk_in : in std_logic; 17 clk_out: out std_logic 18 ); 19 end clk_div_step; 20 21 architecture arch of clk_div_step is 22 signal cnt2 : std_logic; 23 begin 2 ---------- clk divider ---------- 2 process(clk_in) 26 variable cnt1,divisor2 : integer range 0 to divisor; 27 begin 28 divisor2:=divisor/2; 29 ----- up counter ----- 30 if (clk_in'event and clk_in='1') then 31 if cnt1 = divisor then 32 cnt1 := 1; 33 else 3 cnt1 := cnt1 + 1; 3 end if; 36 end if; 37 ----- clk_out register clk generator ----- 38 if (clk_in'event and clk_in='1') then 39 if (( cnt1 = divisor2) or (cnt1 = divisor))then 0 cnt2 <= not cnt2 ; 1 end if; 2 end if; 3 clk_out <= cnt2 ; end process; end arch; 6 27

PIN_3 clock INPUT VCC Param eter Value divisor 3686 clk_div _step stepmotor_dir PIN_37 dir clk_in inst INPUT VCC clk_out clk dir inst1 step[3..0] OUTPUT step[3..0] PIN_8 PIN_6 PIN_ PIN_ 28

clock 28 Step(3) dir 222 Step(2) Step(1) 2 Step(0) 22 29