Microsoft PowerPoint - 2 DevCon_pciexpress_board_guidelines ppt

Bus Topology Evolution PCI common clock Meet setup/hold timing Multi-drop parallel I/O AGP source synchronous Single strobe, multiple data Match all data to strobes PCI Express* serial differential CONN Embedded clock Point-to-point, match per data pair only Longer route, creative device placement CONN CONN 133MT/s CONN MCH CLK 533MT/s MCH 2.5+GT/s MCH PCI Express* pt-to-pt routing is is straightforward Copyright 2004, PCI-SIG, All Rights Reserved 3

800 mv Serial Differential RX TX TX Spec Eye System board Transmitter (TX) & package AC caps D+ D- PCI Express* Connector Interconnect Loss < 13.2 db Jitter < 0.3 UI Add-in card = + TX RX Receiver (RX) & package RX Spec 175 mv Diff. pairs AC coupled Lane-to-lane de-skew Polarity inversion On-chip equalization On-chip terminations 0.7 UI 0.4 UI UI = Unit Interval as defined in PCI Express* Base Spec Copyright 2004, PCI-SIG, All Rights Reserved 4

PCI Express* Routing Trace length matching between pairs is not required Embedded clock & lane-to-lane de-skew simplifies routing rules Longer system board traces possible TX usually route on top layer AC coupling caps on TX traces x16 Connector Add-in card AC Coupling Caps System board Copyright 2004, PCI-SIG, All Rights Reserved 5

CEM* Interconnect Budget CEM* (Card ElectroMechanical) Spec defines budget allocation Loss and jitter are key parameters Target impedance not as critical Maintain differential pair symmetry Design tradeoffs: loss vs. trace length, etc. TX System board AC caps Recommended < 12-inch trace length PCI Express* Connector Board CEM Spec Eye Card CEM Spec Eye Add-in card TX Recommended < 3.5-inch Manage loss and jitter to meet budget Copyright 2004, PCI-SIG, All Rights Reserved 6

Stackup Design No new PCB technology required Standard 4-layer stackup 0.062-inch thick PCB Microstrip ½ oz Cu plated or, Stripline 1 oz Cu (6+ layers) T = ~62 mils T Follow simple layout rules & design tradeoffs Copyright 2004, PCI-SIG, All Rights Reserved 8

Wide pair-to-pair spacing minimize crosstalk Close intra-pair spacing Same geometry for interleaved/non-interleaved Example impedance targets: Single-end Zo of 60 Ω ±15% Differential Impedance of ~100 Ω ±20% Trace Geometry & Impedance Tx w Tx Tx Non-interleaved topology example Rx w Tx Rx Interleaved topology example Tx 5 7 5 20 mil h Microstrip Tx 5 5 5 h 20 mil Stripline Tx Tx Copyright 2004, PCI-SIG, All Rights Reserved 9

FR4 Loss Considerations Loss with Stackup: FR4 material Narrow traces Copper roughness Dielectrics with more resin material Non-homogeneous dielectrics Localized Zo variation due to material weave Wide differential impedance variation on µstrip traces Etching and plating process Resin Material Glass Material FR4 cross-section Copyright 2004, PCI-SIG, All Rights Reserved 10

Trace Length Longer trace length loss ~0.25 to 0.35 db inherent loss per inch for FR4 microstrip traces at 1.25GHz Manage trace lengths to minimize loss Example: 12-inch board, 3.5-inch card lengths max 1.25GHz freq -5.23dB 20-inch line db Example VNA measurements for differential µstrip trace insertion loss Copyright 2004, PCI-SIG, All Rights Reserved 11

Trace Symmetry & Matching No matching needed pair-to-pair Match within each differential pair per segment Match overall length 5 mils (recommended) Symmetric routing for each pair Preferred matching Match near mismatch 45 mils Alternative matching Copyright 2004, PCI-SIG, All Rights Reserved 12

Bends and Small Serpentines Avoid tight bends No 90 bends; impact to loss and jitter budgets Keep angles >= 135 (α) Maintain adequate air gap A >= 4x the trace width Lengths of B, C >= 1.5x the width of the trace C B α >3w A Serpentines length is at least 3w for jog w S S1 < 2 S Copyright 2004, PCI-SIG, All Rights Reserved 13

Package Pin Field Breakout Use side-by-side breakout for package to maintain symmetry Avoid tight bends Side-by-side Best Adjacent w/ small serpentine OK Adjacent w/ bend Fair Diagonal routing Fair Copyright 2004, PCI-SIG, All Rights Reserved 14

Reference Plane Full GND plane reference recommended Stitching vias required for layer transition Keep clearance from plane voids Avoid plane splits Avoid trace over anti-pad Plane Void Long trace routes Gnd stitching via Copyright 2004, PCI-SIG, All Rights Reserved 15

AC Coupling Capacitors Size: 0402 best, 0603 ok No 0805 size or C-packs Symmetric placement best Cap size: 0.1uF best Same sizes for both D+/D- Cap location: Along Tx pairs on system board Along Tx pairs on add-in card Copyright 2004, PCI-SIG, All Rights Reserved 16

Test Points & Vias Minimize via usage Up to 0.25 db loss per via Use via pad size 25 mil, hole size 14 mil; standard anti-pad size of 35 mil Put test points or LAI pads in series (if used) No stubs Place symmetrically Provide GND pads for single-ended probing LAI pads Probe pads GND pads Copyright 2004, PCI-SIG, All Rights Reserved 17

Reference Clock Routing Differential clock routing to each device and connector Use the same differential trace geometries Length matching to different devices NOT required! Clock driver requirements: 100MHz with SSC support (e.g. CK410) Choose low jitter components System board terminations only Clock Driver L1 22-33Ω ±5% Rs L2 1 14 L4 PCI Express Connector 0.5 3.5 PCI Express Card L5 L1' 0.5 max Rs L2' 0 0.2 L3' L3 L4' 0 0.2 L5' Rt Rt 49.9Ω ±1% Copyright 2004, PCI-SIG, All Rights Reserved 19

Connector Layout Connector with standard PTH Connector sizes: x1, x4, x8, x16 Pinout optimized for differential routing & crosstalk reduction Polarity inversion allowed Loss & crosstalk part of system board budget Side B: Tx Improved PTH connector for PCI Express* D- D+ Side A: Rx D+ D- Gnd Gnd Gnd Gnd Gnd= Green TX= Red Rx= Blue Copyright 2004, PCI-SIG, All Rights Reserved 20

Power Rails Increased current capability for x16 connector Additional +12V pin; 1.1 Amp per pin capability Helpful grouping of power supply pins Eases power delivery routing ATX power supply connector 2x12 (recommended) Power Rail +3.3V Voltage Tolerance Current +12V Voltage Tolerance Current +3.3Vaux Voltage Tolerance Current: Wake Non-Wake 75W Slot ± 9% (max) 3.0 A (max) ± 8% (max) 5.5A (max) ± 9% (max) 375 ma (max) 20 ma (max) Copyright 2004, PCI-SIG, All Rights Reserved 21

Power Consumption CEM* Spec 1.1 allows for 75W cards Available for x16 connectors Allows for performance graphics cards 75W can be fully drawn thru x16 connector Note: 25W at initial power-up (75W after configuration as a high power device) Up to 25W allowed for x1, x4, x8 cards Connector Sizes Standard height 10 W 1 (max) X1 x4/x8 x16 25 W (max) 25 W (max) 25 W 1 (max) Low profile card 10 W (max) 10 W (max) 25 W (max) 1. Max at initial power-up only. 75 W (max) PCI Express* spec support for 75W cards Copyright 2004, PCI-SIG, All Rights Reserved 22

Power Delivery Ensure +3.3V & +12V tolerances at add-in card Max of 2%~3% MB +12V voltage drop (e.g. 360mV) Typical power supply = ± 5% drop Balance trace width vs. length Example: 100 mils min trace width, 12 length for +12V with 1oz Cu Proper power decoupling Max current slew rate of 0.1A/µs Suppress high freq coupling noise Tune capacitor type/location to board needs Example uatx +12V layout 2x12 Power Supply Connector Copyright 2004, PCI-SIG, All Rights Reserved 23

Thermal & Acoustic Platforms need to deliver cool air to x16 slot Use side panel vents, ducting 75W card recommendation: 55 o C air temp at graphics card fan intake Use larger fans for better acoustics Cool Air Source Recommended PCI Express* Side Panel Vent Copyright 2004, PCI-SIG, All Rights Reserved 24

Card Retention Card allows for chassis & system board retention Fixed card height & keep outs Hockey-stick near edge fingers 75W Gfx design guideline for retention solution Clip for system board, card hockey-stick Supports up to 350g for 75W cards OEMs free to innovate independent solutions Requires two, 80-mil diameter holes Copyright 2004, PCI-SIG, All Rights Reserved 25

Power Delivery - 150W support Additional 2x3 power supply connector on graphics card for +12V Separate power planes from x16 connector s +12V planes on the graphics card Graphics card should meet safety certifications Features still being reviewed: Recommended current limiting at input of Voltage Regulators (VR) on graphics card Card tolerance to nominal input voltage variations between +12V rails Refer to PCI Express* High-End Graphics CEM Specifications Copyright 2004, PCI-SIG, All Rights Reserved 26

Card Retention - 150W support Card may use the space of adjacent slot Additional retention required for cards > 350 grams Hockey Stick feature on card is required on 75W cards but optional for High End Graphic cards. Ergonomic issue with double wide card. Limited access to release lever High End Graphics Spec support 150W cards Copyright 2004, PCI-SIG, All Rights Reserved 27

Card Edge Fingers Remove ref plane under edge finger pads Better impedance match PRSNT1#, PRSNT2# Pins Layer 2 Ref Plane 1mm shorter: last-mate, first break Hot-Plug support Multiple PRSNT2# pins (x4,x8,x16 cards) Cards must strap PRSNT1# with furthest PRSNT2# signal System board Hot-Plug support optional Outer Layer Differential Pair Signal Traces Layer 3 Ref Plane PRSNT1# to PRSNT2# Strapping Example Outer Layer Edge Fingers Copyright 2004, PCI-SIG, All Rights Reserved 29

Card Physical Dimensions End bracket Top edge keep out and fixed height to enable chassis level retention solutions Hockey-stick to allow for new retention solutions Fixed height for I/O cards (allowance for low profile compliance) Chamfer tolerance ±5 degree Copyright 2004, PCI-SIG, All Rights Reserved 30

Card Thermal & Acoustic Limit heat re-circulated thru Gfx card heat sink Use shroud to separate fan intake and heat sink exhaust Place fan intake near air source- direct away the exhaust Reduce fan noise and low speed chatter Use diode and/or thermister for fan speed control cool air source (e.g. from chassis vent) intake shroud exhaust exhaust Copyright 2004, PCI-SIG, All Rights Reserved 31

Card Thermal - 150W support Exhaust flow of graphic card needs to be managed Recommended that exhaust from graphic card exit to outside of typical ATX Chassis Recommended that graphic card manufacturer and system integrator work together to insure overall system performance Copyright 2004, PCI-SIG, All Rights Reserved 32

Compliance Measurements PCI Express* devices generate compliance pattern per spec Signal validation using: Compliance Base Board (CBB) for add-in cards Compliance Load Board (CLB) for system boards Eye diagrams w/ real-time scope 6+ GHz analog bandwidth 20+ Gs sampling bandwidth SIGTEST analysis software PCI Express* connector CBB Example CLB Example Copyright 2004, PCI-SIG, All Rights Reserved 34

Results Analysis Probe locations TX outputs w/ SMA cables (50Ω terminations at scope) SIGTEST software Create transition bit eye Create de-emphasized eye Pass/Fail: Max median-to-peak jitter Min eye voltage margin (high/low) Validate eye diagrams using real time scope Copyright 2004, PCI-SIG, All Rights Reserved 35

Summary PCI Express* point-to-point layout is straightforward Manage loss and jitter from PCB to meet CEM* interconnect budget Follow basic layout rules and design tradeoffs to implement typical topologies Improved system & add-in card features for 75W & 150W cards support Validate compliance eye diagrams using compliance boards and real-time scope Copyright 2004, PCI-SIG, All Rights Reserved 37

Collateral Intel Developer Network for PCI Express* http://www.express-lane.org/ Where attendees may get additional and updated information on PCI Express* http://www.pcisig.org Copyright 2004, PCI-SIG, All Rights Reserved 38

易迪拓培训专注于微波射频天线设计人才的培养网址 :http://www.edatop.com 射频和天线设计培训课程推荐易迪拓培训 (www.edatop.com) 由数名来自于研发第一线的资深工程师发起成立, 致力并专注于微波射频天线设计研发人才的培养 ; 我们于 2006 年整合合并微波 EDA 网 (www.mweda.com), 现已发展成为国内最大的微波射频和天线设计人才培养基地, 成功推出多套微波射频以及天线设计经典培训课程和 ADS HFSS 等专业软件使用培训课程, 广受客户好评 ; 并先后与人民邮电出版社电子工业出版社合作出版了多本专业图书, 帮助数万名工程师提升了专业技术能力客户遍布中兴通讯研通高频埃威航电国人通信等多家国内知名公司, 以及台湾工业技术研究院永业科技全一电子等多家台湾地区企业易迪拓培训课程列表 :http://www.edatop.com/peixun/rfe/129.html 射频工程师养成培训课程套装该套装精选了射频专业基础培训课程射频仿真设计培训课程和射频电路测量培训课程三个类别共 30 门视频培训课程和 3 本图书教材 ; 旨在引领学员全面学习一个射频工程师需要熟悉理解和掌握的专业知识和研发设计能力通过套装的学习, 能够让学员完全达到和胜任一个合格的射频工程师的要求课程网址 :http://www.edatop.com/peixun/rfe/110.html ADS 学习培训课程套装该套装是迄今国内最全面最权威的 ADS 培训教程, 共包含 10 门 ADS 学习培训课程课程是由具有多年 ADS 使用经验的微波射频与通信系统设计领域资深专家讲解, 并多结合设计实例, 由浅入深详细而又全面地讲解了 ADS 在微波射频电路设计通信系统设计和电磁仿真设计方面的内容能让您在最短的时间内学会使用 ADS, 迅速提升个人技术能力, 把 ADS 真正应用到实际研发工作中去, 成为 ADS 设计专家... 课程网址 : http://www.edatop.com/peixun/ads/13.html HFSS 学习培训课程套装该套课程套装包含了本站全部 HFSS 培训课程, 是迄今国内最全面最专业的 HFSS 培训教程套装, 可以帮助您从零开始, 全面深入学习 HFSS 的各项功能和在多个方面的工程应用购买套装, 更可超值赠送 3 个月免费学习答疑, 随时解答您学习过程中遇到的棘手问题, 让您的 HFSS 学习更加轻松顺畅课程网址 :http://www.edatop.com/peixun/hfss/11.html `

易迪拓培训专注于微波射频天线设计人才的培养网址 :http://www.edatop.com CST 学习培训课程套装该培训套装由易迪拓培训联合微波 EDA 网共同推出, 是最全面系统专业的 CST 微波工作室培训课程套装, 所有课程都由经验丰富的专家授课, 视频教学, 可以帮助您从零开始, 全面系统地学习 CST 微波工作的各项功能及其在微波射频天线设计等领域的设计应用且购买该套装, 还可超值赠送 3 个月免费学习答疑课程网址 :http://www.edatop.com/peixun/cst/24.html HFSS 天线设计培训课程套装套装包含 6 门视频课程和 1 本图书, 课程从基础讲起, 内容由浅入深, 理论介绍和实际操作讲解相结合, 全面系统的讲解了 HFSS 天线设计的全过程是国内最全面最专业的 HFSS 天线设计课程, 可以帮助您快速学习掌握如何使用 HFSS 设计天线, 让天线设计不再难课程网址 :http://www.edatop.com/peixun/hfss/122.html 13.56MHz NFC/RFID 线圈天线设计培训课程套装套装包含 4 门视频培训课程, 培训将 13.56MHz 线圈天线设计原理和仿真设计实践相结合, 全面系统地讲解了 13.56MHz 线圈天线的工作原理设计方法设计考量以及使用 HFSS 和 CST 仿真分析线圈天线的具体操作, 同时还介绍了 13.56MHz 线圈天线匹配电路的设计和调试通过该套课程的学习, 可以帮助您快速学习掌握 13.56MHz 线圈天线及其匹配电路的原理设计和调试详情浏览 :http://www.edatop.com/peixun/antenna/116.html 我们的课程优势 : 成立于 2004 年,10 多年丰富的行业经验, 一直致力并专注于微波射频和天线设计工程师的培养, 更了解该行业对人才的要求经验丰富的一线资深工程师讲授, 结合实际工程案例, 直观实用易学联系我们 : 易迪拓培训官网 :http://www.edatop.com 微波 EDA 网 :http://www.mweda.com 官方淘宝店 :http://shop36920890.taobao.com 专注于微波射频天线设计人才的培养易迪拓培训官方网址 :http://www.edatop.com 淘宝网店 :http://shop36920890.taobao.com